JPH08137739A - Memory access controller - Google Patents

Abstract

PURPOSE: To process an access request at high speed by preferentially processing the access of high priority by means of allocating the access request of high time restriction as the access request of high priority. CONSTITUTION: When a high priority access generation signal 106 is inputted, an access processing part 107 transfers the access request of high priority 104 to a memory controller 108 as the access request 109. When the memory controller 108 receives the access request 109, it outputs a bank selection signal 112 to synchronous DRAM 111 when access under processing at present exists and the access request is for a bank different from the access. A read/write signal 112 is outputted when data input/output 113 is terminated while previous access is processed, and the signal is continuously outputted if it is not. Then, a signal 110 notifying that next access can be received is outputted to the access processing part 107. Thus, the access request can be processed at high speed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory access control device which is effective in accelerating a plurality of access requests including high-priority access to a multi-bank memory in image processing.

[0002]

2. Description of the Related Art Conventionally, in general memory access for processing a plurality of accesses, access control for accumulating and processing access requests has been used. FIG. 4 shows a conventional memory access control device. In FIG. 4, 4
01, 402, and 403 are memory access requests, 404 is an access reception queue that queues the access requests 401, 402, and 403, 405 is the first access request of the access reception queue 404, and 406 is an access processing unit that processes the access request 405. , 407 is a memory, 408 is a signal for controlling the memory 407, and 409 is a data input / output of the memory 407.

In the conventional memory access control device, access requests 401, 402, 403 from the outside are stored in the access reception queue 404, and are passed to the access processing unit 406 as an access request 405 on a first-come-first-served basis. When the access processing unit 406 receives the access request 405,
An access signal (read / write signal) is output to the memory 407, and after the access is completed (data input / output 40
9), the next access request 405 is received, and the access request 405 is processed.

[0004]

However, there are a plurality of access requests including highly time-limited access such as display and capture of an image that needs to be processed within a fixed time with respect to a memory having a multi-bank structure in image processing. When access is performed, the time from access request generation to access processing depends on the processing time of the access that occurs before that access and is not processed, so it is possible that an access with a high time constraint cannot be processed within the constraint time. There was a problem of having.

The present invention solves the above-mentioned problems of the prior art, in which a plurality of access requests including highly time-limited access such as display and capture of images that need to be processed within a certain time in image processing are requested. When processing, access requests with high time constraints are given high priority and are processed preferentially, and individual access is pipelined using the characteristics of the memory with a multi-bank configuration. The purpose is to speed up access processing.

[0006]

In order to achieve this object, a memory access control device of the present invention preferentially accepts an access request having a higher priority among a plurality of access requests, and requests access by inputting an access acceptance signal. An access acceptance unit that outputs a bank selection signal, a read / write signal, and a data input / output unit, and an access request output from the access acceptance unit that receives the bank selection signal. And a memory controller that outputs the read / write signal to the multi-bank configuration memory at the end of the previous access and outputs the access acceptance signal to the access acceptance unit.

[0007]

With this configuration, when performing image processing, priority access requests with high time constraints and high priority are processed preferentially, and individual access requests are processed by utilizing the characteristics of the multi-bank memory. Pipeline.

Since the memory access control device as described above is provided, when performing image processing, priority is given to access requests with high time constraints such as display and capture of images that need to be processed within a fixed time. Can be processed efficiently and individual access requests can be processed at high speed. When applied to memory access control in image processing, high-priority access requests can be processed at high speed, and individual access requests can also be processed at high speed. It is possible to realize an excellent memory access control device.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram of a memory access control device showing a first embodiment of the present invention.

In FIG. 1, 101, 102 and 103 are low priority access requests, 104 is a high priority access request, and 105 is a low priority access request 101,
An access acceptance queue for queuing 102 and 103, a high-priority access generation signal 106 for notifying the generation of an access request 104 having a high priority, and 107 selecting either the access acceptance queue 105 or the access request 104 having a high priority. Access processing unit 108
Is a memory controller, 109 is an access processing unit 107
The access request selected by, 110 is a signal for notifying the access processing unit 107 that the memory controller 108 can accept the next access request, 11
Reference numeral 1 is a two-bank synchronous DRAM, 112 is a signal for controlling the synchronous DRAM 111, and 113 is a data input / output of the synchronous DRAM 111.

In the memory access control device having the above configuration, the access requests 101, 1 with low priority are given.
02 and 103 are access acceptance queues 105 in the order of arrival.
Is queuing in. Further, the high-priority access request 104 inputs the high-priority access generation signal 106 to the access processing unit 107 prior to generation. The access processing unit 107 sets the access request 104 having a high priority as the access request 109 when the high priority access generation signal 106 is input when the signal 110 is input.
When the high-priority access generation signal 106 is not input, the head access request of the access acceptance queue 105 is set as the access request 109 and the memory controller 1
Pass it to 08.

When receiving the access request 109, the memory controller 108 issues a bank selection signal 112 to the synchronous DRAM 111 if there is an access currently being processed and the access request is for a bank different from the access. Access processing is being performed, the read / write signal 112 is continuously output at the end of the data input / output 113.
A signal 110 for notifying that the next access can be accepted is output to 07.

If the access currently being processed and the input access request 109 are access requests for the same bank, a bank selection signal 112 is output to the synchronous DRAM 111 after the end of the access request currently being processed, Then, the read / write signal 112 is output, and the signal 110 for notifying that the next access can be accepted is output to the access processing unit 107.

With the above-mentioned operation, the processing is performed while performing the two-stage pipeline processing. The high-priority access generation signal 106 is generated while the high-priority access request 104 is generated. That is, when a plurality of high priority access requests 104 are successively generated, the high priority access generation signal 106 is input to the access processing unit 107 while the entire plurality of access requests are processed. Continued, high-priority access request 1
04 can be processed preferentially.

By the series of operations described above, priority is given to access requests with high time constraints such as display and capture of images that need to be processed within a fixed time when drawing, displaying and capturing during image processing. High-priority access requests, high-priority access can be preferentially processed, and synchronous DRAM
Each access request can be processed at high speed by performing the two-stage pipeline processing using the bank structure of.

A second embodiment of the present invention will be described below with reference to the drawings. FIG. 2 is a block diagram of a memory access control device showing a second embodiment of the present invention.

In FIG. 2, 201, 202 and 203 are low priority access requests, 204 is a high priority access request and 205 is a low priority access request 201.
202 and 203 and an access acceptance queue for queuing the access request 204 with the highest priority, 206 is an access request selected from the access acceptance queue 205, and 207 is the access request queue 205 that selects and outputs the highest priority access. An access processing unit, 208 is a memory controller, 209 is an access request selected by the access processing unit 207, 210 is a signal notifying the access processing unit 207 that the memory controller 208 can accept the next access request, 211 Is a two-bank synchronous DRAM,
212 is a signal for controlling the synchronous DRAM 211,
Reference numeral 213 is a data input / output of the synchronous DRAM 211.

In the memory access control device having the above configuration, the operation of the memory controller 208 is the same as that of the memory controller 108 in the first embodiment, except that the access acceptance queue 205 and the access processing unit 207 are different. It is an action. Access requests 201, 2
02, 203, and 204 are queued in the access reception queue 205 in the order of arrival. Access processing unit 207
When the signal 210 from the memory controller 208 is input, when the access request queue 205 has a high priority access request 204, the high priority access request 204 is received as the access request 206, and When there is no access request 204 with high priority, access requests 201, 202, 20 with low priority
The access request that arrives earliest among the three is selected, received as the access request 206, and output to the memory controller 208 as the access request 209. That is, the access request 204 having a high priority is always processed first when it arrives at the access reception queue 205.

By assigning an access request having a high time constraint as an access request having a high priority by the above series of operations, the access request having a high priority can be preferentially processed, and each access request can be processed at high speed. Can be processed.

In both the first embodiment and the second embodiment, the access processing unit 107 in the memory controller is used.
When the access request input from 207 and 207 is in the same bank as the access currently being processed, the access processing is started after the end of the access request currently being processed, so that the pipeline processing collapses and the access processing is delayed. When the access requests 201, 202, 203, and 204 arrive at the access acceptance queue 205, information on the data length of each access is also input, so that the access processing unit can avoid continuous access to the same bank. By selecting the access request, it is possible to predict the end time of each access request and avoid continuous access to the same bank, so that the access request can be processed at higher speed.

In both the first embodiment and the second embodiment, the access processing unit 107 in the memory controller is used.
When the access request input from 207 and 207 is in the same bank as the access currently being processed, the access processing is started after the end of the access request currently being processed, so that the pipeline processing collapses and the access processing is delayed. , Fig. 3
As described above, the memory controller 302 adds an access acceptance disabling signal 305 to the access processing unit 301, and the memory controller 302 receives the access request 30
If 3 is an access to the same bank as the access currently being processed, the access refusal signal 305 is output to the access processing unit 301, and the access processing unit 301 is requested to select an access request again. Select the access request 303 and select the memory controller 302
Since it is possible to avoid continuous access to the same bank, the access request can be processed at a higher speed.

[0022]

As described above, according to the present invention, an access requesting unit which preferentially receives an access request having a higher priority among a plurality of access requests, outputs an access request by inputting an access acceptance signal, and a bank selection signal. A multi-bank configuration memory that receives a read / write signal and inputs / outputs data, and a multi-bank configuration memory that receives an access request, which is an output of the access acceptance unit, outputs the bank selection signal to the multi-bank configuration memory and ends the multi-bank configuration at the end of the previous access. By providing a memory controller that outputs the read / write signal to the bank configuration memory and outputs the access acceptance signal to the access acceptance unit, access with a high time constraint such as image display and capture during image processing is performed. Requests can be processed with priority and individual access requests can be processed at high speed. To be, if applied to a memory access control in the image processing, to process the high priority access request at a high speed, each access request is also what can realize a memory access control device excellent that can be processed at high speed.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a memory access control device according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a memory access control device according to a second embodiment of the present invention.

FIG. 3 is a diagram showing complementary operations of an access processing unit and a memory controller of each embodiment.

FIG. 4 is a block diagram of a conventional memory access control device.

[Explanation of symbols]

 101, 102, 103 Low-priority access request 104 High-priority access request 105 Access acceptance queue 106 High-priority access generation signal 107 Access processing unit 108 Memory controller 109 Selected access request 110 Notification signal 111 Synchronous DRAM 112 Control signal 113 Data input / output 201, 202, 203 Low priority access request 204 High priority access request 205 Access acceptance queue 206 Selected access request 207 Access processing unit 208 Memory controller 209 Selected access request 210 Notification signal 211 Synchronous DRAM 212 Control signal 213 Data input / output 301 Access processing unit 302 Memory controller 303 Access request 304 Notification signal 3 05 Access denial signal

Claims (5)

[Claims] 1. An access acceptance unit that preferentially accepts an access request having a higher priority among a plurality of access requests, outputs an access request by inputting an access acceptance signal, receives a bank selection signal and a read / write signal, and inputs data. The multi-bank configuration memory to be output, and the access request output from the access acceptance unit are received, the bank selection signal is output to the multi-bank configuration memory, and the read / write signal is sent to the multi-bank configuration memory at the end of the previous access. And a memory controller that outputs an access acceptance signal to the access acceptance unit. 2. An access reception unit, which serves as an access reception unit, stores an access request having a plurality of low priority access requests, a high priority access generation signal for notifying the generation of a high priority access request, and the high priority access generation signal. When an input request is received, only an access request with a high priority is accepted, and when an input request is not input, the access request stored in the access acceptance queue is accepted and an access request is output by inputting an access acceptance signal. The memory access control device according to claim 1, further comprising a section. 3. An access reception unit, which stores a plurality of access requests, and an access processing unit which selects an access request having a high priority from the access reception queue and outputs the access request when an access reception signal is input. The memory access control device according to claim 1, further comprising: 4. The access processing unit as an access receiving unit, comprising an access processing unit for receiving an access data length when an access request is generated, rearranging the data, and outputting the access request by inputting an access reception signal. Memory access control device. 5. As a memory controller, when an access request input from the access accepting unit cannot be processed immediately, an access accept disabling signal is output to the access accepting unit, the access request is selected again, and the access accept signal is accessed again. The memory access control device according to claim 1, further comprising a memory controller that outputs the request to the reception unit and receives the access request again.