JP2002082901A - Bus controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a bus controller capable of reducing the deterioration of shared bus access performance due to a writing queue generated in a posted write system to such a level or below that no problem will occur. SOLUTION: When a reading request is issued after a writing request is issued from a master 11 to a resource 42 in a period that a shared bus 50 is occupied by a master 12, a writing detecting device 61 detects the reading request, and a reading generating device 71 inserts a dummy reading request following the writing request based on this detection. Thus, any writing request queue can be prevented from being jammed in a writing buffer 31. Therefore, the reading request is allowed to immediately reach the resource 42, and the cycle is quickly ended so that even when any access request from the master 12 to the resource 41 is present in that period, the processing can be executed without being left waiting.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a bus control device in a control device such as an industrial programmable controller device.

[0002]

2. Description of the Related Art Among microprocessor application apparatuses, there are apparatuses employing a multi-master system configuration which employ a shared bus such as a PCI bus system.

In a shared bus having a plurality of masters,
Keeping the bus occupied by a particular master significantly reduces the processing efficiency of other masters, and consequently the efficiency of the entire system. For this reason, it is important to configure the bus so that a specific master does not occupy the bus as much as possible. As a method for improving the bus efficiency, there is a method called posted write or delayed write.

In this method, a write request issued on a shared bus is temporarily stored in a buffer, and writing is performed when the bus is free. At this time, the master completes the access when the write request is stored in the buffer,
Regardless of the occupation state of the bus, the next process can be started, so that the bus efficiency is improved.

FIG. 4 shows a conventional configuration example of such a bus control device. In the figure, 11 and 12 are master, 2
Numerals 1 and 22 denote bus interfaces, 31 and 32 denote write buffers, 41 and 42 denote resources such as memories, 50 denotes a shared bus, and 51 and 52 denote local buses.

FIG. 5 shows an example of this conventional operation in the form of a time chart. In the figure, 100 indicates a write request from the master 11 to the resource 42, 101 indicates a read request from the master 11 to the resource 42, and 102 indicates the master 12 occupying the shared bus.

This operation will be described. First, the master 12 occupies the shared bus. During this occupation period 102, the master 11 issues a write request 100 continuously to the resource 42, and then the master 11 issues a read request 101 to the resource 42.
Is issued.

When the master 11 issues the read request 101, a queue of the write request 100 is generated in the write buffer 31, and the read request 101 is not completed unless this queue is canceled, resulting in a long access cycle.

At this time, the local bus 51
Therefore, even if there is a write or read access request from the master 12 to the resource 41, the access request of the master 12 is also kept waiting until the read request 101 of the master 11 is completed. become. (In FIG. 5, the resources 41
The write or read access request to the master 11 is kept waiting until the point a at which the read request 101 of the master 11 is completed, even if retry is repeated. )

[0010]

As described above, in the conventional posted write system, several write requests are stored in a buffer and a write queue is generated, but read requests are issued to the same address or the same resource. In such a case, all the write queues are cleared and a read request is made.

At this time, the master that has issued the read request remains in a waiting state while the write queue is cleared and the read request is being processed.

At this time, if another master issues a read request to the resource managed by the master in the waiting state, the master waits further until the waiting state of the previous master is resolved.

When this situation is repeated, the problem that the period during which all masters on the system cannot operate at all increases, cannot be ignored.

In a real-time control system, if there is a moment when the performance is extremely reduced, there is a danger that control discontinuity may occur or information may be leaked.

Therefore, it is important to solve this problem.

The present invention has been made in view of such a conventional problem, and reduces the shared bus access performance caused by the write queue generated in the posted write system.
It is an object of the present invention to provide a bus control device that can be suppressed to a level at which no problem occurs.

[0017]

According to the present invention, there is provided a bus control having a multi-master function, wherein a write operation of a master is temporarily stored in a buffer so that a write operation can be delayed. In the device, when the write request stored in the buffer reaches a predetermined depth,
A means for issuing a read request following a write request is provided.

That is, according to the present invention, as a method for limiting an extremely lowering of the processing capability caused by the write queue, means for limiting the depth of the write queue is provided. This is accomplished by means for issuing a dummy read request when the write queue has reached a certain depth.

When the above read request is issued, the write queue operates so as to be immediately released. The worst wait time at this time can be limited by the set depth of the write queue and the number of masters that can issue access to the shared bus, regardless of the capacity of the buffer storing the write queue.

According to a second aspect of the present invention, in the bus control device of the first aspect, the means for issuing a read request subsequent to the write request includes a write request detecting device for detecting a master write request; And a read request issuing device for issuing a read request following the write request based on the detection result of the write request detecting device.

That is, in the present invention according to the second aspect, as a method for realizing a dummy read request in the bus control device according to the first aspect, an apparatus for detecting a write request and a request for a master are provided. A device capable of issuing a read request as needed is provided.

In this configuration, when a write request is detected,
Issuing a read request as needed automatically eliminates the write queue, thereby avoiding a situation where the write queue becomes dangerously deep.

[0023]

Embodiments of the present invention will be described below in detail with reference to the drawings. In the following drawings, the same reference numerals indicate the same or corresponding portions, including those showing the configuration and operation of the conventional example.

FIG. 1 shows the configuration of an embodiment of the bus control device according to the present invention.

As shown in FIG. 1, one embodiment of the present invention may include write detectors 61 and 62 and read generators 71 and 72 as compared with the conventional configuration shown in FIG. It is a feature. In FIG. 1, 53 and 54 indicate write detection signals.

In the minimum configuration required in the present embodiment, the write detecting device 62 and the read generating device 72 are omitted as shown in FIG. In this case, the effect of the present embodiment can be obtained only for access from the master 11.

FIG. 3 shows the operation of this embodiment in the form of a time chart. In the figure, reference numeral 103 denotes a read request from the read generator 71.

This operation will be described. First, the master 12 occupies the shared bus. During this occupation period 102, the master 11 issues a write request 100 continuously to the resource 42, and then the master 11 issues a read request 101 to the resource 42.
Is issued.

As described above, in the conventional operation example, when the read request 101 of the master 11 is issued as shown in FIG.
A queue of write requests 100 is generated in the write buffer 31, and the read requests 101 are not completed unless the queues are cleared, resulting in a long access cycle. At this time, since the local bus 51 is occupied by the read request 101 of the master 11, even if there is a write or read access request to the resource 41 from the master 12, the read request 101 of the master 11 is not completed. The access request from the master 12 is also waited.

On the other hand, in the present embodiment, when a write request 100 to the resource 42 is issued from the master 11, the write detection device 61 detects this, and outputs a write detection signal 53 to the read generation device 71 to read the data. Since the generator 71 issues a dummy read request 103 to the resource 42 based on the write detection signal 53, the dummy read request 103 of the read generator 71 is always inserted after the write request 100 of the master 11. . Therefore, the queue of the write request 100 does not accumulate in the write buffer 31.
Read request 10 of master 11 following write request 100
1 and a dummy read request 1 following the write request 100
03 immediately reaches the resource 42 upon issuance, and the cycle is immediately terminated. Therefore, even if there is a write or read access request from the master 12 to the resource 41 during this period, the master 12 access request There is no waiting. (In FIG. 3, a write or read access request from the master 12 to the resource 41 repeats the retry, but becomes accessible at the time point b.)
The dummy read request 1 from the read generator 71
03 may be issued every time the issuance of the read request 101 is detected, but may be issued when the write request 100 stored in the write buffer 31 reaches a predetermined depth. In this case, the worst wait time can be limited by the set depth of the write queue and the number of masters that can issue access to the shared bus 50 regardless of the capacity of the write buffer 31 that stores the write queue. it can. It is preferable that the larger the number of masters, the smaller the write queue to be set.

As described above, according to the present embodiment, generation of a write queue in the write buffer 31 due to a continuous write request from the master 11 to the resource 42 can be suppressed. There is an effect that it is possible to limit the waiting time when accessing the L. 41 to a certain limit.

In the above description, the operation in the case where the master 11 issues the write request 100 to the resource 42 continuously and then issues the read request 101 from the master 11 to the resource 42 has been described. 12 continuously issues write requests to the resource 41, and then the master 1
The same operation is performed when a read request is issued from the second to the resource 41.

In the above embodiment, when the write request stored in the write buffer reaches a predetermined depth, the write detectors 61 and 62 and the read detector are used as means for issuing a read request following the write request. Although the generators 71 and 72 are provided, these write detectors 61,
Instead of providing the 62 and the read-out generators 71 and 72, it is also possible to provide software means in the masters 11 and 12 so as to execute them.

[0034]

As described above, the problem that the shared bus access performance is extremely reduced due to the write queue generated in the posted write system is reduced to a level below which no problem occurs by applying the present invention. Can be suppressed.

Therefore, in a real-time control system such as a programmable controller, by applying the present invention, it is possible to avoid the possibility that a moment at which the performance is extremely reduced may be avoided, so that there is an effect that stable control can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a minimum configuration in an embodiment of the present invention.

FIG. 3 is a time chart showing an operation state in one embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a conventional example.

FIG. 5 is a time chart showing an operation state of a conventional example.

[Explanation of symbols]

 11, 12 Master 21, 22 Bus interface 31, 32 Write buffer 41, 42 Resource 50 Shared bus 51, 52 Local bus 53, 54 Write detection signal 61, 62 Write detector 71, 72 Read generator 100: Write request from master 11 to resource 42 101: Read request from master 11 to resource 42 102: Shared bus occupation of master 12 103: Read request by read generator 71

Claims (2)

[Claims] In a bus control device having a multi-master function and capable of delaying a write operation by temporarily storing a write request of a master in a buffer, a write request stored in a buffer has a predetermined depth. A bus control device comprising: means for issuing a read request following a write request when the number of times has reached. A means for issuing a read request following the write request; a write request detecting device for detecting a master write request; and a read request following a write request based on a detection result of the write request detecting device. 2. The bus control device according to claim 1, further comprising: a read request issuing device for issuing a request.