JPH0793905A - Digital signal recording/reproducing format - Google Patents

Abstract

PURPOSE:To improve reliability in the detection of a sector address of an ID part and of reproduction data by building up the ID part and a data part composing a sector with a plurality of frames. CONSTITUTION:A digital signal is recorded or reproduced by the unit of sector. The sector is made up of a plurality of frames divided equally and an ID part made up one or a plurality of frames. At the same time. a data part is made up of a specified number of frames and a frame mark is arranged at the head of the frames.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal recording / reproducing format, and more particularly to a format for recording / reproducing a digital signal in sector units.

[0002]

2. Description of the Related Art A device for recording / reproducing a digital signal in sector units, such as an optical disk data file device. In the optical disk data file device, the sector structure is composed of an ID part and a data part.
There is a sector format standardized by C DIS 10090. The sector format and the data section format are shown in FIGS. Here, regarding the data part, the RS (resync (1 to 39)) is the data 15B.
It exists every time, and the data is read while synchronizing with the reproduction. However, as for the ID part, RS existing in 15B cycle or other RS like the data part
There is no mark corresponding to.

Therefore, at the time of reproduction, S indicating the beginning of the data part is obtained.
When the YNC (synchronization) mark (SB1, SB2, SB3) is missed, it is necessary to interpolate the SYNC mark by some method and read the data. As a method,
There is a method of interpolating the SYNC mark detection signal from the SM detection signal or the SYNC mark detection signal of the previous sector. In other words, it is a method of predicting from some previously detected signal and outputting the prediction signal to the position to be detected.

[0004]

However, if there is a large time difference between the previously detected signal and the predicted signal, there is a problem that the circuit scale increases or the reliability decreases. It was

Further, when the RS detection signal in the data part is not output, it is predicted and interpolated from the SYNC detection signal or the previous RS detection signal, but the ID part originally has a periodic RS signal like the RS signal. There is no mark corresponding to. Therefore, it is necessary to stop the interpolation in the ID section, and it is necessary to switch between the data section and the ID section, which causes a problem that the interpolation method becomes complicated.

The present invention solves the above-mentioned drawbacks, and easily performs the interpolation method when a specific mark such as an RS signal is erroneously detected, and records or reproduces a digital signal which can improve reliability. It is intended to provide a format.

[0007]

In order to achieve this object, the present invention is configured such that a sector is composed of a plurality of frames, a frame interval is the same period, and an FM (frame mark) is arranged at the beginning of the frame. The ID part is composed of one or more frames, and the data part is composed of a predetermined number of frames.

[0008]

Since the frame marks are periodically present, interpolation or removal is performed when the frame mark detection signal is not detected for some reason or when the frame mark is detected at a position other than the position where it should be detected. Is realized with a very simple circuit configuration, and reliability is improved.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. 1 (A), FIG. 1 (B), and FIG.
The sector format, ID section format, and data section format are shown respectively.

As shown in FIG. 1A, one sector has 6
It is composed of 2 frames, the ID part is 2 frames, and the data part is 60 frames. The frame mark (FM) has a regular interval. In addition, as shown in FIG.
Frames 1 and 2 of the ID section each have an ID mark (ID
M), preamble (PR), address mark (A
M), a sector address (SA), an error check code (CRCC), and a postamble (PO). That is, the ID part is double-written, which improves the reliability of the ID part detection. The ID part may be written once or tripled.

The IDM is for the purpose of distinguishing the ID part from the data part and for the purpose of indicating the head position of the ID part. PR and PO are repeated patterns in which the same number of 0s and 1s continues. For example, a pattern consisting of a specific 0 or 1 which does not exist in the data part and is different from the frame mark is preferable. AM exists at the beginning of SA, and indicates that SA follows. CRCC is a code for detecting that there is a bit error in the sector address.

In the data section, as shown in FIG. 2, frames are arranged in the vertical direction and one frame consists of 48B data. Frames 3 to 54 are composed of 40B main data and 8B error correction parity. The frames 55 to 62 are composed of 48B ECC parity. However, one frame of data is 48B
Does not have to be. As described above, the ID part and the data part are composed of frames of the same cycle.

Although the number of frames in one sector is 62 in the embodiment, it does not have to be 62 and is arbitrary.

Further, it is preferable that the frame mark is composed of a pattern of only 0 or 1 which does not exist in the ID part and the data part, or a pattern consisting of a specific 0 or 1.

[0015]

As described above, according to the present invention, since the frame mark is periodically present, if the frame mark detection signal is not detected for some reason, or a place other than the position where the frame mark should be detected. If it is detected in step 1, interpolation or removal can be realized with a very simple circuit configuration without distinguishing between the ID part and the data part.

Further, since the circuit structure does not need to be switched between the ID part and the data part, the reliability is improved. As a result, the reliability of sector address detection in the ID part,
And the reliability of data detection is improved.

[Brief description of drawings]

FIG. 1 is a diagram showing a sector format according to an embodiment of the present invention.

FIG. 2 is a diagram showing a data part format according to an embodiment of the present invention.

FIG. 3 is a diagram showing a sector format in a conventional example.

FIG. 4 is a diagram showing a data section format in a conventional example.

Claims (3)

[Claims] 1. An apparatus for recording or reproducing information on a sector-by-sector basis, wherein the sector is composed of an ID section indicating a physical position of a sector on a storage medium and a data section for recording or reproducing information as a digital signal. In format,
The sector is composed of a plurality of equally divided frames,
The ID part is composed of one or more frames,
The digital signal recording / reproducing format is characterized in that the data portion is composed of a predetermined number of frames, and a frame mark is arranged at the head of the frame. 2. The digital signal recording / reproducing format according to claim 1, wherein the frame mark is composed of a pattern of only 0s or 1s not existing in the ID part and the data part or a pattern consisting of specific 0s or 1s. . 3. The digital signal according to claim 1, wherein the ID part has an ID mark which is not present in the data part and which is composed of a specific 0 or 1 pattern different from the frame mark. Signal recording / playback format.