JPH0787398B2 - Spread spectrum receiver - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a spread spectrum receiver, and more particularly to an improvement for detecting the start timing of information data included in demodulated data in the receiver.

[Summary of the Invention] A received pseudo noise code (Pseudo Noise C) included in a received signal.
ode (hereinafter referred to as PN code)) and the reference PN generated at the receiving side
The demodulated data is provided with a correlator that correlates with the code, and the start timing of the information data included in the demodulated data is detected from the output pulse when the demodulated data is given to a pattern determination means such as a matched filter and matches a predetermined determination pattern. Spread spectrum receiver that looks like.

[Prior Art] In spread spectrum communication, as shown in FIG. 9 (a), data is used to modulate a pseudo noise code, which is one of binary codes, and a modulated PN code is used to modulate a carrier wave for transmission. To do. In the figure, 31 is data, 32 is a modulator, 33 is a PN code generator, 34 is a carrier wave generator, 35 is a modulator, and 36 is an antenna. On the receiving side, as shown in FIG. 9 (b), the signal is received, and in the matched filter, the correlation with the reference PN code is taken, and when the two codes match and in the vicinity thereof, they appear relatively. A large amplitude autocorrelation waveform (hereinafter referred to as a correlation spike waveform) is processed to restore the data. In the figure, 37 is an antenna, 38 is a correlator, 39 is a reference PN.
A code generator, 40 is a data demodulator, and 41 is data.

There is a convolver as one of the matched filters. The convolver is a functional element that performs convolutional integration, but if a reference binary signal (hereinafter referred to as a reference code in the present specification) has a time-reversed relationship with the received signal, a matched filter that performs a correlation operation. Becomes

One example of a convolver is the SAW convolver. SAW convolvers are structurally (1) with a gap between the piezoelectric body and silicon, (2) with a piezoelectric body and silicon integrated through an oxide film, and (3) with a piezoelectric body only. , And the like, the non-linear characteristic is used to perform a product operation by the interaction of two signals, and the result is integrated in an electrode called a gate provided on the interaction region.

FIG. 10 is an example showing the structure of a SAW convolver. In the figure, 42 and 43 are transducers, 44 is a piezoelectric body, 45 is an oxide film, 46 is silicon, and 47 is a gate electrode. The signal s (t) input from the transducer 42 propagates to the right in the figure, and the signal input from the transducer 43 propagates to the left. Due to the nonlinear characteristics of the piezoelectric body-oxide film-silicon structure, s (t)
And r (t) interact with each other, a product operation is performed, and the result is integrated by the gate electrode 47.

The signal c (t) output from the gate electrode 47 is expressed by the following equation.

Here, A is a constant, T is a time required for a sound wave to pass under the gate electrode (hereinafter, referred to as an in-gate delay time), x is a distance measured in the propagation direction of s (t), and v
Is the speed of sound.

Generally, a PN code has a fixed period. In the waveform generated by the transmission side, there is often a relationship between one cycle of the PN code and the length of one bit of data. Here, for ease of explanation, the case where one cycle of the PN code and the length of one data bit are equal will be taken as an example.

On the other hand, the relationship between the in-gate delay time and the PN code can be appropriately selected. That is, the delay time in the gate can be shortened, equalized, or lengthened with respect to one cycle of the PN code. The in-gate delay time means an integration section in the correlation calculation. Due to the correlation characteristics of the PN code, it is preferable that the integration interval spans exactly one cycle. Therefore, in this description, the case where the delay time in the gate is equal to one cycle of the PN code will be taken as an example.

The above relationship is shown in FIGS. 11 (a), (b) and (c).
(A) represents data and (b) represents an array of PN codes. In the above example, the length of one data bit and one cycle of the PN code are the same and are equal to 1. (C) is a schematic sectional view of the convolver, and the delay time within the length L of the gate electrode is equal to l. The above is an example for explanation, and the relationship between one data bit, one period of the PN code, and the delay time in the gate can be appropriately selected.

By the way, in actual communication, since it is unknown when the receiving side receives the transmitted signal, the reference signal is input to one of the transducers and stands by to receive the signal. When a signal is received, it is provided by the other transducer to the convolver. When the PN codes contained in the received signal and the reference signal match, a correlative spike waveform is obtained from the gate electrode of the convolver. However, it is completely unknown at what position the two codes match. If the matching positions of both codes are not set correctly,
Data cannot be restored correctly. For example, the 12th
When the two codes match with each other in the form as shown in FIG. 10A, the data bit A is placed on half of the received signal and the data bit B is placed on the other half. The figure represents the array of data bits, the received PN code and the reference PN from the top, the area designated by L representing the inter-use area under the gate electrode. The PN code is a time-reversed version of the PN code A.

As described above, some means must be taken so that no matter which position the received code and the reference code initially match, the received code and the reference code will eventually match at the position as shown in FIG. 12 (b). . In this way, the period from the reception of the signal to the coincidence of the codes at the position shown in FIG. 12 (b) is called initial synchronization.

If the clock frequency of the received PN code and the clock frequency of the reference PN code are different after the initial synchronization is established and the arrangement is as shown in FIG. 12 (b), the arrangement of FIG. 12 (b) is used. The positions where they coincide gradually shift from. The difference is the received PN
Each time the code and the beginning of the reference PN code meet, Is represented. Where f _r is the reference PN code clock frequency, f _t is the received PN code clock frequency, and N is the PN code 1
It is the number of chips that make up the cycle.

That is, even if the initial synchronization is established, if the clock frequencies of the codes are different, the coincident position is gradually displaced from the correct position, and the data cannot be demodulated. This means that the same clock frequency must be prepared on the transmitting side and the receiving side in order to eliminate the "deviation". Generally, a crystal oscillator is used as the clock oscillator, but it is extremely difficult to manufacture multiple crystals that oscillate at exactly the same frequency, and the environment such as temperature and humidity is extremely accurate. There are drawbacks such as having to be controlled.

Therefore, in order to improve the above-mentioned drawbacks, a pulse (hereinafter referred to as a correlation pulse) is generated by signal processing the correlation spike, and the reference PN code is initialized (reset) by the correlation pulse, thereby eliminating one of the two PN codes. The method of matching the pattern in the period on the correlator to perform the initial synchronization is also
For example, it is proposed in Japanese Patent Application No. 59-77789 (Japanese Patent Publication No. 1-24174).

[Problems to be Solved by the Invention] After initial synchronization is achieved by the above method, it is necessary to correct the phase error of the patterns of both codes due to the code clock frequency error between the two codes, that is, to maintain synchronization. Yes,
According to the above method, the phase error is kept synchronous by extracting the correlation pulse obtained each time both codes match on the correlator with the gate pulse at a desired timing and initializing the reference PN code.

However, in such a conventional method, a method for detecting the start timing of the information data included in the demodulated data has not been established, which is a problem. Therefore, an object of the present invention is to provide a means by which an external circuit can easily detect the start timing of information data included in demodulated data in a spread spectrum receiver.

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a correlation that correlates a received PN code included in a received signal with a reference PN code included in a reference signal generated on the receiving side. In the spread spectrum receiver that demodulates desired data by the input device, the correlation output of the correlator is input to the initial synchronization determination means, and the reception PN is output by the output when it matches the predetermined initial synchronization determination pattern.
The code and the reference PN code are initially synchronized with each other, and the demodulated data is input to the information data start timing determination means, and the determination output when the predetermined start timing determination pattern is matched is given to the external circuit to provide the above information data. It is characterized in that it is configured to detect the start timing of.

[Operation] The start timing determination means is composed of, for example, a matched filter, and when demodulated data is input and coincides with the determination pattern, a pulse is output and the start timing of the information data can be easily known from this pulse.

[Examples] The present invention will be described below with reference to the examples shown in the drawings.
FIG. 1 shows an embodiment of a spread spectrum receiver according to the present invention, in which 1 is a correlator, 2 is a binarization circuit, 3 is a first matched filter, 4 is an up / down counter, and 5 is a reference PN code generator. , 6 is a sampling pulse and window pulse generator, 7 is a digital phase locked loop circuit, 8 is a PN code phase control pulse generation circuit, 9 is a binary data demodulation circuit, 10
Is a second matched filter.

In FIG. 1, the binarization circuit 2 causes a correlation spike (d) appearing when the received PN code and the reference PN code (h) match in the correlator 1 and in the vicinity thereof to the positive and negative sides of the polarity. The separated correlation pulse (e) is generated. When the pattern of the correlation pulse (e) output from the binarization circuit 2 matches the predetermined determination pattern, the first matched filter 3
Outputs pulse (f) (initial synchronization detection signal).

The up-down counter 4 is initialized by a strobe pulse (re) output from the reference PN code generator 5 and performs up-counting from an offset value (a) set by an external circuit such as a microprocessor. When a pulse (f) is output from the matched filter 3 of (1), it is triggered by this to down-count and generate a borrow pulse (g).

The reference PN code generator 5 outputs a reference PN code (h) and a strobe pulse (i) indicating the head bit thereof based on the initial information (c) of the reference PN code set from an external circuit.

The sampling and window pulse generator 6 outputs a sampling pulse (n) and a window pulse (l) for sampling and extracting the correlation pulse e) output from the binarization circuit 2. The digital phase lock loop circuit 7 holds the received PN code included in the received signal (b) input to the correlator 1 and the reference PN code (h) included in the reference signal in synchronization.

The PN code phase control pulse generation circuit 8 is triggered by the pulses (to) and (wo) output from the up / down counter 4 and the digital phase locked loop 7 to generate the phase control pulse (yo) of the reference PN code (h). Output. The binary data demodulation circuit 9 demodulates binary data by the correlation pulse (e) output from the binarization circuit 2 and the window pulse (e) output from the sampling and window pulse generator 6. The second matched filter 10 outputs a pulse (re) when the binary data (ta) output from the binary data demodulation circuit 9 matches a predetermined pattern.

Note that each of the circuits described above is triggered by a reception operation start pulse output from an external circuit (not shown) to start each operation.

Next, the operation of the above-described embodiment of the present invention will be described in more detail. To facilitate the explanation, one period of the PN code and the data bit length are equal, and the integration interval by the correlator 1 and the PN An example will be taken in the case where the code 1 cycle is the same.

When the reception operation start pulse is output from the external circuit, the reference
The PN code generator 5 gives the reference PN code (h) included in the reference signal to the correlator 1 based on the initial information (c) of the PN code set by the external circuit. Received PN code and reference PN included in received signal (b) when spread spectrum signal is received
When the signs (H) match, the correlator 1 outputs a correlation spike (D) to the binarization circuit 2. As shown in FIG. 2, the binarization circuit 2 separates the correlation spike (d) into the positive side and the negative side to generate a correlation pulse (e), and the first matched filter 3 and the digital phase locked loops 7 and 2 are provided. It is given to the value data demodulation circuit 9.

By the way, as described above, it is not known at which position the two PN codes match in the correlator 1, and the received data cannot be correctly demodulated unless the positions where both codes match are set correctly. Finally, it is necessary to perform the initial synchronization so that the positions finally coincide with each other as shown in FIG. 12 (b). In the present invention, this initial synchronization operation is performed as follows.

The transmitted data consists of information data and preamble data as shown in FIG. 14 (a), and the preamble data further includes an initial synchronization pattern and an information data start timing detection pattern as shown in FIG. 14 (b). The correlation pulse (e) output from the binarization circuit 2 is input to the first matched filter 3. The first matched filter 3 outputs a pulse (f) to the up / down counter 4 when the pattern of the correlation pulse (e) matches the set predetermined pattern.

The up / down counter 4 keeps the reference until the pulse (f) is output from the first matched filter 3 as shown in FIG.
It is initialized by the strobe pulse (re) indicating the first bit of the reference PN code (h) output from the PN code generator 5, and the up count is repeated from the offset value (a) set by the external circuit. When the pulse (f) is output from the first matched filter 3, the up-down counter 4 switches from up-counting to down-counting at the timing of the pulse, and when the count value of the counter 4 becomes 0, a borrow pulse is generated. (G) is output to the PN code phase control pulse generation circuit 8.

The PN code phase control pulse generation circuit 8 is triggered by the borrow pulse (G) to output the phase control pulse (Y) of the reference PN code (H) to the reference PN code generator 5, sampling pulse and window pulse generator 6 and digital. Output to the phase locked loop circuit.

Through the series of operations described above, the received PN code and the reference PN code (h) match.

FIG. 4, FIG. 5 and FIG. 6 show a configuration example of the first matched filter 3.

In FIG. 4, 11 is a shift register, 12 is a pulse counter, and 13 is a comparator.

As shown in FIG. 5, the shift register 11 has a plurality of shift registers SR _{1 to} SR _n connected in series, each driven by a code clock, and an output terminal is set for each fixed length. Each output is given to the pulse counter 12.

The pulse counter 12 counts the total number of pulses output from each shift register in parallel, converts the count into binary data, and outputs the binary data to the comparator 13. This pulse counter 12
Is composed of a plurality of half adders 14 and full adders 15 as shown in FIG.

The parallel output of each shift register is input to each half adder 14 as a set of two, and half addition is performed. The resulting sum output also carry output 2 ^0-position is converted into binary data by allocating the 2 ^first.

Further, each converted into binary data is input to the full adder 15 and added. In this way, the total number of pulses output from the shift register 11 in parallel is converted into binary data.

The comparator 13 compares the binary data output from the pulse counter 12 with a threshold value set by an external circuit, and outputs a pulse when the binary data reaches the threshold value.

In the first matched filter 3 having the above-described configuration, for example, when all the data patterns for initial synchronization transmitted are "1", correlation spikes are generated even in the case shown in FIG. 12 (a). To do. That is, the positive correlation spike occurs at a half cycle of the time (hereinafter referred to as delay time) T corresponding to the integration section of the correlator 1, and the negative correlation spike does not occur. Therefore, the binarization circuit 2 generates a positive correlation spike in the same cycle as the correlation spike, but does not generate a negative correlation pulse.

This correlation pulse is input to the shift register 11 and the shift register 11 has the delay time T as shown in FIG.
Output terminal is set for each 1/2. Therefore, if the signal is normally received, pulses are output in parallel from the shift register 11 at intervals of 1/2 of the delay time T, and are output in parallel, and are converted into binary data by the pulse counter 12 as described above. After that, when the comparator 13 reaches a threshold value set by an external circuit, the comparator 13 outputs a pulse.

According to the above-described configuration of the first matched filter 3, even if the output of the correlator 1 is abnormal due to noise or the like, it is possible to match only the normal correlation pulse.

It should be noted that a plurality of shift registers forming the shift register 11
The intervals of the output terminals set in SR _{1 to} SR _n are modified according to the pattern of the data for initial synchronization to be transmitted.

An example of the configuration of the second matched filter 10 shown in FIGS. 7 and 8 is shown. In FIG. 7, 21 is a shift register, 22 is a pulse counter, and 23 is a comparator.

As shown in FIG. 8, the shift register 21 is composed of a plurality of shift registers SR ′ _{1 to} SR ′ _n connected in series, and is driven by a clock having a period equal to the length of one data bit. Has the output terminal set.

Demodulated data is input to the shift register 21, and when the demodulated data matches the pattern set to detect the start timing of the information data included in the preamble data as shown in FIG. 14 (b), An inverter INV is appropriately connected to the output of each shift register so that the pulses are output from all the shift registers SR ′ _{1 to} SR ′ _n, and the output of each shift register is the pulse counter 22. Is output to.

The pulse counter 22 and the comparator 23 are configured in the same manner as described above, and the pulse counter 22 counts the total number of pulses output from the shift register 21, converts it into binary data, and outputs it to the comparator 23. To do. The comparator 23 compares the binary data with a threshold value set by an external circuit, and outputs a pulse when the binary data reaches the threshold value.

Now, the initial synchronization is established as described above, and the arrangement relationship between both codes is as shown in FIG. 12 (b).

However, if there is an error in the code clock frequency between the two codes, the position where the two codes match gradually shifts from the above arrangement relationship. That is, even if the initial synchronization is established, if the code clock frequencies between the two codes are different, the position where the two codes match gradually deviates from the normal position.

For this reason, in the present invention, the following means are taken to correct the above-mentioned shift, that is, the phase error and maintain synchronization.

Reference PN output from the PN code phase control pulse generation circuit 8
The sampling pulse and window pulse generator 6 and the digital phase lock loop circuit 7 are initialized by the phase control pulse (Y) indicated by the code (H).

As shown in FIG. 13, the circuit 6 provides sampling pulses S ₁ and S ₂ before and after the correlation pulse (e) obtained in the normal positional relationship as shown in FIG. 12 (b). Generated and output to the circuit 7. The circuit 7 constantly samples the correlation pulse (e) with the sampling pulses S ₁ and S ₂ and monitors the direction of deviation of the correlation pulse.

The circuit 7 counts the number of times each time sampling is performed by an internal counter, and if there is a difference in the number of sampling times by both sampling pulses, it indicates a deviation amount of advance or delay when this difference reaches a predetermined value. It outputs a pulse to the circuit 8.

The circuit 8 is triggered by the above pulse (2), and the phase control pulse of the reference PN code (h) corresponding to the deviation detection amount of the correlation pulse by both sampling pulses is applied to the reference PN code generator 5.
To control the phase. As a result, the phase error between both codes is corrected and the synchronization can be maintained.

By performing the initial synchronization of the received PN code and the reference PN code in the correlator 1 and holding the synchronization as described above, the binary data demodulation circuit 9 can perform accurate data demodulation as follows. it can.

As shown in FIG. 13, the positional relationship between the correlation pulse (e) and the sampling pulses S ₁ and S ₂ is always maintained.

The sampling pulse and window pulse generator 6 is the 13th
As shown, a window pulse (L) having a width equal to the interval from the rising edge of the sampling pulse S _{1 to} the falling edge of the sampling pulse S ₂ is generated and output to the circuit 9. The circuit 9 extracts the correlation pulse (e) by the window pulse (le) and performs accurate data demodulation.

Next, in order to process the demodulated data by the external circuit, it is necessary to detect the start timing of the information data after the initial synchronization is established.

Therefore, the transmitted data includes the second pattern set for detecting the start timing after the pattern (first pattern) set for the initial synchronization. The second matching circuit 10 is weighted corresponding to the second pattern.

The demodulated data (ta) is given to the second matching circuit 10, and it is judged whether there is a match with the second pattern. When they match, a pulse (re) is output from the second matching circuit 10. By this pulse, the external circuit can detect the start timing of the information data included in the demodulated data.

In this case, it is especially preferable to use, for example, a Barker code (BARKER) pattern as the second pattern. For the Barker code, for example, June 1981
Please refer to Code Theory (Computer Basic Course 18) published by Shokoido Co., Ltd. on the 30th.

[Effect of the Invention] As is clear from the above description, according to the present invention, the start timing of the data of the information included in the demodulated data can be detected easily and accurately, and the practical effect is remarkable.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a timing chart for explaining the operation of the binarizing circuit in the above embodiment, and FIG. 3 is a timing chart for explaining the initial synchronization operation of the above embodiment. FIGS. 4, 5, and 6 are block diagrams showing an example of the configuration of the first matched filter in the above embodiment, and FIGS. 7 and 8 are configurations of the second matched filter in the above embodiment. FIG. 9 is a block diagram showing an example, FIG. 9 is a block diagram showing a configuration of a conventional spread spectrum transmitter (a) and a receiver (b), FIG. 10 is a sectional view showing an example of the structure of a convolver, and FIG. FIGS. 12A and 12B are diagrams showing the relationship between the array of data bits and the PN code and the gate electrode, FIGS. 12A and 12B are diagrams showing that the correct array of the received PN code and the reference PN code is necessary, and The figure illustrates the synchronization holding operation and data demodulation of the above embodiment. Waveform diagram of FIG. 14 is a diagram showing a configuration of a transmission data. 1 ... Correlator, 2 ... Binarization circuit, 3 ... First matched filter, 4 ... Up-down counter, 5 ... Reference PN code generator, 6 ... Sampling pulse and window pulse generator, 7: Digital phase lock loop circuit, 8
...... PN code phase control pulse generation circuit, 9 ... Binary data demodulation circuit, 10 ... Second matched filter.

Continuation of the front page (56) References JP-A-55-30288 (JP, A) JP-A-60-216648 (JP, A) JP-B-55-19097 (JP, B1)

Claims (2)

[Claims] 1. A spread spectrum receiver that demodulates desired data by a correlator that correlates a received PN code included in a received signal and a reference PN code included in a reference signal generated on the receiving side, The correlation output of the correlator is input to the initial synchronization determination means, and the received PN code and the reference PN code are initially synchronized by the output when they match the predetermined initial synchronization determination pattern, and the demodulated data is information. A spread spectrum receiver characterized in that the start timing of the information data is inputted to the external circuit and a judgment output when the pattern coincides with a predetermined start timing judgment pattern is given to an external circuit to detect the start timing of the information data. . 2. The determination means includes a matched filter, the filter is weighted corresponding to the determination pattern, and is applied to an external circuit when the determination output is equal to or more than a predetermined threshold value. The spread spectrum receiver according to claim 1.