JPH01126035A - Spread spectrum receiver - Google Patents

Abstract

PURPOSE:To attain sure synchronization holding by always monitoring the direction of deviation and its quantity of a correlation pulse after the initial synchronization in the correlation device is established so as to correct the phase error between a received PN code and a reference PN code. CONSTITUTION:A sampling pulse and window pulse generator 6 generates sampling pulses S1, S2 before and after timewise the correlation pulse outputted from a binarization circuit 2 obtained at the normal relation of position and gives them to a phase locked loop circuit 7. The circuit 7 uses the pulses S1, S2 to sample the correlation pulse to monitor the direction of deviation of the correlation pulse and to count the number of times, thereby obtaining the quantity of deviation and outputs a pulse representing the quantity of deviation in lead or lag direction to a PN code phase control pulse generating circuit 8. The circuit 8 is triggered by the pulse to give a phase control phase to a reference PN code generator and to control the phase.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a spread spectrum receiver, and in particular to a received pseudo-noise code (P5) in a correlator used in the receiver.
eudo Noise Code (hereinafter referred to as PN code) and base 1i! This invention relates to improving data demodulation by maintaining synchronization after initial synchronization with the JPN code.

[Summary of the Invention] A correlator is provided for correlating a received PN code included in a received signal with a reference PN code generated on the receiving side, and the time of a correlation pulse generated from a correlation spike output from the correlator is provided. A sampling pulse is generated before and after the reference PN code, thereby sampling the correlation pulse, detecting the direction and amount of deviation, and controlling the phase of the reference PN code with the corresponding phase control pulse to synchronize both codes. This is a spread spectrum receiver designed to maintain

[Prior Art] In spread spectrum communication, as shown in Fig. 9(a), a pseudo-noise code, which is a type of binary code, is modulated with data, and a carrier wave is modulated with the modulated PN code and transmitted. do. In the figure, 31 is data, 32 is a modulator, 33 is a PN code generator, 34 is a carrier wave generator, 35 is a modulator, and 36 is an antenna.

On the receiving side, as shown in FIG. 9(b), the signal is received, and the matched filter calculates the correlation with the reference PN code, and calculates the relative value that appears when both codes match and in the vicinity. A large amplitude autocorrelation waveform (hereinafter referred to as a correlation spike waveform) is processed to restore data.

In the figure, 37 represents an antenna, 38 a correlator, 39 a reference PN code generator, 40 a data demodulator, and 41 data.

A convolver is one type of matched filter.

A convolver is a functional element that performs convolution integration, but if the reference code 2 (hereinafter referred to as reference code) is in a time-reversed relationship with the received code, a matched filter that performs a correlation calculation is used. becomes.

An example of a convolver is a SAW convolver. S
AW convolvers have the following structural features: (1) those with a gap between the piezoelectric material and silicon, (2) those in which the piezoelectric material and silicon are integrated via an oxide film, and (3) those with only piezoelectric material. , etc., and all of them utilize nonlinear characteristics to perform a product operation by the interaction of two signals, and integrate the result at an electrode called a gate provided on the interaction region.

Figure 10 is an example showing the structure of a SAW convolver.

In the figure, 42 and 43 are transducers, 44 are piezoelectric bodies, and 4
Reference numeral 5 indicates an oxide film, 46 indicates silicon, and 47 indicates a gate electrode.A signal 5(t) input from the transducer 42 propagates to the right in the figure, and a signal input from the transducer 43 propagates to the left. Due to the nonlinear characteristics of the piezoelectric body-oxide film-silicon structure, an interaction occurs between 5(t) and r(t), a product operation is performed, and the result is transferred to the gate electrode 47.
It is integrated by

The signal c(t) output from the gate electrode 17 is.

It is expressed by the following formula.

However, A is a constant, T is the time required for the sound wave to pass under the gate electrode (hereinafter referred to as in-gate delay time), x is the distance measured in the propagation direction of 5(t),
is the speed of sound.

Generally, a PN code has a constant period. In the waveform created by the transmitting side, there is often a certain relationship between one period of the PN code and the length of one data bit. Here, for ease of explanation, we will take as an example a case where one period of the PN code is equal to the length of one data bit.

On the other hand, the relationship between the in-gate delay time and the PN code can also be selected as appropriate. That is, the in-gate delay time can be made shorter, equal, or longer for one period of the PN code. What is the in-gate delay time?

In correlation calculations, it means an integral interval. Due to the correlation characteristics of the PN code, it is preferable that the integration interval spans exactly one period. Therefore, in this explanation.

Let us take as an example a case where the in-gate delay time and one period of the PN code are equal.

The above relationships are shown in FIGS. 11(a), (b), and (C). (a) represents the data, (b) represents the PN code arrangement,
In the above example, the length of one data bit and one period of the PN code are the same and equal to Q. (c) is a schematic cross-sectional view of the convolver, and the delay time within the length L of the gate electrode is Q
0 or more is an example for explanation, and 1 data
The relationship between the bits, one cycle of the PN code, and the in-gate delay time can be selected as appropriate.

Now, in actual communication, since it is unknown when the receiving side will receive the transmitted signal, it inputs the reference signal to the - side transducer and waits for reception of the signal. When the signal is received, the other transducer
Supplied to the convolver. When the respective PN codes included in the received signal and the reference signal match, a correlated spike waveform is obtained from the gate electrode of the convolver. However, it is completely unknown at what position the two codes match. 0 If the matching position of both codes is not set correctly, the data cannot be restored correctly. 1 For example, the 12th
When both codes match as shown in Figure (a), half of the received code contains data bit A, and the other half contains data bit B. The figure shows, from the top, the arrangement of data bits, received PN code, and reference PN, and the region indicated by . . . represents the interaction region under the gate electrode. The PN code person is a time-reversed version of the PNN code.

As explained above, no matter where the received code and the reference code initially match, some means must be taken so that they will eventually match at the position shown in Figure 12(b). ,in this way.

The period from when a signal is received until the codes match at the position shown in FIG. 12(b) is called initial synchronization.

After initial synchronization is established and the arrangement is as shown in Fig. 12(b), if there is a difference between the clock frequency of the received PN code and the clock frequency of the reference PN code, the arrangement is as shown in Fig. 12(b). The matching position gradually shifts from The deviation is expressed as follows every time the beginning of the received PN code and the base $PN code meet. However, in equation 1, fr is the clock frequency of the reference PN code, ft is the clock frequency of the received PN code, and N is the number of chips constituting one period of the PN code.

In other words, even if initial synchronization is established, if the clock frequencies of the codes differ, the matching position will gradually shift from the correct position, making it impossible to demodulate the data.This means that in order to eliminate the "shift", This means that the transmitting and receiving sides must have exactly the same clock frequency. Clock oscillators are generally based on crystal oscillators, but it is not only extremely difficult to manufacture multiple crystals that oscillate at exactly the same frequency, but it is also extremely difficult to manufacture multiple crystals that oscillate at exactly the same frequency. There are drawbacks such as the need for accurate control.

Therefore, in order to improve the above-mentioned drawback, the correlation spike is signal-processed to generate a pulse (hereinafter referred to as a correlation pulse), and the reference PN code is initialized (reset) by this correlation pulse. A method of performing the initial synchronization by matching patterns in the period on a correlator is also proposed, for example, in Japanese Patent Application No. 77789/1989.

[Problems to be Solved by the Invention] After initial synchronization is achieved by the above method, it is then necessary to correct the phase error in the patterns of both codes due to the code clock frequency error between the above two codes, that is, to maintain synchronization. can be,
According to the above method, the phase error is maintained by extracting the correlation pulse obtained every time the two codes match on the correlator using a gate pulse at a desired timing and initializing the basic IPN code.

However, according to such a conventional method, there is a high possibility of malfunction if noise or the like is mixed in at the timing of the above-mentioned pulses.
Each time the reference PN code is initialized, it is reduced to 1/2, so it takes time for the error to converge, and there is a problem that data demodulation cannot be performed accurately.

Therefore, an object of the present invention is to improve the above-mentioned method of maintaining synchronization to perform data demodulation accurately and stably.

[Means for Solving the Problems] In order to achieve the above object, the present invention provides means for generating sampling signals temporally before and after a correlation pulse output from a correlator in a spread spectrum receiver. and means for extracting the correlation pulse using the sampling pulse.

A means for counting the number of extractions, and a means for generating a phase control signal when the difference between the counted value reaches a predetermined value; 4PN
The present invention is characterized by comprising means for controlling the phase of the code, and means for extracting the correlation pulse between both sampling pulses and demodulating data.

[Operation] By counting the number of times the correlation pulse is extracted by the sampling pulse, the amount and direction of deviation of the correlation pulse are detected, and the phase of the reference PN code is controlled according to the detected amount, thereby reducing the phase error between the two codes. is corrected, synchronization can be maintained, and data can be demodulated by extracting the correlation pulse between both sampling pulses.

[Examples] The present invention will be described below with reference to examples shown in the drawings.
FIG. 1 shows an embodiment of a spread spectrum receiver according to the present invention, in which 1 is a correlator, 2 is a binarization circuit, 3 is a first matched filter, 4 is an up/down counter, and 5 is a reference PN code generator. , 6 is a sampling pulse and wind pulse generator, 7 is a digital phase-locked loop circuit, 8 is a PN
A code phase control pulse generation circuit, 9 a binary data demodulation circuit, and 10 a second matched filter.

In FIG. 1, the binarization circuit 2 converts the received PN code and base *P
Correlation pulses (E) are generated by separating the correlation spikes (D) that appear when and near the N codes (H) in the correlator 1 into positive and negative polarities. The first matched filter 3 outputs a pulse (E) (initial synchronization detection signal) when the pattern of the correlation pulse (E) output from the binarization circuit 2 matches a predetermined determination pattern.

The up/down counter 4 is initialized by a strobe pulse output from the reference PN code generator 5 and counts up from an offset value (a) set from an external circuit such as a microprocessor. When a pulse (to) is output from 3, this triggers a down count and generates a borrow pulse (to).

The reference PN code generator 5 uses a reference P set from an external circuit.
Based on the initial information (c) of the N code, create the standard PN code (c)
and outputs a strobe pulse (su) indicating the first bit.

The sampling and wind pulse generator 6 generates a sampling pulse (nu) and a wind pulse (ru) that output pulses for sampling and extracting the correlation pulse (e) output from the binarization circuit 2. The digital phase-locked loop circuit 7 maintains synchronization between the received PN code included in the received signal (b) input to the correlator 1 and the reference PN code (h) included in the reference signal.

The PN code phase control pulse generation circuit 8 is triggered by the pulses (T) and (W) output from the up/down counter 4 and the digital phase lock loop 7, and generates the reference P.
Outputs a phase control pulse (Y) of N code (J). The binary data demodulation circuit 9 demodulates binary data using the correlation pulse (e) outputted from the binarization circuit 2 and the wind pulse (ru) outputted from the sampling and wind pulse generator 6. The second matched filter 10 outputs a pulse (shi) when the binary data (nu) outputted from the binary data demodulation circuit 9 matches a predetermined pattern.

Note that each of the above-mentioned circuits is triggered by a reception operation starting pulse outputted from an external circuit (not shown) to start its respective operation.

Next, the operation of the embodiment of the present invention described above will be explained in more detail, but in order to facilitate the explanation, it is assumed that one period of the PN code and the length of the data bit are equal, and the integration interval by the correlator 1 and the length of the PN code are equal. Let us take as an example the case where the codes have the same period.

When the reception operation activation pulse is output from the external circuit, the reference PN code generator 5 generates the reference P included in the reference signal based on the initial information (c) of the PN code set by the external circuit.
The N code (chi) is given to the correlator 1. When a spread spectrum signal is received, the received PN included in the received signal (b)
When the code and the reference PN code (H) match, a correlation spike (D) is output from the correlator 1 to the binarization circuit 2. As shown in FIG. 2, the binarization circuit 2 separates the correlation spike (D) into a positive side and a negative side to generate a correlation pulse (E).

First matched filter 3. Digital phase lock loop 7
and the binary data demodulation circuit 9.

Now, as mentioned above, it is unknown at what position in the correlator 1 the two PN codes match, and unless the matching position of both codes is set correctly, the received data cannot be demodulated correctly. , eventually the 12th
It is necessary to perform initial synchronization so that the positions match as shown in FIG.

The transmitted data is composed of preamble data and information data as shown in FIG. 14(a).

The transmitted data includes a predetermined pattern for initial synchronization (initial synchronization pattern) as shown in FIG. ) is input to the first matched filter 3. 1st
The matched filter 3 outputs a pulse (E) to the up/down counter 4 when the pattern of the correlation pulse (E) matches a predetermined pattern.

As shown in FIG. 3, the up/down counter 4 keeps the base j
It is initialized by a strobe pulse (su) indicating the first bit of the reference PN code (ch) output from the 11PN code generator 5, and repeatedly counts up from an offset value (a) set from an external circuit. When a pulse is output from the first matched filter 3, the up/down counter 4 switches from up counting to down counting at the timing of the pulse, and the count value of the counter 4 becomes O.
When this happens, a borrow pulse (g) is output to the PN code phase control pulse generation circuit 8.

The PN code phase control pulse generation circuit 8 is triggered by the borrow pulse and generates the phase control pulse (Y) of the reference PN code (J) to the reference PN code generator 5, the sampling pulse and wind pulse generator 6, and the digital phase lock loop circuit. Output to.

Through the above-described series of operations, the received PN code and the reference PN code (chi) come to match.

FIGS. 4, 5, and 6 show an example of the configuration of the first matched filter 3. FIG.

In FIG. 4, 11 is a shift register, 12 is a pulse counter, and 13 is a comparator.

The shift register 1 has a plurality of shift registers SR1 to SRn connected in series as shown in FIG. The output is pulse counter 12
given to.

The pulse counter 12 counts the total number of pulses output in parallel from each shift register, converts the count into binary data, and outputs it to the comparator 13. This pulse counter 12 includes, for example, a plurality of half adders 1 as shown in FIG.
4 and a full adder 15.

The parallel outputs of the shift registers are input into each half adder 14 as a set of two, and half addition is performed. The resulting addition output is assigned to the 2° position, and the carry output is assigned to the 2' position, thereby converting it into binary data.

Furthermore, each of the converted binary data is input to a full adder 15 and added. In this way, the total number of pulses output in parallel from the shift register 11 is converted into binary data.

The comparator 13 compares the binary data output from the pulse counter 12 with a threshold value set by an external circuit, and outputs a pulse when the binary data reaches the threshold value.

In the first matched filter 3 having the above-described configuration.

For example, if the pattern of the transmitted data for initial synchronization is all 1", correlation spikes will occur even in the case shown in FIG. (hereinafter referred to as delay time) occurs in 172 cycles of T corresponding to the integration interval of is generated.

No negative correlation pulse is generated.

This correlation pulse is input to the shift register 11,
In this shift register 11, output terminals are set for every 172 delay times T, as shown in FIG. Therefore, if the signal is being received normally, shift register 11
From then on, the pulses are output in parallel while increasing every 1/2 of the delay time T, converted into binary data by the pulse counter 12 as described above, and then sent to the comparator 13 at a threshold value set from an external circuit. Once reached, comparator 13 outputs a pulse.

According to the above-described configuration of the first matched filter 3, even if an abnormality occurs in the output of the correlator 1 due to noise or the like, it is possible to match only normal correlation pulses.

Note that the intervals between the output terminals set in the plurality of shift registers SR to SRn constituting the shift register 11 are modified in accordance with the pattern of data for initial synchronization that is transmitted.

7 and 8 show an example of the configuration of the second matched filter 10. In FIG. 7, 21 is a shift register;
is a pulse counter, and 23 is a comparator.

As shown in FIG. 8, the shift register 21 is composed of a plurality of shift registers SR'1 to SR'n connected in series, and is driven by a clock having a period equal to the length of one data bit. An output terminal is set in the register.

Demodulated data is input to the shift register 21.

As shown in FIG. 14(b), when the demodulated data matches the pattern set to detect the start timing of the information data included in the preamble data, all shift registers SR', ~SR So that a pulse is output from 'n.

An inverter INV is appropriately connected to the output of each shift register, and the output of each shift register is output to the pulse counter 22.

The pulse counter 22 and the comparator 23 are constructed in the same manner as described above, and the pulse counter 22 is connected to the shift register 2.
The total number of pulses output from 1 is counted, converted to binary data, and output to the comparator 23. Comparator 23 is this 2
The binary data is compared with a threshold value set from an external circuit, and a pulse is output when the binary data reaches the threshold value.

Now, initial synchronization is established as described above, and FIG. 12 (
The arrangement relationship between the same codes is as shown in b).

However, if there is an error in the code clock frequency between the same codes, the position where the two codes match will gradually shift from the above arrangement relationship. That is, even if initial synchronization is established, the code clock frequencies between the same codes are different.

The position where both codes match gradually deviates from the normal position.

Therefore, in the present invention, the following measures are taken to correct the above-mentioned deviation, that is, phase error, and maintain synchronization.

The sampling pulse and wind pulse generator 6 and the digital phase lock loop circuit 7 are initialized by the phase control pulse (Y) of the reference PN code (J) outputted from the PN code phase control pulse generation circuit 8.

As shown in FIG. 13, the circuit 6 generates a correlation pulse (H) obtained in the normal positional relationship as shown in FIG. 12(b).
The sampling pulse S□Is before and after that
I is generated and output to the circuit 7 described above. The circuit 7 receives sampling pulses S1. S.

The correlation pulse (E) is constantly sampled by the above method, and the shift direction of the correlation pulse is monitored.

Each time sampling is performed, the circuit 7 counts the number of times using an internal counter, and if there is a difference in the number of samplings between the two sampling pulses, when this difference reaches a predetermined value, it indicates the amount of advance or delay. A pulse (wo) is output to the circuit 8.

The circuit 8 is triggered by the above-mentioned pulse (w), and provides the reference PN code generator 5 with a phase control pulse of the reference PN code (h) corresponding to the detected amount of deviation of the correlation pulse by both sampling pulses to control its phase. . As a result, the phase error between the same codes is corrected and synchronization can be maintained.

By performing the initial synchronization of the received PN code and the reference PN code in the correlator 1 and maintaining the synchronization as described above, accurate data demodulation can be performed by the binary data demodulation circuit 9 as described below. can.

As shown in FIG. 13, the correlation pulse (e) and the sampling pulse S1. The positional relationship of S2 is always maintained.

The sampling pulse and wind pulse generator 6 is the first
As shown in FIG. 3, a wind pulse having a width equal to the interval from the rising edge of the sampling pulse S to the falling edge of the sampling pulse S2 is generated and output to the circuit 9. The circuit 9 extracts a correlation pulse (E) using a wind pulse (R) and performs accurate data demodulation.

[Effects of the Invention] As is clear from the above explanation, according to the present invention, after the initial synchronization of both codes in the correlator is established, the direction and amount of deviation of the correlation pulse are constantly monitored, and the difference between the two codes is constantly monitored. Since the phase error is corrected, synchronization is reliably maintained and accurate data demodulation can be performed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a timing chart for explaining the operation of the binarization circuit in the above embodiment, FIG. 3 is a timing chart for explaining the initial synchronization operation of the above embodiment, Figure 4. 5 and 6 are block diagrams showing an example of the structure of the first matched filter in the above embodiment, and FIGS. 7 and 8 are block diagrams showing an example of the structure of the second matched filter in the above embodiment. 9 is a block diagram showing the configuration of a conventional spread spectrum transmitter (a) and a receiver (b).
Figure 0 is a cross-sectional view showing an example of the convolver structure, Figure 11 is a diagram showing the relationship between the data bit and PN code arrangement and the gate electrode, and Figures 12 (a) and (b) are the received PN code and the reference. FIG. 13 is a waveform diagram for explaining the synchronization holding operation and data demodulation of the above embodiment, and FIG. 14 is a configuration diagram of transmission data and preamble data. . 1... Correlator, 2......2
Value conversion circuit, 3...First matched filter,
4... Up/down counter, 5...
...Reference PN code generator, 6...
- Sampling pulse and wind pulse generator. 7... Digital phase locked loop circuit, 8... PN code phase control pulse generation circuit, 9... Binary data demodulation circuit, 10・
...Second matched filter. Patent Applicant Clarion Co., Ltd. Agent Patent Attorney Nagai 1) Take 3 Part 4! 112ff No. 5 IN ￥, 6 Figure 7 Figure 8 Figure 9 Figure 1 et al. Figure 10 @ 11 Figure 12 Figure 13 Figure @ Figure 14 Procedure auxiliary device October 1986

Claims (1)

[Claims] It has a correlator that correlates the received PN code included in the received signal with the reference PN code included in the reference signal generated on the receiving side, and generates a correlation pulse from the correlation spike output from the correlator. , a spread spectrum receiver for demodulating desired information from the received signal using the correlation pulse, comprising: means for generating sampling signals temporally before and after the correlation pulse; and means for generating the correlation pulse by the sampling pulse. means for extracting, means for counting the number of times of extraction, means for generating a phase control signal to control the phase of the reference PN code when the difference between the counted values reaches a predetermined value, and a means for controlling the phase of the reference PN code; and means for extracting the correlation pulse and demodulating data.