JPH0778720B2 - Image synthesizer - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to synthesizing digitized images, and is particularly suitable for recording an arbitrarily shaped foreground image by superimposing it on another background image. The present invention relates to an image synthesizer.

[Prior Art] In recent years, some workstations and the like have systems for capturing, editing, and recording digitized natural images. This type of apparatus is introduced, for example, in Nikkei New Media and Technology Frontline Report "CD-ROM, CD-I Development Site Report" (1987.5), pages 36 to 45, published by Nikkei McGraw-Hill. The system introduced in the above document is based on a 16-bit microprocessor, and has a depth direction 24-bit (8 bits each for R, G, B) frame buffer (display memory) and a video camera for capturing natural images. And an A / D converter, a monitor for checking the contents of the frame buffer, a doublet or terminal for inputting coordinates and characters, a working memory, an external storage device for recording the edited result, and the like. The captured natural image can be subjected to editing / processing such as noise removal, color tone / contrast change, contour extraction, enlargement / reduction, and mask composition. Among them, the mask composition is to extract a part of another image and superimpose it on the background image. For this, in the conventional example, a memory for a mask is provided in parallel with the frame buffer, and The background image and the image extracted by the mask are combined while referring to the contents. This mask memory reference is generally performed by software.

Further, there is a method of controlling the circuit whether or not to transfer data to the corresponding frame buffer by the contents of the mask memory itself to speed up the synthesizing process.
No. 7 is disclosed.

[Problems to be Solved by the Invention] The above-mentioned conventional technique has a problem in that it is necessary to provide a mask memory in parallel with the frame buffer, resulting in an increase in circuit scale. Further, if the mask memory is referred to by software, it takes a very long time to synthesize the mask. On the other hand, in order to realize high-speed synthesis in a circuit manner, the mask memory needs to have a sufficiently fast access time as compared with a frame buffer, which tends to be expensive in combination with an increase in circuit scale. In addition, even if an image called chroma key that should be overlaid on the premise of mask composition is captured with a fixed background color, a separate mask pattern is created based on the image and recorded in the mask memory. There is also a problem in that it takes time and effort to synthesize because it requires a procedure to do so.

It is an object of the present invention to provide an apparatus which eliminates the above-mentioned drawbacks of the prior art and easily realizes high-speed mask composition with a relatively small circuit scale and low cost.

[Means for Solving the Problems] In order to achieve the above-mentioned object, the present invention has a first display memory for storing first image data, and provides a first image composed of the first image data. Second to
In an image synthesizing apparatus for synthesizing images, predetermined image data and image data of the second image are compared for each unit image data, and the second image data is stored in the first display memory based on the comparison result. It is characterized in that display memory control means for controlling whether or not to write is provided.

The unit image data is, for example, pixel data.

The display memory control means, for example, first comparing means for comparing the predetermined image data and the second image data for each unit image data, and the second image based on the result of the first comparing means. It can be configured by a writing control unit that controls writing of data to the second display memory. The predetermined image data may be set so as to have a specific range, and the first comparing means may set the second image data to the second range.
When the image data is included in the range, a coincidence signal is output, and in response to the coincidence signal, the writing control means causes the second control unit to output the coincidence signal.
Prohibits writing to the display memory.

The second image data may be stored in the main memory, or may be provided in the second display memory and stored in the second display memory. When the second display memory is provided, a display reading means for periodically reading image data from the first and second display memories for displaying the image data, and image data read from the second display memory are further provided. Second comparing means for comparing every predetermined unit image data, and one of the first and second image data read from the first and second display memories is selected based on the comparison result of the second comparing means. It may be provided with a selection means for displaying the image. At this time, the second
The comparison means can be shared with the first comparison means.

One or both of the first and second comparing means may be composed of a rewritable memory in which the unit image data is used as an address input and the comparison result is used as data.

The second image data is, for example, image data in which an image to be superimposed on the first image is a foreground image and a color not included in the foreground image is a background color, and the predetermined image data is the background color. Image data.

[Operation] According to the present invention, the first image formed by the image data stored in the first memory is combined with the second image formed by the second image data, that is, a part of the second image is selectively selected. First
It is to be superimposed on the image. Therefore, the second image data is created such that the portion other than the image to be superimposed on the first image has a predetermined background color,
Or take in. Therefore, when the second image data is overwritten and written in the first display memory which stores the first image data,
The second image data is compared with the image data representing the background color for each unit image data, for example, for each pixel, and if they match, the writing of the second image data is prohibited. If it does not match the background color data, the second image data is written in the first display memory.

With such a configuration, the necessary portion of the second image is selectively changed to the first area without using the conventional mask memory.
Can be combined into an image. Also, only the foreground image is first
When writing to memory, DMA (Direct Memory Access) from memory to memory is possible without passing through MPU (Micro Processing Unit), and high-speed transfer can be realized.

[Embodiment] <First Embodiment> A first embodiment of the present invention will be described below with reference to FIG.
In FIG. 1, 10 is an MPU, 20 is an MPU data, 30 is an MPU address, 40 is an R / W signal, 50 is a display read address and a display address generation for generating a horizontal / vertical synchronization signal based on an original clock. Section, 60 is a display address, 70 is an address composition section for combining an MPU address and a display address, 80 is a display memory address, 90 is a second display memory for storing second image data, and 110 is for storing first image data. 1st display memory, 1
00 and 120 are serial display data which are outputs of display readout respectively, 130 is a display combining unit which combines both serial display data 100 and 120, 140 is a digital image output, 150 is a DA converter, 160 is an analog output image signal, 170 is the display memory R / W
Control unit (display memory control means), 180 is an R / W control signal for the display memory 110, 190 is an R / W control signal for the display memory 90, and 200 is a period during which the display address 60 is given to the display memories 90 and 110. Display cycle signal, 210 is MPU10
Direct Memory Access Controlle (DMAC) that controls high-speed block transfer of data directly between memories without going through
r), 220 is a main memory, 230 is an RGB camera, 240 is an input image signal, 250 is an AD converter, and 260 is a digital image input.

Next, the operation of this embodiment will be described. The MPU10 is a general-purpose 16-bit microprocessor. The display address generation unit 50 generates a display address 60, a display cycle signal 200, a horizontal / vertical synchronization signal (not shown), etc. by dividing the signal with the 1-pixel period signal as an original clock. The address synthesizing unit 70 switches between the display address 60 and the MPU address 30 based on the display cycle signal 200 and outputs it as the display memory address 80. That is, the MPU address 30 can be given to the display memories 90 and 110 during the period other than the time when the display address 60 is given, and data can be read and written. The display memories 90 and 110 have a total of 15 bits with 5 bits for each of R, G and B per pixel, and have a random access port accessible from the MPU 10 and a serial port for outputting data for display. Serial display data from the serial port 10
0 and 120 are continuously output and are input to the display synthesis unit 130. In the display synthesizing unit 130, the serial display data 120, the serial display data 100, or the serial display data 120 based on the mode preset by the MPU 10.
Any one of the data obtained by superimposing only the foreground image of the serial display data 100 on the above is given to the DA converter 150 as the digital image output 140. In the D-A converter 150, R, G, B
The 5-bit digital image output 140 is output as an R, G, B analog output image signal 160 and is supplied to a color CRT display or the like, and as a result, an image is reproduced on the screen.

On the other hand, the image data is captured by converting the input image signal 240 input from the RGB camera 230 into a digital image input 260 by the AD converter 250 and directly transferring it to the display memory 90. The image captured in the display memory 90 can be transferred to the display memory 110 or the main memory 220 or an external storage device (not shown) for processing or storage.

The display memory R / W control unit 170 uses the R / W signal 40, MP
Based on the U address 30, the display cycle signal 200, the transfer mode signal set by the MPU 10, and the value of the data to be transferred, read / write control signals 180 and 190 for the data in the display memories 90 and 110 are generated. If the transfer mode signal indicates the normal mode, the MPU10 or DMAC210 can access the display memories 90 and 110 and transfer data normally, but in the composite transfer mode, the display memory of the transfer source is displayed.
The data read from the memory 90 or the main memory 220 is also taken into the register in the display memory R / W control unit 170 at the same time as being taken into the internal register of the MPU 10 or the DMAC 210. Then, it is determined whether or not the data is background color data in a preset range of the MPU 10, and if so, a read / write control signal 1 to / from the display memory 110 which is the transfer destination.
80 is prohibited and writing is not performed. By performing this for all the one screens, only the foreground image portion is transferred to the display memory 110 and is combined with the image previously stored therein.

Next, the configuration and operation of the display memory R / W control unit 170 will be described in more detail with reference to FIGS. 2 and 3. FIG. 2 is a configuration diagram of the display memory R / W control unit 170 and its peripheral portion, and FIG. 3 is a circuit diagram showing the main portion of the data comparator 173 together with the register 172. 2 and 3, the same components as those in FIG. 1 are designated by the same reference numerals.

In FIG. 2, 171 is an address decoder, 172 is a register for temporarily holding pixel data read from the data transfer source, and 173 is the output of the register 172 included in the range of color data preset by the MPU 10. A data comparator (first comparing means) for discriminating whether or not, 174 is a transfer mode register set by the MPU 10, 175 is a capture signal for fetching color data into the register 172, and 176 is a mask showing the discrimination result of the data comparator 173. A signal, 177 is a transfer mode signal indicating the normal mode or the transfer combining mode, 181 is a valid signal for selecting and activating the display memory 110, 182 is a write enable signal to the display memory 110, and 191 is selection of the display memory 90. Similarly, the signal 192 is a write enable signal. Reference numeral 500 in FIG. 3 is a reference register for holding data to be compared with the blue component fetched in the register 172, 510 is a fetch signal generated when data is set from the MPU 10 to the reference register 500, and 520 is the above-mentioned two signals. Valid bit register indicating the bit to be compared between two registers, 530 is a capture signal generated when the valid bit register MPU10 sets data, 540 is an EOR gate, 550
Is a NAND gate, 560 is an AND gate, 570 is a blue effective signal that indicates that the blue component is within the specified range, 580 is a green effective signal that indicates that the green component is within the specified range, and 590 is the red component is within the specified range The red valid signal, 600, is a NAND gate. Although omitted in FIG. 3, the comparator 17
3 is a circuit for generating a green valid signal and a red valid signal, which are a reference register 500 and a valid bit register 5, respectively.
20 and gates 540-560.

Next, the operation will be described. First, an image to be superimposed as a background is captured and stored in the display memory 110 in advance. Further, the color data to be used as the background color is set in advance in the reference register 500 and the effective bit register 520 in FIG. Specifically, for example, when all of R, G, B are “0”, that is, black is the background color, all bits “0” are written from the MPU 10 into the reference registers 500 for blue, green, and red. And
In each of the valid bit registers 520 for blue, green and red, "1" indicating that all the bits are to be compared is written in all the bits. As a result, all registers 17 for blue, green, and red
The blue valid signal 570, the green valid signal 580, and the red valid signal 590 go to the “H” level only when “0” is taken into 2, and the mask signal 176 is brought to the “L” level by the operation of the NAND gate 600. To do. The reason for providing the effective bit register 520 is that the background color can be designated with a certain width. The operation will be described later.

As described above, after storing the background image and setting the background color, the foreground image is stored in the display memory 90 with the color previously set in the reference register 500 as the background color. Specifically, a method for capturing a foreground image with the background color screen set in the background through the RGB camera 230 and the A / D converter 250, a painting program called a paint system, and a painting system are not shown. There is a method of drawing a desired foreground image on a background color designated in advance using a coordinate input device or the like.

Next, the same color data as that set in the reference register 500 is set in a transparent color register (described later) included in the display combining unit 130 in FIG. 1, and the image in the display memory 90 is displayed on the image in the display memory 110. By setting the overlay mode in which the image is overlaid and displayed by the MPU 10, it is possible to actually transfer the foreground image to the display memory 110 and confirm the image of the exact same result on the screen before combining the two images. . And if the foreground picture is not missing from the background color, reset the background color and re-acquire the image,
If the position of the foreground image is improper, a proper offset value is given to the display address 60 given to the display memory 90 to scroll up, down, left and right to determine the optimum position.

Next, based on the offset value obtained as a result of the above scroll, MPU10 calculates the transfer destination address of the display memory 110,
The address of the display memory 90 as the transfer source and the transfer destination address are set in the DMAC 210, and the transfer mode register transfer synthesis mode shown in FIG.
Hand it over to DMAC210. When the bus mastership is transferred from the MPU 10, the DMAC 210 first generates an address and a read signal of the display memory 90, and fetches the transfer source data in the internal register.
Next, the address of the display memory 110 which is the transfer destination and the write signal are generated, and at the same time, the previously written data is output.
While updating the transfer source and transfer destination addresses,
Repeat for a preset number of words. At this time, the background color data of the transfer source is not written to the display memory 110 that is the transfer destination, and only the portion of the foreground image other than that is selectively extracted and written, so that the combination of the two images is realized. To do.

The transfer synthesis mode will be described in detail by operation. First, DMAC
Based on the MPU address 30 and R / W signal 40 given from 210, the address decoder 171 detects that the data of the transfer source has been read out, and generates the fetch signal 175. The register 172 takes in the transfer source data in parallel with the DMAC 210 using this signal as a clock. As described above, the data comparator 173 compares the register 172 with the background color data set in the reference register 500 in advance, and validates the mask signal 176 if the value is a designated value. In the address decoder 171, when the DMAC 210 outputs the address of the display memory 110 which is the transfer destination next time, if the mask signal 176 is valid, the valid signal 181 and the write enable signal 182 of the display memory 110 are the mask signal 176. It is banned because it is gated by. If the mask signal
MPU address 30 as usual, unless 176 is enabled
And a valid enable signal 181 and a write enable signal 182 obtained by decoding the R / W signal 40 are given to the display memory 110,
Data is written via MPU data 20. The display cycle signal 200 is a signal indicating a period during which the display address periodically given is valid, and data cannot be read or written from the DMAC 210 during this period. Therefore, during that period, an unillustrated acknowledge signal to the DMAC 210 is stretched from the display memory. The selection signal 191 and the write enable signal 192 for the display memory 90 are output without being affected by the state of the mask signal 176.

Table 1 shows a truth table of main inputs and outputs of the address decoder 171. In this table, the transfer source is the display memory 90.

In this way, if the background color has one specific value, it can be realized by mask composition of two images by the above method. But,
For example, if the background is a uniform color screen and the foreground image is RG
Even when captured from the B camera 230, the background color has a certain width due to the way the light is applied and the noise of the camera. In this way, the method of setting the background color with a certain width,
This will be described below with reference to FIG.

For example, when the foreground image is captured with the blue background as the background, the mask signal 176 may be activated when the level of blue is above a certain level and the levels of red and green are below a certain level. Here, for example, a case will be described in which the level of blue is detected as 24 levels or more out of 32 levels. First, write a binary value of 1 in the upper 2 bits to the reference register 500 for blue, and set the valid bit register 520
Write the binary number (11000) to. Then, the lower 3 bits may be any value, and the blue effective signal 570 is activated when the value of the blue component reaches the level of (11000) to (11111) in binary, that is, 24 levels or more in decimal. It This operation will be described in more detail below. When the corresponding bits of the register 172 and the reference register 500 are compared by the EOR gate 540, the output becomes “L” only when they match. Its output is provided to one input terminal of NAND gate 550 and the other terminal is provided with the output of the corresponding bit of valid bit register 520. When the output of the corresponding bit of the valid bit register 520 is “L”, the output of the NAND gate 550 is always “H” regardless of the output of the EOR gate 540,
The comparison result of that bit is ignored. Conversely, for the bit whose output of the valid bit register 520 is “H”, the EOR gate
The inverted value of the output of 540 is input to NAND gate 560, and when all of these values are at “H” level, that is, register 172
Only when all the valid bits of the reference register 500 match with each other, the blue valid signal becomes the “H” level. Similarly, in order to set the green valid signal 580 and the red valid signal 590 to be at “H” level when the level is 3 or less, for example, in the reference registers 500 for green and red, 0 is set in the upper 3 bits. Write a value and write the binary number (11100) to the valid bit register 520. Then, the binary number (0000
0) to (00011), that is, when the decimal component of each component is 3 or less, the green effective signal 580 and the red effective signal 5
If 90 is valid and the blue valid signal 570 is also valid, the mask signal 176 is valid by the action of the NAND gate 600.

Next, the configuration and operation of the display combining unit 130 will be described in more detail with reference to FIG. In FIG. 4, 600 is a comparator (second comparing means), 610 is a coincidence signal, 620 is a switching control circuit, 630 is a display mode register, 640 is a display mode signal,
650 is an acquisition signal, 660 is a switching signal, 670 is a switching circuit, 680
Is a transparent color register, 690 is a capture signal, 700 is a valid bit register, and 710 is a capture signal. Next, the operation will be described. First, in the transparent color register 680, the color data desired to be a transparent color is set by the MPU 10. Similarly, 1 is recorded in the effective bit register 700 for valid bits of the transparent color register 680, and 0 is recorded for other bits. The comparator 600 compares the real display data 100 with the contents of the transparent color register 680 pixel by pixel.
To enable. The comparison here is valid pit register 700
It is possible to have a certain width based on the value of.
The operation is exactly the same as that of the data comparator 173 described above.

The switching control circuit 620 uses the match signal 610 and the display mode signal 6 set in the display mode register 630 from the MPU 10 in advance.
A switching signal 660 is generated based on 40. The display mode signal 640 consists of 2 bits, and when it is (00), the switching signal 66
0 is always 0, and the serial display data 120 is the switching circuit 67.
It is selected at 0 and is sent to the DA converter 150 as the digital image output 140. When the display mode signal 640 is (01), the switching signal 660 is always 1 and the serial display data 100 is selected. When the display mode signal 640 is (10) or (11), the coincidence signal 610 is directly input to the switching circuit 670. In this display mode, the transparent color register 68 is
0 and valid bit register 700 to the reference register 500
And by setting the same value as the setting value of the valid bit register 520, the digital image output 140 becomes a signal forming a superimposed image with the serial display data 120 as the background and the serial display data 100 as the foreground. This is the overlay mode described above. The transparent color register 680 and the effective bit register 700 in FIG. 4 have exactly the same configuration and function as the reference register 500 and the effective bit register 520 shown in FIG. 3, and therefore both can be shared.

According to this embodiment, without providing a mask memory,
There is an effect that mask composition can be performed at high speed by using the DMAC. Moreover, since the final image can be confirmed and corrected on the screen before the data is actually transferred, the composition can be performed, and therefore the number of failures is small and the usability is good. If prior confirmation of the final image is unnecessary, the memory of the transfer source is not limited to the display memory and may be the main memory. Therefore, it is possible to omit one series of the display memory and reduce the circuit scale.

Further, even when the display memory has two series, the transparent color register 680, the reference register 500, and the effective bit registers 700 and 520 are commonly used, so that the circuit scale can be reduced and the registers to be set can be set. Usability improves as the number decreases.

<Second Embodiment> Next, a second embodiment of the present invention will be described with reference to FIG. The basic configuration of this embodiment is the same as the first configuration shown in FIG.
The display memory R / W control unit 170 is similar to the embodiment of FIG.
The configuration and operation of are different. Among the constituent elements in FIG. 5, those which are the same as the constituent elements in FIG. 1 and FIG.
The same reference numerals are given.

In FIG. 5, 700 is a display memory 9 as a new component.
Parallel display data of 0, 710 is parallel display data of the display memory 110, 720 is a buffer for controlling the connection between the parallel display data 700 and the MPU data 20, 730 is a control signal of this buffer 720, 740 is parallel display data 710. 750 is a control signal for the buffer 740, 760 is transfer data, 770 is a buffer for inputting the transfer data 760 to the display memory 110, and 780 is a control signal for the buffer 770.

Next, the operation of this embodiment will be described focusing on the points different from the first embodiment. In this embodiment, the display memories 90 and 110 are
Each pixel has 8 bits for each of R, G, and B with a total of 24 bits. Meanwhile, MPU
Since the bus width of data 20 remains 16 bits, one MP
It is not possible to read / write all data for one pixel by accessing from U10 or DMAC210. Transfer mode register 17
In the normal mode designated by 4, two addresses are assigned to the data for one pixel, and the data for one pixel is read and written by two accesses. Where the parallel display data 70
0,710 is 24-bit width data, and when the buffer 720 accesses an even address, the upper 16 bits,
When accessing an odd address, the remaining 8 bits are MPU
Connect to data 20. Therefore, data for one pixel is stored in two consecutive addresses, and the control signals 730 and 750 control the buffers 720 and 740 depending on whether the least significant bit of the MPU address 30 is 1 or 0.

On the other hand, when the composite transfer mode is set in the transfer mode register 174 and the display memory 90 which is the transfer source is read from the DMAC 210 or MPU 10, all 24 bits of the data of the pixel are output as the parallel display data 700. At this time, the fetch signal 175 is enabled and the register 172 fetches all 24 bits. This 24-bit data is discriminated by the data comparator 173 as to whether it is the background color or not, and the mask signal 176 is generated. On the other hand, the transfer data 760 is also input to the buffer 770.
If the transfer data 770 is not background color data,
Mask signal 176 remains invalid and address decoder 1
When the address of the display memory 110, which is the transfer destination, is selected, 71 separates the parallel display data 710 and the MPU data 20 by using the buffer 740 via the control signal 750. At the same time, the transfer data 760 is input as parallel display data 710 to the display memory 110 by the buffer 770 via the control signal 780. At this time, the valid signal 181 and the write enable signal 182 are also written in parallel in 24 bits because two consecutive addresses are validated at the same time. When the transfer data 770 is background color data, the mask signal 176 is validated and the valid signal 181 and the write enable signal 182 are prohibited as in the first embodiment. No writing or transfer is performed. Similarly, the mask composition is completed by updating the transfer source and transfer destination addresses in units of two addresses.

According to the present embodiment, even if the data for one pixel exceeds the bus width of MPU data, it is possible to determine and control the necessity of transfer in pixel units, and the transfer speed is less than or equal to the bus width of MPU data. Same and fast.

<Third Embodiment> Next, a third embodiment of the present invention will be described with reference to FIG. The overall structure of this embodiment is the same as that shown in FIG. The configuration of the data comparator 173 in the display memory R / W control unit 170 is different from that of the first embodiment. FIG. 6 shows the configuration of the data comparator 173 according to this embodiment.

In FIG. 6, 800 is blue transfer data, 810 is green transfer data, 820 is red transfer data, 830,840 and 850 are address switching circuits, 860,870 and 880 are rewritable memories with a data width of 1 bit and an address length of 8 bits or more, and 890,900 and 910 are the memories. This is a write signal generated when the MPU 10 writes data to the 860, 870, 880.

Next, the operation of this embodiment will be described with reference to FIG. The register 172 stores the 24-bit parallel display data 700 for one pixel read from the display memory 90 which is the transfer source. This data is input to the switching circuits 830, 840, 850 as 8-bit transfer data 800, 810, 820 for each R, G, B component. In the switching circuits 830, 840, 850, the transfer data 800, 810, 820 are normally input to the address terminals of the memories 860, 870, 880 as they are. The memories 860, 870, 880 output 1 as the valid signals 570, 590 for each color when the transfer data 800, 810, 820 for each color input to the address terminals are in the designated area, and 0 otherwise. In the NAND gate 600, when the three input signals are all 1, the mask signal 176 is validated. The memories 860, 870 and 880 are rewritable memories having at least 1 bit width and 256 addresses, and are MPU10.
1-bit data can be written directly from. MPU10
Generates addresses for the three memories for writing data, the write signals 890, 900, 910 are validated, and the write signals are input as switching control signals. Switching circuits 830, 84
0,850 inputs MPU address 30 into memories 860,870,880. The write signals 890,900,910 are stored in the memories 860,870,880.
Is also given to each write enable terminal of, and the MPU data 20 when each write signal is validated is written to the address. The data setting method for the memories 860, 870 and 880 is as follows. For example, if you want to use it as the background color when the level of blue is 200 levels or more out of 256 levels and the levels of green and red are 50 or less, 0 is the address 0 to 199 of the memory 860 for blue. It is sufficient to write 1 as data in 200 to 255, 0 in addresses 0 to 49 of the green and red memories 870 and 880, and 1 to 50 to 255 in advance. For the actual data setting, the average pixel data of the background color area whose coordinates are specified by the coordinate input device is read, and each color component has a separately specified width centered on that value, and 1 is set in the corresponding address range. writing,
By clearing 0 in other areas in advance, settings and changes can be made easily.

According to the present embodiment, it is possible to specify the background color range for each color component in units of one level. Also, the circuit can be simplified by using a memory.

Although the above description has been made with respect to the data comparator 173, a similar circuit is applied to the display synthesizing unit 130, and the comparison circuit 6 is used.
It is self-evident that the 00, the transparent color register 680 and the valid bit register 700 can be replaced by a memory. At that time, if the address of the memory of the display synthesizing unit 130 is the same as that of the data comparator 173, it is possible to share the address decoder and simplify the setting procedure.

Further, in the above three embodiments, all the transfer destination memories are fixed, but by adding a circuit to the display memory R / W control unit 170 etc., the display memory 90 can be set as the transfer destination, or bidirectional. It can be easily understood by those skilled in the art.

EFFECTS OF THE INVENTION According to the present invention, it is possible to determine whether or not the image is a foreground image in a circuit and perform image mask composition by high-speed block transfer using DMAC. It can be several to several tens of times faster than in some cases.
Further, since a high-speed mask memory is not required, the circuit scale is reduced, the cost is reduced, and the usability is improved by omitting the data setting procedure for the mask memory.

[Brief description of drawings]

1 is a configuration diagram of an embodiment of the present invention, FIG. 2 is a more detailed configuration diagram of a part of FIG. 1, FIG. 3 is a more detailed configuration diagram of a part of FIG. 2, and FIG. FIG. 5 is a more detailed block diagram of a part of FIG. 1, FIG. 5 is a block diagram of a second embodiment of the present invention, and FIG. 6 is a block diagram of a third embodiment of the present invention. 90 …… Display memory 110 …… Display memory 130 …… Display composition section 170 …… Display memory R / W control section 171 …… Address decoder 172 …… Register 173 …… Data comparator 210 …… DMAC

Claims (4)

[Claims] 1. An image synthesizing apparatus for synthesizing a first image and a second image, comprising: a first display memory storing first image data representing the first image; and a second display memory representing the second image. A second display memory for storing the image data of, a receiving unit that selectively receives an instruction to generate a composite image and an instruction to display a composite image, and the receiving unit receives an instruction to generate a composite image In addition, a first comparing unit that compares the second image data read from the second display memory with a preset value for each unit of predetermined image data, and the receiving unit generates a composite image. Is received, the second image data read from the second display memory is displayed in the first display for each unit of the predetermined image data according to the comparison result of the first comparing unit. Write to control whether to write to memory Only the first image data stored in the first display memory and the second image data stored in the first display memory in units of predetermined image data when the receiving unit receives the instruction to display the composite image. A unit for sequentially reading the second image data stored in the display memory at a predetermined cycle; and, when the receiving unit receives an instruction to display the composite image, the unit for each predetermined image data unit Second comparing means for comparing the second image data read from the second display memory with the set value; and the first means when the receiving means receives an instruction to display a composite image. Selecting means for selecting one of the read first image data and second image data for display for each unit of the predetermined image data according to the comparison result of the comparing means; , Change the set value Image synthesizing apparatus characterized by having means. 2. The image synthesizing apparatus according to claim 1, wherein the set value indicates a value range of image data, and the first comparing unit is configured to output the second display memory from the second display memory. When the read second image data is within the range of the value of the image data indicated by the set value, the first match signal is output, and the write control unit outputs the first match signal. In the case where the second image data is written, the writing of the second image data to the first display memory is prohibited, and the first comparing means sets the second image data read from the second display memory to the set value. Output the first match signal when the value is within the range of the value of the image data, and the selecting unit selects the first image data when the second match signal is output, If the second match signal is not output, the second image data is output. Image synthesizing apparatus and selects the data. 3. The image synthesizing apparatus according to claim 1, wherein the first comparing means is the second comparing means when the receiving means receives an instruction to display a composite image. An image synthesizing device characterized by being used as. 4. The image synthesizing apparatus according to claim 1, wherein the first comparing means and the second comparing means include the second comparing means.
An image synthesizing device, which is a rewritable memory that inputs image data as an address and outputs a comparison result as data.