JPH0775623B2 - Pacemaker pulse detection circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pacemaker pulse detection circuit, and more particularly, to a pacemaker pulse detection circuit which receives electrocardiographic information from a patient in which an artificial pacemaker device is implanted, that is, a subject.

[0002]

2. Description of the Related Art Conventionally, in an electrocardiogram analyzer, electrocardiogram information input from electrodes attached to a subject is detected and sent to the main body side by optical communication or the like for analysis. In this case, the signals input from the electrodes during the measurement are amplified by the main amplifier section and the like, and then are analog / digital (A / D) converted and sequentially stored as data in the memory. In addition, after the 1 to 10 [KHz] portion, which is the frequency component of the pacemaker pulse, is extracted, its level is determined, and only the portion exceeding a certain level is detected as a pulse, and the data in the memory is stored. The data corresponding to the pulse portion was sent to the main body as a pacemaker pulse.

[0003]

Since the above processing is realized by hardware, 1 to 10 may be added during measurement.
When high-frequency noise of [KHz] was mixed in, a pacemaker pulse was sometimes erroneously detected. The high frequency noise of 1 to 10 [KHz] is attenuated by the frequency characteristic of the main amplifier section. Therefore, since it does not appear as noise in the print result of the printer (recorder) on the main body side, it cannot be determined as false detection due to noise,
Actually, there is a drawback that an erroneous diagnosis is made because there is a pulse even though it is a portion where there is no pulse in the electrocardiogram signal.

Here, as a measure for judging the normality of the operation of the artificial pacemaker device, there is a technique described in Japanese Patent Application Laid-Open No. 2-302274. This technique calculates the time interval between the pacemaker pulse and the P wave or R wave on the electrocardiogram waveform and compares it with the preset expected value, and determines whether the operation of the artificial pacemaker device itself is normal or not. To do. Therefore, it is premised that the pacemaker pulse detection processing is normally performed, and even if this technique is used, there is a drawback that an erroneous diagnosis is still performed when the noise is mixed.

The present invention has been made to solve the above-mentioned conventional drawbacks, and an object of the present invention is to provide a pacemaker pulse detection circuit in which erroneous diagnosis is not performed even if high frequency noise is mixed. is there.

[0006]

In order to solve the above-mentioned conventional problems, the pacemaker pulse detection circuit according to the present invention comprises means for judging whether or not the level of an input signal is higher than a predetermined threshold level, and Pulse output means for outputting a pulse corresponding to a portion of the input signal that is determined to be higher than the threshold level, and pulse width and pulse interval values of each output pulse from the output means are compared and determined with predetermined expected values. It is characterized in that only the output pulse which is judged to be valid by the judging means is treated as a pacemaker pulse among the output pulses.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an embodiment of a pacemaker pulse detection circuit according to the present invention. In the figure,
In the pacemaker pulse detection circuit according to the embodiment of the present invention, the signal from the electrode attached to the subject is the preamplifier 1
After being amplified by A, it is further amplified by main amplifier 2
The signals are sequentially input to the / D conversion circuit 3. The data digitized by the A / D conversion circuit 3 is sequentially input and held in the memory 5 under the control of the CPU 4. Regarding the data held in the memory 5, only the portion corresponding to the pulse of the electrocardiogram signal has to be sent to the main body side not shown,
For this reason, the parts a and b in the figure are provided.

The section a compares a high-pass filter (HPF) 6 which outputs a signal of 1 to 10 [kHz] with respect to the signal amplified by the preamplifier 1, and compares the signal after passing the filter with a predetermined threshold level. And a one-shot circuit 8 that outputs a pulse having a predetermined width in response to the transition timing of the signal in the portion exceeding the threshold level. The output pulse of the one-shot circuit 8 is input to the b section.

The section b is a rising / falling detecting section 9 for detecting the rising and falling timings of the output pulse of the one-shot circuit 8 and whether the pulse is an original pacemaker pulse based on the detection result. It is configured to include a pulse determination unit 10 that determines whether it is due to noise. And, this part b is a one-shot circuit 8
The pulse width and the pulse interval of the output pulse are calculated and compared with a predetermined expected value, and the determination result is sent to the CPU 4. Of the data in the memory 5, the CPU 4 sends only the data determined to be valid from the determination result to the main body (not shown).

The principle of the pulse width determination and the pulse interval determination in the part b will be described with reference to FIGS. 2 and 3. These determinations are made depending on whether or not the count value of the counter is within a predetermined expected value range.

First, referring to FIG. 2, there is shown an output pulse of the one-shot circuit. In FIG. 2A, an output pulse w1 having a normal pulse width is shown, and in FIG. An output pulse w2 having an abnormal pulse width due to high frequency noise or the like is shown. That is, the output pulse w1 is determined to be normal because the pulse width is within the range of the expected value W. On the other hand, for the output pulse w2, the pulse is continuously output from the one-shot circuit, and the rising and falling edges of individual pulses cannot be detected,
Since the pulse width is outside the range of the expected value W, it is determined to be abnormal. Regarding the value of W, the output pulse width of the one-shot circuit is, for example, 30 to 40 [mS].
If it is set to W, W = 40 [mS] may be set.

Next, referring to FIG. 3, the output pulse of the one-shot circuit is also shown. In FIG. 3A, the output pulse t1 having a normal pulse interval is shown in FIG. Indicates an output pulse t2 having an abnormal pulse interval due to high-frequency noise or the like. That is, the output pulse t1 is determined to be normal because the pulse interval is larger than the expected value T. On the other hand, for the output pulse t2,
The one-shot circuit outputs pulses at short time intervals, and since the pulse interval is smaller than the expected value T, it is determined to be abnormal. The value of T may be T = 400 [mS] (60/150 [S]) when the maximum heart rate of a healthy person is considered to be about 120 and 150 or more is abnormal.

In the present embodiment, the above determination process is realized by a program by firmware, and the CPU 4
Shall be executed by.

Next, the structure of the portion b in FIG. 1 will be described.

FIGS. 4 to 9 are flowcharts showing the processing procedure when the section b in FIG. 1 is realized by a program by firmware. 4 and 5 show rising / falling detection processing, and FIGS. 6 to 9 show pulse width and pulse interval comparison / determination processing.

Here, the meaning of the abbreviations in the flow charts of FIGS. 4 to 9 will be described with reference to FIGS.

FIG. 10 shows pulses input from the portion b to the portion a. Pstatus in the figure indicates the level of the pulse. That is, it indicates that the level is “0” when Pstatus = 0 and the level is “1” when Pstatus = 1. Also, "Prise-flg" in the figure is a flag that becomes "1" when it is determined that the rising edge of the pulse is detected, and
wn-flg is a flag that becomes “0” when it is determined that the falling edge of the pulse has been detected. That is, the rise or fall of the pulse can be detected by the change of the value of Pstatus, and the value of Prise-flg or Pdown-flg is set accordingly.

On the other hand, FIG. 11 also shows pulses input from the portion b to the portion a. Plcunt in the figure is the time from the falling edge of one pulse to the rising edge of the next pulse, and Plcunt
Cunt is the time from the fall of one pulse to the fall of the next pulse. Therefore, the pulse interval can be determined by Pcunt, and the pulse width can be determined by Pcunt-Plcunt.

First, the rising / falling detection process will be described.

In FIG. 4, the contents of the output port of part a,
That is, the output signal of the one-shot circuit 8 is sampled (step 41). This sampling is CPU4
Is performed every 2 [mS]. That is, FIGS.
Will be performed in a cycle of 2 [mS].

It is judged whether or not a pulse is detected in the sampling result (step 42). When a pulse is detected, the value of Pdown-flg is set to "0" and then Pst
It is determined whether or not atus is "1" (step 43 → 4).
4). When Pstatus is "1", set Prize-flg to "0".
(No rise), set Pstatus to "1" (level 1),
The rising / falling edge detection process ends (step 44 →
45 → 47). In other words, even if a pulse is detected, if Pstatus is already "1", it is determined that the level is still "1", and it is not the rising point of the pulse, and Prize-flg becomes "0". .

On the other hand, if Pstatus is "0", then Prize-f
The lg is set to "1" (rising), Pstatus is set to "1" (level 1), and the rising / falling detection processing ends (steps 44 → 46 → 47). In other words, when a pulse is detected and Pstatus is "0", it is determined that the level has changed from "0" to "1", and the value of Prize-flg is "1" as the rising point of the pulse. Is set to.

When no pulse is detected in step 42, it is determined whether Pstatus is "1" (step 42 in FIG. 4 → step 51 in FIG. 5).

When Pstatus is "1", the value of Pdown-flg is set to "1" (falling) (step 51 → 5).
2). That is, when Pstatus is "1" but no pulse is detected, it is determined that the pulse level has changed from "1" to "0", and it is determined that the pulse is at the falling point. The value of Pdown-flg is set to "1".

On the other hand, when Pstatus is "0", Pdown-f
Set the value of lg to “0” (no fall) (step 51 →
53). That is, when Pstatus is "0" and no pulse is detected, it is determined that the pulse level is still "0", and the value of Pdown-flg is "not the falling point of the pulse". It is set to "0".

When the setting of Pdown-flg is completed, Prise-flg
After P and Pstatus are both set to "0" (no rising, level 0), the rising / falling detection process ends (step 54 in FIG. 5 → step 47 in FIG. 4).

Next, the process of comparing and determining the pulse width and the pulse interval will be described.

In this process, Pcunt and Plcunt are calculated by, for example, operating and stopping the counter at the rising and falling points detected in the processes of FIGS. 4 and 5.
Then, it is determined whether or not the pulse interval and the pulse width are within the expected value range. In the following description, the count value of the expected value of the pulse interval is T, and the count value of the expected value of the pulse width is W. In this example, a 16-bit counter is used, and measures are taken when it overflows.

First, in FIG. 6, the value of Prise-flg is judged (step 61).

If the value of Prize-flg is "1" (rising), the value of the counter (cunter) is put in Plcunt, and PCS-f
After setting lg to “0”, the counter is incremented by 1 (step 61 → 62). PCS-flg is a flag for stopping the counter when it overflows. When the value is "1", it means that it has overflowed, and when it is "0", it means that it has not overflowed. .

After the counter is incremented by 1 in step 62, it is determined whether the counter overflows (step 63). If the counter has not overflowed, Pm-flg is set to "0" and the processing ends (steps 64 → 66). Pm-flg indicates whether the pulse is valid or not. When the value is "1", it means valid, and when it is "0", it means not valid. That is, in this case, it is determined that the pulse is not valid.

If the counter overflows in step 63, the counter and Plcunt are set to "0", and then the counter is incremented by 1 and the process is terminated (steps 65 → 66).

In step 61, if the value of Prise-flg is "0" (no rise), the value of Pdown-flg is judged (step 71 in FIG. 7).

If the value of Pdown-flg is "1", the value of the counter is put in Plcunt and PCS-flg is set to "0".
The counter is set to "0" (reset) and further incremented by 1 (steps 71 → 72).

When the value of Pcunt, that is, the pulse interval is "0", Pm-flg is set to "0" (step 7).
3 → 74) The process ends (step 66 in FIG. 6).

If the value of Pcunt is not "0" and the value of Plcunt is "0" (step 73 → 75), it is judged whether or not the value of Pcunt is between the count value 0 and the expected value W. (Step 76). If it is in the meantime, Pm-flg is set to "1" and the process ends (step 76 → 7).
7 → step 66 of FIG. 6).

On the other hand, if it is not within the range, the processing is finished as it is (step 76 → step 66 in FIG. 6).

When the values of Pcunt and Plcunt are not "0", it is judged whether the value of Pcunt-Plcunt, that is, the pulse width is between the count value 0 and the expected value W (step 73 → 75). → Step 81 in FIG. 8), and if there is any time, then it is determined whether or not the value of Pcunt, that is, the pulse interval is larger than the expected value T (Step 81 →
Step 82).

When the value of Pcunt-Plcunt is between the count value 0 and the expected value W and the value of Pcunt is larger than the expected value T, Pm-flg is set to "1" and the processing is terminated. (Step 83 → Step 66 in FIG. 6). That is,
In this case, it is determined that the pulse is valid.

Whether the value of Pcunt-Plcunt is not between the count value 0 and the expected value W (step 81 → 84), or P
When the value of cunt is smaller than the expected value T (step 82 → 8)
In step 4), Pm-flg is set to "0", and the process ends (step 84 → step 66 in FIG. 6). That is, in this case, it is determined that the pulse is not valid.

If the value of Pdown-flg is "0" in step 71 of FIG. 7, the value of PCS flg is judged (step 91 of FIG. 9).

If the value of PCS-flg is "1", Pm-flg
Is set to “0” and the process is completed (step 91 →
95 → step 66 of FIG. 6). That is, in this case, it is determined that the pulse is not valid.

If the value of PCS flg is "0", after incrementing the counter by 1, it is determined whether or not the counter is overflowing (steps 91 → 92 → 9).
3). If the counter overflows, the PC
After setting the value of S-flg to "1", the counter is set to "0", Pm-flg is set to "0", and the processing ends (step 93 → 94 → 95 → step 66 in FIG. 6). . If the counter has not overflowed, Pm-flg is set to "0" and the processing ends (step 93 → 9).
5 → Step 66 of FIG. 6).

Only the data of the portion determined to be a legitimate pulse by the above determination processing, that is, the portion corresponding to the pacemaker pulse of the electrocardiogram information is read from the memory 5 and sent to the main body side not shown. . As a result, even if high frequency noise is mixed, the main body side will not be erroneously diagnosed.

Although the determination process of the pulse width and the pulse interval in the above embodiment is realized by firmware, it is obvious that the invention is not limited to this and can be constituted by firmware using a flip-flop or the like.

[0046]

As described above, according to the present invention, the input pulse is judged by the pulse width and the pulse interval, and only the pulse judged to be valid by the judgment result is treated as the pacemaker pulse. Even if noise is mixed, there is an effect that a false diagnosis is not made.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a pacemaker pulse detection circuit according to an embodiment of the present invention.

FIG. 2 is a waveform diagram showing a case where the pulse width is normal and a case where the pulse width is not normal.

FIG. 3 is a waveform diagram showing a case where the pulse interval is normal and a case where the pulse interval is not normal.

FIG. 4 is a flowchart showing a rising / falling determination processing procedure in a part b of FIG. 1.

5 is a flowchart showing a rising / falling determination processing procedure in a part b of FIG. 1. FIG.

FIG. 6 is a flowchart showing a procedure for determining a pulse width and a pulse interval in part b of FIG.

FIG. 7 is a flowchart showing a procedure for determining a pulse width and a pulse interval in part b of FIG.

FIG. 8 is a flowchart showing a procedure for determining a pulse width and a pulse interval in part b of FIG.

9 is a flowchart showing a procedure for determining a pulse width and a pulse interval in the part b of FIG.

10 is an explanatory diagram of meanings of abbreviations in FIGS. 4 to 9. FIG.

FIG. 11 is an explanatory diagram of the meaning of abbreviations in FIGS. 4 to 9.

[Description of symbols] 1 preamplifier 2 main amplifier 3 A / D conversion circuit 4 CPU 5 memory 6 high-pass filter 7 comparator 8 one-shot circuit 9 rising / falling detection unit 10 pulse determination unit

Claims (2)

[Claims] 1. A means for determining whether the level of an input signal is higher than a predetermined threshold level, and a pulse output means for outputting a pulse corresponding to a portion of the input signal determined to be higher than the threshold level. And a determination means for determining the pulse width value of each output pulse from this output means with a predetermined expected value, and only the output pulse which is determined to be valid by the determination means is output. A pacemaker pulse detection circuit characterized in that it is handled as a pacemaker pulse. 2. A means for determining whether the level of an input signal is higher than a predetermined threshold level, and a pulse output means for outputting a pulse corresponding to a portion of the input signal determined to be higher than the threshold level. And a determining means for comparing and comparing the value of the pulse interval of each output pulse from this output means with a predetermined expected value, and among the respective pulses of the output pulse, the determining means determines that the output interval is valid. Pacemaker pulse detection circuit characterized in that only things are handled as pacemaker pulses.