JPH0771300B2 - Digital type phase lock circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital phase lock circuit of a digital video device for digitally processing a video signal.

[Prior Art] FIG. 3 shows, for example, the 1980 Television Society National Convention Proceedings.
16-5 (P367,368) shows an example of a digital phase lock circuit in a conventional digital video device.

In the figure, (1) is an A / D conversion circuit for converting an analog video signal into digital data, (2) is a digital signal processing circuit for processing a video signal converted into digital data by the A / D conversion circuit (1), (3) is a sync separation circuit that generates a burst gate pulse in a burst signal period from an analog video signal, and (4) is a burst gate pulse from the sync separation circuit (3), and takes in data of a burst signal portion to calculate a phase error Phase error calculation circuit,
(5) is an integration circuit that compensates for the phase locked loop, (6) is a D / A conversion circuit that converts the phase error data into an analog voltage, and (7) is oscillated by the output error voltage of the D / A conversion circuit (6). Conversion clock generation circuit (VCX that can change frequency)
O) and (8) are wobbling circuits that change the conversion clock phase.

FIG. 4 is a diagram showing the quantization range of the video signal, FIG. 5 is a diagram showing sampling points in the burst signal portion of the video signal, and FIG. 6 is a diagram showing phase comparison characteristics without wobbling. FIG. 7 is a diagram showing phase comparison characteristics when wobbling.

Next, the operation will be described. In FIG. 3, the input video signal is set by the A / D conversion circuit (1), for example, the conversion clock is set to four times the color subcarrier fsc (4fsc = 14.3 MHz), and the reference voltage ( The reference voltage is RefV and the horizontal sync signal (H SYN
The C level from the lowest level (SYNC TIP) of C) to the peak level including the color signal is quantized by 8 bits.
Here, in order to match the sampling points in each horizontal scan, the conversion clock phase is generally controlled so as to have a constant phase difference with respect to the burst phase. This method will be described below.

As shown in FIG. 5, there are always four sampling points in the burst period, such as P _{1 to} P _4K , in one burst period. This data is taken into the phase error calculation circuit (4) by the burst gate pulse from the sync separation circuit (3). From SYNC TIP to pedestal level a, the up burst amplitude level b, and the phase difference between the burst signal and the conversion clock theta, when the target value of the phase difference and theta _o, the phase error calculating circuit (4) in the following manner Performs various calculations.

However, P _4j-3 = a + b sin θ …… (2) P _4j-2 ＝ a + b cos θ …… (3) P _4j-1 ＝ a + b sin θ …… (4) P _4j ＝ a−b cos θ …… (5) is there. Therefore, the error calculation result is as in the following expression (6).

However, as shown in FIG. 6, the phase comparison characteristic has a dead zone Δθ _o due to the quantization accuracy of A / D conversion. Therefore, in order to reduce the dead zone Δθ _o , the wobbling circuit (8) wobbling only the phase of the exchange clock corresponding to the burst signal portion by Δθ _o / k for each cycle of the burst signal, and the error calculation is performed every K cycle. . Therefore, the phase characteristic shifts in the phase axis direction by the following equation (7) for each cycle of the burst signal and becomes an added value from j = 1 to K.

(However, j = 1,2, ..., k) That is, the calculation of the phase error is the following equation (8), The dead zone is Δθ _o / k. Therefore, the phase error E is obtained from the equation (8) in the error calculation circuit (4), integrated by the integration circuit (6), and then converted into the phase error voltage by the D / A conversion circuit (6). The voltage controls the conversion clock oscillation circuit (VCXO) (7).

[Problems to be Solved by the Invention] Since the conventional digital phase-locked loop circuit is configured as described above, in consideration of the influence of the wobbling waveform on the image signal, the dead band width practically sufficient by 8 bit quantization. To obtain Δθ _j , a burst signal for 2 horizontal scanning periods is required, phase synchronization cannot be achieved within 1 horizontal scanning period, and there is a problem that image quality is deteriorated due to jitter or the like.

The present invention has been made to solve the above problems, and an object of the present invention is to obtain a digital phase synchronization circuit capable of establishing phase synchronization within one horizontal scanning period.

[Means for Solving the Problems] A digital phase synchronization circuit according to the present invention is an A / D conversion circuit for quantizing an analog video signal with a predetermined conversion clock, and a color quantized by the A / D conversion circuit. Color burst signal phase and A /
The phase difference detection means for detecting the phase difference with the conversion clock input to the D conversion circuit and using it as the phase error signal, and the phase of the conversion clock is changed by the phase error signal output from the phase difference detection means. A conversion clock generation circuit that changes the quantization phase of the D conversion circuit, and a level range to be quantized in the A / D conversion circuit for a predetermined period including at least the color burst signal period other than the video signal period in the analog video signal And a reference voltage switching means for switching to a level range for improving accuracy.

[Operation] The means for switching the reference voltage applied to the A / D conversion circuit in the present invention is to quantize only the horizontal synchronizing signal and the burst signal period by the horizontal synchronizing signal (H SYNC) and the reference voltage switching pulse made from the burst gate. The reference voltage is switched so that the level range becomes narrow. Therefore, the quantization accuracy in the period is improved, and the dead band width Δθ in the phase error calculation circuit can be reduced, so that the phase synchronization can be achieved within one horizontal scanning period.

[Embodiment of the Invention] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block circuit diagram showing the digital type phase locked loop circuit of this embodiment. Reference numerals (1) to (8) show the same components as those of the conventional example of FIG. In the figure, (9)
From the horizontal sync signal (H SYNC) and burst gate,
A reference voltage switching pulse generation circuit that generates a reference voltage switching pulse. (10) RefV determines the reference voltage of the A / D conversion circuit by the reference voltage switching pulse.
Or it is a reference voltage switching switch that switches to 1/2 RefV.

FIG. 2 is a diagram showing the quantized level ranges c and d of the video signal switched in the A / D conversion circuit of this embodiment and the timing of the reference voltage switching pulse.

Next, the operation will be described.

As shown in FIG. 1, the digital phase lock circuit operates basically in the same manner as the conventional one, but the reference voltage of the A / D conversion circuit (1) is changed to the reference voltage switching switch (1).
0), the voltage of RefV and RefV, which is the same as the conventional one, is halved 1 /
2 Switch to RefV. The reference voltage switching pulse (shown in FIG. 2 (d)) is detected by the sync separation circuit (3) from the analog video signal to detect the horizontal sync signal and the burst gate, and the reference voltage switching pulse generation circuit (10) detects the horizontal sync signal. A pulse from the falling edge of (H SYNC) (shown in FIG. 2 (b)) to the falling edge of the burst gate (shown in FIG. 2 (c)) is generated, and the reference voltage is set to 1 only during this pulse period (HIGH level). / 2RefV, and during other video signal periods (LOW level), the reference voltage is switched to RefV as before. Therefore, the horizontal sync signal (H SYN
8b for the level range c (c in FIG. 2 (a)) from the lowest level (SYNC TIP) of C) to the peak level including the color signal.
It is quantized, but during the HIGH level period of the reference voltage switching pulse, that is, during horizontal synchronization (H SYNC) and burst signal period, half the level range d (d in FIG. 2 (a)) is quantized by 8 bits. become. In this case, burst signal sample points P _{1 to} P _4K (see FIG. 5 (a))
, The quantization accuracy is doubled compared to the video signal period, and if the wobbling is performed for the same period as in the conventional example, the dead band width of the phase comparison characteristic in the phase error calculation circuit (4) is half the conventional Δθ _o / 2k. Becomes Accordingly, practically sufficient performance can be obtained in half the horizontal scanning period, and the phase synchronization can be performed for each horizontal scanning period.

Generally, in the digital video signal processing, since the processing is performed on the video signal portion, the data of the horizontal synchronizing signal (H SYNC) and the burst portion do not directly affect the video. Also, by halving the digital data of this portion, the quantization accuracy of the video signal portion can be made to substantially match.

In the above embodiment, the case of the digital type phase locked loop has been described, but the quantizing accuracy is high even when applied to the clamp circuit for detecting the horizontal sync signal after quantization or the level judgment in the digital system. The effect is obtained.

As described above, according to the present invention, the level range to be quantized in the A / D conversion circuit is quantized for a predetermined period including at least the color burst signal period other than the video signal period in the analog video signal. Since the reference voltage is switched to a level range that enhances accuracy, there is an effect that a digital type phase synchronization circuit capable of performing phase synchronization every horizontal scanning period can be obtained with the same A / D conversion circuit as in the related art.

[Brief description of drawings]

FIG. 1 is a block circuit diagram of an embodiment of the present invention, FIG. 2 is a diagram showing a quantization range and timing of a video signal of this embodiment, and FIG. 3 is a block circuit diagram of a conventional digital phase lock circuit. FIG. 4 is a diagram showing the quantization range of the video signal of this conventional example, FIG. 5 is a diagram showing sampling points in the burst signal portion of the video signal, and FIG.
FIG. 7 is a phase comparison characteristic diagram without wobbling, and FIG. 7 is a phase comparison characteristic diagram with wobbling. (1) …… A / D conversion circuit, (3) …… Synchronous separation circuit,
(4) ... phase error calculation circuit, (7) ... conversion clock generation circuit, (8) wobbling circuit, (9) ... reference voltage switching pulse generation circuit, (10) ... reference voltage switching switch. In each figure, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1. An A / D conversion circuit for quantizing an analog video signal with a predetermined conversion clock, and a phase of the color burst signal from the data of the color burst signal part quantized by the A / D conversion circuit and the A The phase difference detection means for detecting the phase difference with the conversion clock input to the / D conversion circuit and using it as the phase error signal, and the phase of the conversion clock is changed by the phase error signal output from the phase difference detection means. the above
A conversion clock generation circuit that varies the quantization phase of the A / D conversion circuit, and a level that is quantized in the A / D conversion circuit for a predetermined period including at least a color burst signal period other than the video signal period in the analog video signal. A digital phase-locked circuit having reference voltage switching means for switching the range to a level range that enhances quantization accuracy.