JPH0766982B2 - Wavelength selective light receiving element - Google Patents
Wavelength selective light receiving elementInfo
- Publication number
- JPH0766982B2 JPH0766982B2 JP1079800A JP7980089A JPH0766982B2 JP H0766982 B2 JPH0766982 B2 JP H0766982B2 JP 1079800 A JP1079800 A JP 1079800A JP 7980089 A JP7980089 A JP 7980089A JP H0766982 B2 JPH0766982 B2 JP H0766982B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- light receiving
- wavelength
- region
- spacer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000000758 substrate Substances 0.000 claims description 89
- 238000005530 etching Methods 0.000 claims description 33
- 125000006850 spacer group Chemical group 0.000 claims description 32
- 239000004065 semiconductor Substances 0.000 claims description 12
- 239000010408 film Substances 0.000 description 28
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 16
- 229910052710 silicon Inorganic materials 0.000 description 16
- 239000010703 silicon Substances 0.000 description 16
- 239000011521 glass Substances 0.000 description 14
- 238000009792 diffusion process Methods 0.000 description 12
- 229910004298 SiO 2 Inorganic materials 0.000 description 10
- 238000000034 method Methods 0.000 description 9
- 238000005304 joining Methods 0.000 description 7
- 238000004891 communication Methods 0.000 description 5
- 230000003287 optical effect Effects 0.000 description 5
- 239000000243 solution Substances 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 238000001514 detection method Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000012544 monitoring process Methods 0.000 description 4
- 239000007864 aqueous solution Substances 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000002844 melting Methods 0.000 description 3
- 230000008018 melting Effects 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- OAKJQQAXSVQMHS-UHFFFAOYSA-N Hydrazine Chemical compound NN OAKJQQAXSVQMHS-UHFFFAOYSA-N 0.000 description 2
- 229910010413 TiO 2 Inorganic materials 0.000 description 2
- 230000009471 action Effects 0.000 description 2
- 238000005452 bending Methods 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- YCIMNLLNPGFGHC-UHFFFAOYSA-N catechol Chemical compound OC1=CC=CC=C1O YCIMNLLNPGFGHC-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 230000010363 phase shift Effects 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 230000003595 spectral effect Effects 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 238000002834 transmittance Methods 0.000 description 2
- RZVAJINKPMORJF-UHFFFAOYSA-N Acetaminophen Chemical compound CC(=O)NC1=CC=C(O)C=C1 RZVAJINKPMORJF-UHFFFAOYSA-N 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- PIICEJLVQHRZGT-UHFFFAOYSA-N Ethylenediamine Chemical compound NCCN PIICEJLVQHRZGT-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910013641 LiNbO 3 Inorganic materials 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 229920000515 polycarbonate Polymers 0.000 description 1
- 239000004417 polycarbonate Substances 0.000 description 1
- 239000005297 pyrex Substances 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000003566 sealing material Substances 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
- 238000000411 transmission spectrum Methods 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B26/00—Optical devices or arrangements for the control of light using movable or deformable optical elements
- G02B26/001—Optical devices or arrangements for the control of light using movable or deformable optical elements based on interference in an adjustable optical cavity
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
- G01J3/00—Spectrometry; Spectrophotometry; Monochromators; Measuring colours
- G01J3/12—Generating the spectrum; Monochromators
- G01J3/26—Generating the spectrum; Monochromators using multiple reflection, e.g. Fabry-Perot interferometer, variable interference filters
Description
【発明の詳細な説明】 （イ）産業上の利用分野 本発明は、２枚の基板を接合により一体化したファブリ
ーペロー型可変干渉フィルターを基にした波長選択性受
光素子に関し、小型の分光器・色識別器、波長多重通信
における受光素子、カラー時分割検出型イメージセンサ
などに利用可能な、波長選択性受光素子に関するもので
ある。The present invention relates to a wavelength selective light receiving element based on a Fabry-Perot type variable interference filter in which two substrates are integrated by bonding, and a compact spectroscope. The present invention relates to a wavelength selective light receiving element that can be used for a color discriminator, a light receiving element in wavelength division multiplexing communication, a color time division detection type image sensor, and the like.
（ロ）従来の技術 一般に、この種の可変干渉フィルターでは、２枚のガラ
ス基板上にそれぞれ反射膜を形成してそれらを対向さ
せ、両基板を薄膜スペーサを介して接合することによ
り、ファブリーペロー干渉を生じる空隙が形成される。
そしてその空隙間隔に応じて光の干渉が生じ、特定波長
のみを透過するフィルター作用を生じる。また一方の基
板に力を印加して湾曲させ空隙間隔を可変することによ
って、透過波長を変化させることが可能である。(B) Conventional technology Generally, in this type of variable interference filter, a reflective film is formed on each of two glass substrates, and they are made to face each other, and both substrates are bonded to each other through a thin film spacer. An air gap is created that causes interference.
Then, light interference occurs in accordance with the gap distance, and a filter action that transmits only a specific wavelength is generated. In addition, it is possible to change the transmission wavelength by applying a force to one of the substrates to bend it and vary the gap spacing.
この可変干渉フィルターは光路を曲げずに波長選択を行
うことができるため、回転機構などの機械的動作部分が
不要であり、また発光素子あるいは受光素子を可変干渉
フィルターに接して設置することができるため、システ
ム全体を小型化できる。Since this variable interference filter can perform wavelength selection without bending the optical path, it does not require a mechanical operation part such as a rotating mechanism, and a light emitting element or a light receiving element can be installed in contact with the variable interference filter. Therefore, the entire system can be downsized.
ここで、可変干渉フィルターの一方のガラス基板を半導
体フォトディテクタに置き換えた一体型の波長選択性受
光素子が、従来、提案されている（特願昭61−102989号
参照）。Here, an integrated wavelength selective light receiving element in which one glass substrate of the variable interference filter is replaced with a semiconductor photodetector has been conventionally proposed (see Japanese Patent Application No. 61-102989).
すなわち、これは、受光素子とファブリーペロー型可変
フィルターを一体型とするこにより両者の位置合わせが
不要となり取り扱いが容易になるとともに、素子間の界
面が減ることにより光量ロスが減少するなどの利点を有
する。That is, this is an advantage that the light receiving element and the Fabry-Perot type variable filter are integrated so that they do not need to be aligned and handling is easy, and the interface between elements reduces the loss of light quantity. Have.
（ハ）発明が解決しようとする課題 受光素子と透光性基板とを接合し、両基板間に形成され
る微細空洞において生じるファブリーペロー干渉を利用
して波長選択を行う素子において重要な点は、空洞間隔
を適当な駆動力で制御できるかどうか、空洞の平行性が
良好かどうか、および素子を小型化できるかどうかであ
る。(C) Problem to be Solved by the Invention An important point in an element that joins a light-receiving element and a translucent substrate and performs wavelength selection by using Fabry-Perot interference generated in a microcavity formed between the two substrates is , Whether the cavity spacing can be controlled by an appropriate driving force, whether the cavities have good parallelism, and whether the element can be miniaturized.
しかし、上記従来の素子においては、以下の理由によ
り、スペーサ間隔をある程度以上に狭めることができ
ず、素子を有効受光面積に対して著しく大きなものとせ
ざるを得なかった。However, in the above-mentioned conventional device, the spacer interval cannot be narrowed to a certain extent or more for the following reason, and the device has to be remarkably large with respect to the effective light receiving area.
第１の理由は空洞の平行度を確保するためである。空洞
間隔を変化させるために、一方の基板をスペーサに囲ま
れた領域内でそのまま湾曲させている。この場合、受光
領域上において空洞の良好な平行度を保つためには基板
の湾曲曲率を小さく設定して基板の平面度を確保しなけ
ればならないので、スペーサ間隔を広く取る必要があ
り、必然的に素子が有効受光面積に対してかなり大きな
ものとなる。The first reason is to ensure the parallelism of the cavity. In order to change the cavity spacing, one of the substrates is curved as it is in the region surrounded by the spacers. In this case, in order to maintain good parallelism of the cavity on the light receiving region, it is necessary to set the curvature of the substrate small to ensure the flatness of the substrate. In addition, the element becomes considerably large with respect to the effective light receiving area.
第２の理由は空間間隔の制御に要する力を小さくするた
めである。特に静電駆動法（後述）を用いて空洞間隔を
制御する場合には、力を増加させると電界強度が強くな
り、絶縁破壊の危険性が生じる。力を小さくするために
は他にも基板の厚さを薄くすることが考えられるが、基
板の平面度を維持するためには基板にある程度の厚さが
必要である。必要な力はスペーサ間隔の３乗に反比例し
て小さくなるので、スペーサ間隔を広く取ることによっ
て力を小さく抑えるしかない。The second reason is to reduce the force required to control the space interval. In particular, when the space between cavities is controlled by using the electrostatic drive method (described later), increasing the force increases the electric field strength, resulting in a risk of dielectric breakdown. Although it is conceivable to reduce the thickness of the substrate in order to reduce the force, the substrate needs to have a certain thickness to maintain the flatness of the substrate. Since the required force becomes smaller in inverse proportion to the cube of the spacer distance, the force must be kept small by widening the spacer distance.
（ニ）課題を解決するための手段 この発明は、一方の面に受光部を有する半導体基板と、
その半導体基板にスペーサを介して上記一方の面に対向
して接合され、それによってファブリーペロー干渉を生
じる空洞を形成しうる透光性基板と、両基板間の空洞間
隔を可変にしうる空洞間隔可変手段と備え、半導体基板
は、他方の面において、受光層形成領域とスペーサ配設
領域との間の領域に、エッチングにより形成されてなる
溝を有することを特徴とする波長選択性受光素子であ
る。(D) Means for Solving the Problems The present invention is directed to a semiconductor substrate having a light receiving portion on one surface,
A translucent substrate that is bonded to the semiconductor substrate so as to face one of the above-mentioned surfaces via a spacer, thereby forming a cavity that causes Fabry-Perot interference, and a cavity spacing variable that can vary the cavity spacing between the two substrates. And a semiconductor substrate having a groove formed by etching in a region between the light receiving layer forming region and the spacer disposing region on the other surface of the semiconductor substrate. .
すなわち、この発明は、一方の面に受光部を有する半導
体基板と、これにスペーサを介して上記一方の面に対向
して接合された透光性基板とを備えた波長選択受光素子
において、半導体基板における受光領域とスペーサ領域
間の他方の面の基板部分をエッチングして溝を形成した
ものである。That is, the present invention provides a wavelength-selective light-receiving element comprising a semiconductor substrate having a light-receiving portion on one surface and a translucent substrate bonded to the one surface so as to face the one surface via a spacer. A groove is formed by etching the substrate portion on the other surface of the substrate between the light receiving region and the spacer region.
その際、エッチングした分だけ基板部分の厚さを薄くで
きるから、基板の湾曲を容易にできる。特に、受光素子
を構成する半導体基板としてシリコンを用い、それを異
方性エッチングすることにより得られる溝の形状を良好
に制御できるとともに、再現性の向上を図ることができ
る。At that time, since the thickness of the substrate portion can be reduced by the amount of etching, the substrate can be easily bent. In particular, it is possible to satisfactorily control the shape of the groove obtained by using silicon as the semiconductor substrate that constitutes the light receiving element and anisotropically etching it, and to improve the reproducibility.
（ホ）作用 受光領域においては、基板の平面度および空洞の平行度
を確保するため基板をエッチングせずにそのまま用い、
スペーサ領域と受光領域の間の部分において基板をエッ
チングすることにより、基板の湾曲が容易となり、素子
の大幅な小型化および低電圧駆動化を図る事ができる。(E) Action In the light receiving area, the substrate is used as it is without etching in order to ensure the flatness of the substrate and the parallelism of the cavity.
By etching the substrate in the portion between the spacer region and the light receiving region, the substrate can be easily curved, and the device can be significantly downsized and driven at a low voltage.
（ヘ）実施例 以下、実施例に基づいて本発明を詳細に説明する。な
お、それによってその発明は限定されるものではない。(F) Examples Hereinafter, the present invention will be described in detail based on Examples. The invention is not limited thereby.
第１図に本発明の一実施例による波長選択性受光素子の
概略構成図を示す。素子の作製法および各構成要素につ
いて第2,3,4図にもとづいて説明する。FIG. 1 shows a schematic configuration diagram of a wavelength selective light receiving element according to an embodiment of the present invention. The manufacturing method of the device and each component will be described with reference to FIGS.
第２図（ａ）は接合直前の素子断面図である。FIG. 2 (a) is a cross-sectional view of the element immediately before joining.
第２図（ａ）において、基板10は面方位が（100）、比
抵抗率が４Ω・cm、厚さＷが300μｍのｎ型シリコン基
板である。この表面10aおよび裏面10bに熱酸化SiO2層1
3、14をそれぞれ形成し、SiO2層13をパターンニングし
てボロン拡散を行うことによりｐ型シリコン層16,17,18
をそれぞれ受光層、静電駆動・静電容量モニタ用電極
層、エッチングストップ層として形成する。ここでｐ型
シリコン層18は必ずしも必要でなく、もしこれがない場
合にはSiO2層13自体がSiエッチング時のストップ層とし
ての機能を果たす。さらに、SiO2層13上にスペーサ膜兼
静電接合陽極（2.0μｍの厚さを有するAI層）30を形成
する。そのほかに、スペーサ30に接続する電極35および
ｐ型シリコン層16,17にそれぞれ接続する電極（500Åの
厚さを有するAI層）165,175を形成する（第１図参
照）。In FIG. 2A, the substrate 10 is an n-type silicon substrate having a plane orientation of (100), a resistivity of 4 Ω · cm, and a thickness W of 300 μm. A thermally oxidized SiO 2 layer 1 is formed on the front surface 10a and the back surface 10b.
3 and 14 are respectively formed, the SiO 2 layer 13 is patterned, and boron diffusion is performed to form p-type silicon layers 16, 17, and 18
Are formed as a light-receiving layer, an electrostatic drive / capacitance monitor electrode layer, and an etching stop layer, respectively. Here, the p-type silicon layer 18 is not always necessary, and if it is not present, the SiO 2 layer 13 itself functions as a stop layer during Si etching. Further, a spacer film / electrostatic bonding anode (AI layer having a thickness of 2.0 μm) 30 is formed on the SiO 2 layer 13. In addition, electrodes 35 connected to the spacers 30 and electrodes (AI layers having a thickness of 500Å) 165 and 175 respectively connected to the p-type silicon layers 16 and 17 are formed (see FIG. 1).
基板20は厚さＥが0.5mmのガラスである。このガラスはS
iに熱膨張率が近いパイレツクスガラスとした。基板20
のシリコン基板10に対向する面20aの裏面20bにアルミニ
ウム薄膜の静電接合陽極40を形成する。一方、シリコン
基板10に対向する面20aの表面上に静電駆動・静電容量
モニタ用電極（500Åの厚さを有するAI層）27を形成す
る。この際、電極27は接合時に外周縁部27aがスペーサ3
0とわずかに重なるようになっており、接合後はシリコ
ン基板側のパッドを介して外部と接続する。The substrate 20 is glass having a thickness E of 0.5 mm. This glass is S
Pyrex glass having a coefficient of thermal expansion close to that of i was used. Board 20
An aluminum thin film electrostatic bonding anode 40 is formed on the back surface 20b of the surface 20a facing the silicon substrate 10. On the other hand, an electrostatic drive / capacitance monitoring electrode (AI layer having a thickness of 500Å) 27 is formed on the surface of the surface 20a facing the silicon substrate 10. At this time, the outer peripheral edge portion 27a of the electrode 27 is bonded to the spacer 3 at the time of joining.
It is slightly overlapped with 0, and after bonding, it is connected to the outside through the pad on the silicon substrate side.
すなわち、シリコン基板10上には受光層16から引き出さ
れた電極165と、ｐ型拡散層17から引き出された電極175
と、スペーサ30に接続する電極35のそれぞれのパッドが
配設されている［第１図参照］。That is, on the silicon substrate 10, the electrode 165 extracted from the light receiving layer 16 and the electrode 175 extracted from the p-type diffusion layer 17.
And pads of the electrodes 35 connected to the spacers 30 are provided [see FIG. 1].
接合後は、電極27とｐ−Si層17との間に空洞コンデンサ
が形成されるので、両層27および17の間に電圧を印加し
て静電引力を発生することにより空間間隔を制御し、ま
た両電極27および17間の静電容量より空間間隔ｄをモニ
タする。After bonding, a cavity capacitor is formed between the electrode 27 and the p-Si layer 17, so that a space is controlled by applying a voltage between both layers 27 and 17 to generate electrostatic attraction. Also, the space interval d is monitored by the capacitance between the electrodes 27 and 17.
なお、本実施例では電極165,175と対向する領域につい
ては静電駆動・静電容量モニタ用電極27を形成せず、該
電極27を一部切欠いた空間Ｓを設け［第７図（ａ）参
照］、これによりショートなどのトラブルを未然に防止
できる。In this embodiment, the electrostatic drive / capacitance monitoring electrode 27 is not formed in the region facing the electrodes 165 and 175, and a space S is formed by partially cutting the electrode 27 [see FIG. 7 (a)]. ], This can prevent problems such as short circuits.
Si基板10の受光領域100の表面50上およびガラス基板20
のその領域100に対向する表面51上にそれぞれ反射膜11,
21を形成する。この反射膜は、本実施例ではTiO2、SiO2
の９層交互多層膜としたが、MgF2、ZnSなどよりなる誘
電体多層膜、あるいはAg、Al、Auなどの金属膜でもよ
い。On the surface 50 of the light receiving area 100 of the Si substrate 10 and the glass substrate 20.
On the surface 51 facing the area 100 of the reflective film 11,
Form 21. This reflective film is made of TiO 2 , SiO 2 in this embodiment.
However, a dielectric multilayer film made of MgF 2 , ZnS or the like, or a metal film made of Ag, Al, Au or the like may be used.
以下、素子の作成方法について説明する。Hereinafter, a method for producing the element will be described.
（ｉ）両基板10,20を以下のようにして接合する。(I) The two substrates 10 and 20 are joined as follows.
まず、第２図（ｂ）に示すように、シリコン基板10のス
ペーサ30がガラス基板20と接するように対向させる。こ
の際、上述したように、電極27はその外周縁部27aを介
してスペーサ30と重なる。続いて、加熱雰囲気（400
℃）でスペーサ30および基板10全体を接地し、静電接合
陰極40に−300Vを10分間印加することにより、静電接合
を行う。これにより両基板10,20間にファブリーペロー
干渉を生じる空洞99が形成される。First, as shown in FIG. 2B, the spacer 30 of the silicon substrate 10 is opposed to the glass substrate 20 so as to be in contact therewith. At this time, as described above, the electrode 27 overlaps the spacer 30 via the outer peripheral edge portion 27a thereof. Then, heating atmosphere (400
The spacer 30 and the entire substrate 10 are grounded at (.degree. C.), and electrostatic bonding is performed by applying -300 V to the electrostatic bonding cathode 40 for 10 minutes. This forms a cavity 99 that causes Fabry-Perot interference between the substrates 10 and 20.
（ii）次に、Si基板10の異方性エッチングを行う。(Ii) Next, the Si substrate 10 is anisotropically etched.
すなわち、Si基板10の裏面10bにおいて、受光領域100と
スペーサ配設領域300との間の領域200に縦断面略台形状
の溝80を形成する。That is, on the back surface 10b of the Si substrate 10, the groove 80 having a substantially trapezoidal vertical cross section is formed in the region 200 between the light receiving region 100 and the spacer disposition region 300.
その準備として、Siの異方性エッチングのマスク層とし
て働くSiO2層14のパターニングを行う。スペーサ30の内
側、受光部の外側に２つの正方形を描き、これらの小さ
な正方形、大きな正方形の間で囲まれた領域のSiO2層14
を除去する。正方形の各辺は＜110＞または＜101＞方向
を向くように設定した。このパターニングの形状は正方
形に限らず、円形であってもよい。なお、この作業は接
合前に行ってもよい。もう一つの準備として、エッチン
グ液が、接合によって形成された空隙99に侵入するのを
阻止するため、接合された両基板10,20の端面にシール
材を塗るのが好ましい。As its preparation, the SiO 2 layer 14 that functions as a mask layer for Si anisotropic etching is patterned. Two squares are drawn inside the spacer 30 and outside the light receiving part, and the SiO 2 layer 14 in the area surrounded by these small squares and large squares is drawn.
To remove. Each side of the square was set to face the <110> or <101> direction. The shape of this patterning is not limited to a square and may be a circle. Note that this work may be performed before joining. As another preparation, it is preferable to apply a sealing material to the end faces of the both substrates 10 and 20 which are joined together, in order to prevent the etching solution from entering the void 99 formed by the joining.
続いて、上記のように接合された両基板10,20をSi異方
性エッチング液に浸す。だたし、異方性エッチングとは
結晶方位によってエッチングレートが少なくとも２倍以
上違うものを指し、一般には（100）面などでエッチン
グ速度が早く、（111）面でのエッチング速度が遅いた
め、一旦形成された（111）面がエッチングストップ層1
8として働き、エッチング時間依存性のほとんどない高
精度のエッチング形状が得られるとという特徴がある。Subsequently, the both substrates 10 and 20 bonded as described above are immersed in a Si anisotropic etching solution. However, anisotropic etching means that the etching rate differs by at least two times depending on the crystal orientation. Generally, the etching rate is fast in the (100) plane and slow in the (111) plane. The (111) surface once formed is the etching stop layer 1
The feature is that it acts as 8, and a highly accurate etching shape with little dependence on etching time can be obtained.
ここで異方性エッチング液としてEPW（エチレンジアミ
ン・ピロカテコール水溶液）を用い、115℃で300分エッ
チングを行った。Here, EPW (ethylenediamine / pyrocatechol aqueous solution) was used as an anisotropic etching solution, and etching was performed at 115 ° C. for 300 minutes.
なお、異方性エッチング液としてはKOH水溶液、ヒドラ
ジン水溶液などを用いてもよい。エッチング液としてKO
Hを用いる場合にはSiO2を若干エッチングするので、SiO
2膜14をやや厚く形成することが望ましい。また、エッ
チング形状の精度をさほど要求しない場合などにはSiの
等方性エッチング液（ふっ酸・硝酸混合液など）を用い
てもよい。Note that a KOH aqueous solution, a hydrazine aqueous solution, or the like may be used as the anisotropic etching solution. KO as etching liquid
When H is used, SiO 2 is slightly etched, so
2 It is desirable to form the film 14 to be slightly thick. Further, when the precision of the etching shape is not required so much, an isotropic etching solution of Si (hydrofluoric acid / nitric acid mixed solution, etc.) may be used.
なお、本実施例では接合後にSiエッチングを行う方法を
示したが、その順序を逆にして、Siエッチング後に接合
を行ってもよい。Although the method of performing the Si etching after the bonding is described in this embodiment, the order may be reversed and the bonding may be performed after the Si etching.
（iii）次に電極を形成する。(Iii) Next, an electrode is formed.
すなわち、Siエッチング終了後、Si基板10の裏面10bのS
iO2層14を除去し、その面に電極19を形成する。なお、S
iO2層14を除去しなくても電極19はSiのエッチング部分
でSi基板10と電気的コンタクトを取ることができるの
で、この除去は必須条件ではない。That is, after completion of Si etching, S on the back surface 10b of the Si substrate 10 is
The iO 2 layer 14 is removed, and an electrode 19 is formed on the surface. Note that S
This removal is not essential because the electrode 19 can make electrical contact with the Si substrate 10 at the etched portion of Si without removing the iO 2 layer 14.
（iv）さらに、基板をダイシングする。(Iv) Further, the substrate is diced.
すなわち、ガラス基板20をダイシングして基板20を分割
し、各素子を取り出す。ダイシング時の素子は、第３図
（ａ）に示すように、素子分割に必要なダイシング溝81
に加え、電極165,175,35を外部に接続するためのパッド
部分91の上のガラスを除去するためのダイシング溝82も
形成する。That is, the glass substrate 20 is diced to divide the substrate 20, and each element is taken out. As shown in FIG. 3 (a), the element during dicing has a dicing groove 81 necessary for dividing the element.
In addition, a dicing groove 82 for removing the glass on the pad portion 91 for connecting the electrodes 165, 175, 35 to the outside is also formed.
第３図（ｂ）は、ダイシング時に空隙に水が侵入するの
を防ぐために、両面から空隙を突き抜けないようにダイ
ング溝61および62を入れた場合を示す。溝62は、Si基板
10の異方性エッチング時に同時に形成することもでき
る。FIG. 3 (b) shows a case where dicing grooves 61 and 62 are provided so as not to penetrate the voids from both sides in order to prevent water from entering the voids during dicing. Groove 62 is a Si substrate
It can also be formed simultaneously with the anisotropic etching of 10.
（ｖ）素子をステムに装着する。(V) Attach the element to the stem.
素子を装着するステム83を第４図に示す。このステムは
素子装着部の中央が図のようにえぐられており、Si基板
10の受光部16下部の領域とは接触しないようになってい
る。スペーサ30下部のSi基板10のみが導電性ペーストに
よってステム83に装着される。A stem 83 for mounting the element is shown in FIG. The center of the element mounting part of this stem is scooped out as shown in the figure.
It does not come into contact with the region below the light-receiving section 16 of 10. Only the Si substrate 10 under the spacer 30 is attached to the stem 83 by the conductive paste.
なお、ステムの形状を、受光部16下部のSi基板10がステ
ム83に装着され、スペーサ30直下のSi基板がステム83に
接触しないものであってもよい。The shape of the stem may be such that the Si substrate 10 below the light receiving portion 16 is attached to the stem 83 and the Si substrate directly below the spacer 30 does not contact the stem 83.
この後、電極35,165,175のパッドとステム上のリード線
パッド84をワイヤ86でボンディングし、透明ウインドウ
85をステム83に取れ付けハーメチックシールを行う。After this, the pads of the electrodes 35, 165, 175 and the lead wire pad 84 on the stem are bonded with a wire 86 to form a transparent window.
Attach 85 to stem 83 and make a hermetic seal.
この際、パッケージ内は真空とするか、乾燥空気、窒素
あるいは放電抑止ガス（SF6あるいはC2F6など）を封入
する。ハーメチックシールは信頼性の確保および湿度の
影響を除去する目的で行うことが望ましいが、必須条件
ではない。なお、素子のガラス基板20自体がパッケージ
のウインドウ85の代わりをするよう素子をステム83の上
部に接着してもよく、これにより界面での反射が減少す
る利点がある。この場合、パッドに配線してからステム
に接着するなどの工夫が必要である。At this time, the inside of the package should be vacuumed or filled with dry air, nitrogen or discharge suppressing gas (SF 6 or C 2 F 6 etc.). Hermetic sealing is preferably done for the purpose of ensuring reliability and removing the influence of humidity, but it is not an essential condition. It should be noted that the element may be bonded to the upper part of the stem 83 so that the glass substrate 20 itself of the element replaces the window 85 of the package, which has the advantage of reducing reflection at the interface. In this case, it is necessary to devise such as wiring to the pad and then adhering to the stem.
このようにして素子が作成される。In this way, the device is produced.
本実施例は、さらに以下のように変形することが可能で
ある。The present embodiment can be further modified as follows.
まず、基板10には拡散型（PN型）シリコンフォトダイオ
ードを用いたが、低容量拡散型、PNN+型、PIN型、アバ
ランシェ型のものなどを用いてもよい。シリコン基板は
ｎ型でなくｐ型であっても通常の不純物濃度であれば特
に問題なく異方性エッチングを行うことができる。更に
は、基板10がGe,SiC,GaAs, CaAlAs,GaAsP,GaP,InP,InAsP,InGaAlPなどの半導体であ
ってもよい。First, the diffusion type (PN type) silicon photodiode is used for the substrate 10, but a low capacitance diffusion type, a PNN + type, a PIN type, an avalanche type or the like may be used. Even if the silicon substrate is p-type instead of n-type, anisotropic etching can be performed without any particular problem as long as the impurity concentration is normal. Further, the substrate 10 may be a semiconductor such as Ge, SiC, GaAs, CaAlAs, GaAsP, GaP, InP, InAsP, InGaAlP.
次に、基板20は透光性がある材料ならばガラス以外のも
の、例えば、石英、サファイアあるいは透光性アルミ
ナ、LiNbO3、LiTaO3、Mgo、アクリル、ポリカーボネー
トなどであってもよい。ただし、静電接合のできない材
料の場合には、接合方法を変更する必要がある。Next, the substrate 20 may be made of any material other than glass as long as it has a light-transmitting property, such as quartz, sapphire or light-transmitting alumina, LiNbO 3 , LiTaO 3 , Mgo, acrylic, polycarbonate, or the like. However, in the case of materials that cannot be electrostatically joined, it is necessary to change the joining method.
また、基板20の外側には反射防止膜をコートすることが
望ましい。これには反射膜11・21と同じような誘電体多
層膜を用いることができる。Further, it is desirable to coat the outside of the substrate 20 with an antireflection film. For this, a dielectric multilayer film similar to the reflective films 11 and 21 can be used.
さらに、接合方法は静電接合に限定されない。例えば、
低融点ガラスあるいは鉛・すず・はんだ等の低融点金属
を基板10もしくは基板20上に塗布し、融点以上に加熱し
て接合してもよい。Furthermore, the joining method is not limited to electrostatic joining. For example,
A low melting point glass or a low melting point metal such as lead, tin or solder may be applied onto the substrate 10 or the substrate 20 and heated to a temperature equal to or higher than the melting point for bonding.
駆動方法は静電駆動法に限定されない。例えば素子外部
に圧電素子またはコイルなどを設置し、そこで発生した
力を基板10の受光部分に加え、空隙間隔を可変にするよ
うにしてもよい。また静電容量モニタは必ずしも行わな
くてもよい。静電駆動および静電容量モニタを両方とも
行わない場合には、電極27およびｐ型拡散層17は不要と
なる。The driving method is not limited to the electrostatic driving method. For example, a piezoelectric element or a coil may be installed outside the element, and the force generated there may be applied to the light receiving portion of the substrate 10 to make the gap spacing variable. Further, the capacitance monitor does not necessarily have to be performed. If neither electrostatic drive nor capacitance monitoring is performed, the electrode 27 and the p-type diffusion layer 17 are unnecessary.
一方、電極27およびｐ型拡散層17の間の放電を抑止する
ために、これらの少なくとも一方にSiO2などの絶縁膜を
形成してもよい。ただし絶縁膜を電極17上に形成する場
合には、スペーサ30と電極27との電気的導通を保つため
に、スペーサ30と重なる領域には絶縁膜を形成しないよ
うにしなければならない。On the other hand, in order to suppress discharge between the electrode 27 and the p-type diffusion layer 17, an insulating film such as SiO 2 may be formed on at least one of them. However, when the insulating film is formed on the electrode 17, the insulating film must be formed in a region overlapping with the spacer 30 in order to maintain the electrical continuity between the spacer 30 and the electrode 27.
そして、本実施例では電極27およびｐ型拡散層17は静電
駆動と静電容量モニタの異なる働きを同時に行っている
が、これを分けてもよい。例えば電極27は共通とし、ｐ
型拡散層は静電駆動と静電容量モニタについて別個に設
けてもよい。Further, in this embodiment, the electrode 27 and the p-type diffusion layer 17 simultaneously perform different functions of electrostatic drive and electrostatic capacity monitor, but they may be separated. For example, the electrode 27 is common and p
The mold diffusion layer may be provided separately for the electrostatic drive and the capacitance monitor.
また、電極35,165,175から取り出すパッドを基板10上で
なく、基板20上に設けてもよい。ただしそのためにはス
ペーサ30を素子化後互いに電気的に独立となる幾つかの
領域に分け、それぞれが基板10上の各電気要素（拡散層
16,17など）からの電気を基板20に中継する必要があ
る。Further, the pads taken out from the electrodes 35, 165 and 175 may be provided not on the substrate 10 but on the substrate 20. However, for that purpose, the spacer 30 is divided into several regions which are electrically independent from each other after the device is formed, and each of them is provided with each electric element (diffusion layer) on the substrate 10.
Electricity from (16, 17 etc.) needs to be relayed to the substrate 20.
使用波長領域については後程述べるが、700〜1600nmの
近赤外光（光通信の短波長領域）以外であってもよい。
受光素子基板にSi、透光性基板にガラスを用いる場合に
は、0.3〜１μｍの領域の光は単にスペーサ間隔および
反射膜厚を若干変更するだけで波長識別・検出可能であ
る。また、1.0〜1.6μｍの波長領域（光通信の長波長領
域）で使用するためには、基板10の材料をGeあるいはIn
・Ga・Al・As・Ｐのうちの幾つかを組み合わせた化合物
半導体（前述）などにする必要がある。さらに0.3μｍ
以下の紫外領域、1.6μｍ以上の遠赤外領域において
も、その波長で感度を有する受光素子基板およびその基
板のエッチング方法、その波長で透光性を有する基板の
組み合わせを工夫することにより、本発明を適用するこ
とができる。以下、本素子の動作について述べる。The wavelength range to be used will be described later, but it may be other than near infrared light of 700 to 1600 nm (a short wavelength region of optical communication).
When Si is used for the light receiving element substrate and glass is used for the translucent substrate, the light in the region of 0.3 to 1 μm can be identified and detected by simply changing the spacer interval and the reflection film thickness. Further, in order to use in the wavelength region of 1.0 to 1.6 μm (long wavelength region of optical communication), the material of the substrate 10 is Ge or In.
-It is necessary to use compound semiconductors (described above) that combine some of Ga, Al, As, and P. 0.3 μm
Even in the following ultraviolet region and far-infrared region of 1.6 μm or more, by devising a light-receiving element substrate having sensitivity at that wavelength, an etching method for the substrate, and a combination of substrates having translucency at the wavelength, The invention can be applied. The operation of this device will be described below.
対向する反射膜11および21のそれぞれの領域50および51
において、反射膜間隔ｄに応じてファブリーペロー干渉
が生じ、その結果この領域の透過スペクトル及び反射ス
ぺクトルに顕著な波長依存性が生じる。とくに反射膜の
反射率が高い場合には、分光透過率が極大となる波長の
近傍の波長の光のみを透過し、その他の波長の光をほと
んど遮断する。この分光透過率の極大波長（選択波長と
呼ぶ）は複数存在し、 として与えられる。ここにｍは共鳴次数（ｍ＝1,2,3,4
…）、ｎは反射膜間の媒質の屈折率、φは反射膜での反
射の際に生ずる位相シフトである。φの波長依存性を無
視すると、λｍはｄに比例するものとみなせる。本素子
ではこの原理を利用して、干渉領域の空洞間隔を可変と
することにより波長選択受光素子を実現している。Regions 50 and 51 of the opposing reflective films 11 and 21, respectively.
, Fabry-Perot interference occurs depending on the reflection film spacing d, and as a result, a remarkable wavelength dependence occurs in the transmission spectrum and the reflection spectrum in this region. In particular, when the reflectance of the reflection film is high, only the light having a wavelength in the vicinity of the wavelength where the spectral transmittance becomes maximum is transmitted, and the light having other wavelengths is almost blocked. There are multiple maximum wavelengths (called selective wavelengths) of this spectral transmittance, Given as. Where m is the resonance order (m = 1,2,3,4
,), N is the refractive index of the medium between the reflection films, and φ is the phase shift generated at the time of reflection on the reflection film. Ignoring the wavelength dependence of φ, λm can be regarded as being proportional to d. This device utilizes this principle to realize a wavelength selective light receiving device by making the cavity spacing in the interference region variable.
そして、波長分解能を良くするためには、反射膜の反射
率を上げ、共鳴次数ｍを高く設定すればよい。本実施例
では反射膜としてTiO2膜とSiO2膜を交互に９層積層した
ものを用いており、その反射率は使用波長領域全体で95
％以上、位相シフトφは約180°である。共鳴次数は使
用波長領域に唯一の透過ピークが存在するという条件か
ら決定される。使用波長範囲を、例えば、光通信の短波
長領域である780〜890nmと設定すると、共鳴次数ｍが４
以下であれば、この選択波長が上記近赤外領域内のどの
波長となるように走査されても、それより高次もしくは
低次の選択波長はこの領域には含まれない。従って、本
実施例においてはｍ＝４とした。また媒質として真空を
用いているためｎ＝１である。以上の条件下で選択波長
λ４を780〜890nmの範囲において走査するためには、計
算上ｄをおよそ1560〜1780nmの範囲で可変とすればよ
い。Then, in order to improve the wavelength resolution, the reflectance of the reflective film may be increased and the resonance order m may be set high. In this embodiment, as the reflection film, a film in which nine layers of TiO 2 film and SiO 2 film are alternately laminated is used, and the reflectance thereof is 95 in the entire wavelength range used.
% Or more, the phase shift φ is about 180 °. The resonance order is determined by the condition that there is only one transmission peak in the used wavelength region. When the used wavelength range is set to 780 to 890 nm, which is the short wavelength region of optical communication, the resonance order m is 4
As long as the selected wavelength is scanned so that the selected wavelength is in the near-infrared region, the selected wavelengths higher or lower than the selected wavelength are not included in this region. Therefore, m = 4 in this embodiment. Further, since a vacuum is used as the medium, n = 1. In order to scan the selected wavelength λ 4 in the range of 780 to 890 nm under the above conditions, it is necessary to make d variable in the range of approximately 1560 to 1780 nm in calculation.
なお、一般にはより広い波長領域で用いようとするとｍ
を小さく設定する必要がある。例えば可視光領域（400
〜750nm）で使用可能な素子はｍ＝１とする必要があ
り、また反射膜もこの広い波長全域でほぼ一定の反射膜
を有するAg,Alなどにする必要がある。In general, when trying to use in a wider wavelength range, m
Needs to be set small. For example, visible light region (400
˜750 nm), it is necessary to set m = 1 for the element, and the reflection film also needs to be Ag, Al or the like having a substantially constant reflection film over this wide wavelength range.
本実施例においては、空洞間隔を可変とするための手段
として、電極17・27間に電圧を加えたときに生じる静電
引力を利用している。この方法は、干渉フィルター外部
に圧電素子等の駆動素子を必要としないため、素子全体
の構造を単純・小型化でき、また素子の耐振動性が向上
する。In this embodiment, electrostatic attraction generated when a voltage is applied between the electrodes 17 and 27 is used as a means for varying the cavity spacing. Since this method does not require a driving element such as a piezoelectric element outside the interference filter, the structure of the entire element can be simplified and downsized, and the vibration resistance of the element is improved.
電極17・27間に生じる静電力は次式で与えられる。The electrostatic force generated between the electrodes 17 and 27 is given by the following equation.
ここに、Ｖは電極間に印加した電圧、ε０は真空の誘電
率、εｒは電極間媒質の比誘電率である。なお、ｄはＦ
の増加に伴い減少するため、Ｖとｄの関係はかなり複雑
なものとなる。 Here, V is the voltage applied between the electrodes, ε 0 is the dielectric constant of the vacuum, and ε r is the relative dielectric constant of the interelectrode medium. In addition, d is F
The relationship between V and d becomes quite complicated because it decreases with increasing.
さらに本実施例では、選択波長を所定値に保つために、
電極17・27間の静電容量Ｃを検出している。この静電容
量Ｃは、反射膜間隔ｄに反比例するため、Ｃとλ４とは
一対一の関係にある。従って、静電容量Ｃが一定となる
ように静電駆動電圧を制御することにより、選択波長を
安定化することができる。Further, in this embodiment, in order to keep the selected wavelength at a predetermined value,
The capacitance C between the electrodes 17 and 27 is detected. Since the electrostatic capacitance C is inversely proportional to the distance d between the reflecting films, C and λ 4 have a one-to-one relationship. Therefore, the selected wavelength can be stabilized by controlling the electrostatic drive voltage so that the electrostatic capacitance C becomes constant.
本実施例では、電極17・27を静電容量モニタと静電駆動
の両方に用いるために、静電容量検出信号に静電駆動信
号の最高周波数よりも高い周波数の交流を用い、カップ
リングコンデンサを用いて２信号を分離している。な
お、これらの信号を電極上で混合しなくてもよいよう
に、素子内部に静電容量検出専用電極と静電駆動専用電
極を独立に配設してもよい。In this embodiment, since the electrodes 17 and 27 are used for both the electrostatic capacity monitor and the electrostatic drive, an alternating current having a frequency higher than the maximum frequency of the electrostatic drive signal is used for the electrostatic capacity detection signal, and the coupling capacitor is used. Are used to separate the two signals. It should be noted that the capacitance detection dedicated electrode and the electrostatic drive dedicated electrode may be independently provided inside the element so that these signals do not have to be mixed on the electrodes.
次に、本実施例の波長選択受光素子の特性について述べ
る。Next, the characteristics of the wavelength selective light receiving element of this embodiment will be described.
本素子の最大の特徴は、基板10としてエッチングが容易
なシリコンを用い、それを精密に異方性エッチング加工
することによって、反射面の面精度を保ちながら、空隙
間隔の制御性を飛躍的に高めたことである。The greatest feature of this element is that silicon that is easy to etch is used as the substrate 10, and by precisely anisotropically etching it, the controllability of the air gap is dramatically improved while maintaining the surface accuracy of the reflective surface. It was raised.
第５図に本実施例に係る素子の駆動時の断面図を示す。FIG. 5 shows a cross-sectional view of the device according to the present embodiment during driving.
第５図において、基板10の中でエッチングによって薄く
なった部分77が大きく変形し、それによって中央の受光
部分100の全体にわたり空隙間隔が一様に小さくなって
いることが分かる。本素子は、第７図に示すように、Ｌ
が縦3mm・横Ｒが4mmの矩形状であり、シリコン基板10が
エッチングされ最も薄くなっている部分77は、厚さＨが
１μｍ・長さＦが160μｍ、幅の内周がＫ＝2mm角の正方
形であり、静電駆動導電極の面積は3.75mm2である。ま
た、溝80の開口長Ｊは600μｍである。In FIG. 5, it can be seen that the portion 77 of the substrate 10 that has been thinned by etching is largely deformed, and as a result, the gap spacing is uniformly reduced over the entire central light receiving portion 100. As shown in FIG.
Has a rectangular shape of 3 mm in length and 4 mm in width R, and the thinnest part 77 where the silicon substrate 10 is etched has a thickness H of 1 μm, a length F of 160 μm, and an inner circumference of K = 2 mm square. The area of the electrostatically driven conductive electrode is 3.75 mm 2 . The opening length J of the groove 80 is 600 μm.
このときの駆動電圧と空隙間隔の関係を第６図に示す。
16〜20Vの駆動電圧で必要な全波長領域を走査できるこ
とがわかる。なお電圧印加前の電極間隔を1.78μｍにす
れば、さらに低電圧駆動化を図ることができるが、電極
間隔Ｍの作製ばらつきを考慮して設計値を２μｍとし
た。なお、第７図において、Ｍのみ「μｍ」の単位を有
し、残りのものは「mm」の単位を有する。FIG. 6 shows the relationship between the driving voltage and the gap distance at this time.
It can be seen that the required wavelength range can be scanned with a drive voltage of 16 to 20V. If the electrode spacing before applying the voltage is set to 1.78 μm, further lower voltage driving can be achieved, but the design value was set to 2 μm in consideration of manufacturing variations in the electrode spacing M. In FIG. 7, only M has a unit of “μm”, and the rest has a unit of “mm”.
比較のため、特にエッチング加工しないシリコン基板11
0を用いた波長可変受光素子の駆動時の断面図を第８図
に示す。この素子の大きさは、縦ｌが2mm・横ｒが20mm
と細長くなっており、スペーサ130は横方向の両端部の
み形成されている。スペーサ間内径ｎは16mmである。駆
動時に基板110のスペーサ130に挟まれた部分400の全体
が湾曲し、そのため空隙401の間隔が一定と見なせる領
域は中央部401aのごく一部となる。更に、基板厚が厚
く、湾曲に大きな力が必要なため、スペーサ間隔を広く
することによって静電駆動印加電圧が著しく大きくなる
ことを避けている。しかしそのために、素子全体が大型
化し、パッケージ（好ましくはハーメチックシール）の
コストが非常に大きくなる。駆動電圧と空隙間隔の関係
を第６図に示す。このとき、印加電圧が70〜88Vの範囲
で走査ができる。ただし電圧が高いため多くの素子で放
電による絶縁破壊が生じている。For comparison, a silicon substrate 11 not particularly etched
FIG. 8 shows a sectional view of the variable wavelength light receiving element using 0 when driven. The size of this element is 2mm in length 1 and 20mm in width r.
The spacer 130 is formed only at both ends in the horizontal direction. The inner diameter n between the spacers is 16 mm. When driven, the entire portion 400 of the substrate 110 sandwiched by the spacers 130 is curved, so that the region where the spacing of the voids 401 can be regarded as constant is only a part of the central portion 401a. Further, since the substrate is thick and a large force is required for bending, it is avoided that the electrostatic drive applied voltage is significantly increased by widening the spacer interval. However, as a result, the entire device becomes large and the cost of the package (preferably hermetic seal) becomes very large. The relationship between the driving voltage and the gap distance is shown in FIG. At this time, scanning can be performed in the applied voltage range of 70 to 88V. However, since the voltage is high, dielectric breakdown occurs due to discharge in many devices.
（ト）発明の効果 以上詳説した如く、本発明に係る波長選択性受光素子に
よれば、素子の大幅な小型化が達成されるため低コスト
化が図れ、また静電駆動電圧の低電圧化が図れるので絶
縁破壊問題を解決できる。(G) Effect of the Invention As described in detail above, according to the wavelength-selective light receiving element of the present invention, the size of the element is significantly reduced, so that the cost can be reduced and the electrostatic drive voltage can be reduced. Therefore, the dielectric breakdown problem can be solved.
従って、本発明は今後、小型・ポータブル分光計・色識
別器、カラー時分割検出型イメージセンサ、光通信用波
長可変受光素子等に広く用いられることが期待される。Therefore, it is expected that the present invention will be widely used in the future in a compact / portable spectrometer / color discriminator, a color time division detection type image sensor, a wavelength tunable light receiving element for optical communication and the like.
第１図は本発明の一実施例に係る波長選択性受光性素子
を示す要部分解構成図、第２図（ａ），（ｂ）はそれぞ
れ上記実施例に係る波長選択性受光素子の製作中におけ
る構成説明図、第３図（ａ），（ｂ）はそれぞれ上記実
施例に係る波長選択性受光素子のダイシング方法を説明
するための要部構成説明図、第４図は上記実施例に係る
波長選択性受光素子をステムに装着した状況を示す構成
説明図、第５図は上記実施例に係る波長選択性受光素子
の駆動時における構成説明図、第６図は上記実施例に係
る波長選択性受光素子およびその比較例の印加電圧−選
択波長特性を示す特性図、第７図（ａ）（ｂ）はそれぞ
れ上記実施例における素子の要部説明図、第８図（ａ）
（ｂ）（ｃ）はそれぞれ従来例を示す要部構成説明図で
ある。 10……シリコン基板、20……ガラス基板、11・21……反
射膜、16……受光層（ｐ型拡散層）、17……静電駆動・
静電容量モニタ用導電層（ｐ型拡散層）、18……異方性
エッチングストップ層（ｐ型拡散層）、27……静電駆動
・静電容量モニタ用電極、30……スペーサ、40……静電
接合用電極。FIG. 1 is an exploded view showing the essential parts of a wavelength-selective light-receiving element according to an embodiment of the present invention, and FIGS. 2 (a) and 2 (b) are each a fabrication of the wavelength-selective light-receiving element according to the above embodiment. 3A and 3B are explanatory views of the essential parts for explaining the dicing method of the wavelength selective photodetector according to the above embodiment, and FIG. 4 is the above embodiment. FIG. 5 is a structural explanatory view showing a situation in which the wavelength selective light receiving element is attached to a stem, FIG. 5 is a structural explanatory view at the time of driving the wavelength selective light receiving element according to the above embodiment, and FIG. 6 is a wavelength according to the above embodiment. FIG. 7A and FIG. 7B are characteristic diagrams showing the applied voltage-selected wavelength characteristics of the selective light-receiving element and its comparative example, respectively, and FIG. 8A and FIG.
(B) (c) is a principal part configuration explanatory view which shows a prior art example, respectively. 10 …… Silicon substrate, 20 …… Glass substrate, 11 ・ 21 …… Reflective film, 16 …… Light receiving layer (p-type diffusion layer), 17 …… Electrostatic drive
Capacitance monitor conductive layer (p-type diffusion layer), 18 ... Anisotropic etching stop layer (p-type diffusion layer), 27 ... Electrostatic drive / capacitance monitoring electrode, 30 ... Spacer, 40 ...... Electrostatic bonding electrode.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 橋爪 信郎 大阪府大阪市阿倍野区長池町22番22号 シ ャープ株式会社内 (56)参考文献 特開 昭62−257032（ＪＰ，Ａ) ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Nobuo Hashizume, 22-22 Nagaike-cho, Abeno-ku, Osaka-shi, Osaka Within Sharp Co., Ltd. (56) References JP 62-257032 (JP, A)
Claims (1)
その半導体基板にスペーサを介して上記一方の面に対向
して接合され、それによってファブリーペロー干渉を生
じる空洞を形成しうる透光性基板と、両基板間の空洞間
隔を可変にしうる空洞間隔可変手段とを備え、半導体基
板は、他方の面において、受光層形成領域とスペーサ配
設領域との間の領域に、エッチングにより形成されてな
る溝を有することを特徴とする波長選択性受光素子。1. A semiconductor substrate having a light receiving portion on one surface,
A translucent substrate that is bonded to the semiconductor substrate so as to face one of the above-mentioned surfaces via a spacer, thereby forming a cavity that causes Fabry-Perot interference, and a cavity spacing variable that can vary the cavity spacing between the two substrates. And a groove formed by etching in the region between the light receiving layer forming region and the spacer disposing region on the other surface of the semiconductor substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1079800A JPH0766982B2 (en) | 1989-03-29 | 1989-03-29 | Wavelength selective light receiving element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1079800A JPH0766982B2 (en) | 1989-03-29 | 1989-03-29 | Wavelength selective light receiving element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02257676A JPH02257676A (en) | 1990-10-18 |
| JPH0766982B2 true JPH0766982B2 (en) | 1995-07-19 |
Family
ID=13700295
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1079800A Expired - Fee Related JPH0766982B2 (en) | 1989-03-29 | 1989-03-29 | Wavelength selective light receiving element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0766982B2 (en) |
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