JPH0758790A - Clock regeneration circuit - Google Patents

Abstract

PURPOSE:To accurately maintain the lock state of a PLL circuit for the bit data of analog signals even when the same codes continue by providing a timer means and a synthesis means for inserting interpolation timing pulses in the gaps of timing pulses and inputting them in a PLL means. CONSTITUTION:In this circuit provided with a thresholding means 11 for thresholding the amplitude of demodulated analog signals, an edge detection means 12 for detecting the edge of binary output and forming the timing pulses and the PLL means 15 for synchronizing oscillation signals based on the timing pulse output, the timer means 14 and the synthesis means 13 are provided. In the information, when the same codes continue in digital data, the interpolation timing pulses are outputted from the timer means 14 and the synthesis means 13 inserts the pulses in the gaps of the timing pulses of the edge detection means 12. Thus, influence by the same consecutive codes of the digital data on timing signals for locking the PLL means 15 is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock recovery circuit for forming a clock pulse synchronized with digital data from an analog signal obtained by modulating digital data.

[0002]

2. Description of the Related Art Various digital communications using amplitude modulation, frequency modulation, phase modulation, amplitude-phase modulation, etc., such as wire multiplex data communication, wireless data communication, and commercial data broadcasting have been put into practical use. In digital data communication,
Error detection and code correction using redundant bits can be used, and high quality communication is possible with low power consumption and a simple transceiver.

A receiver used for digital data communication generally includes a binarizing circuit for binarizing the amplitude of an analog signal (baseband signal) formed through a detection operation, and a binarizing circuit. It has an edge detection circuit that detects the edge of the binarized output and forms a timing pulse, and a PLL circuit that synchronizes the oscillation signal based on the timing pulse output of the edge detection circuit. Then, for example, the amplitude of the analog signal is read at the phase position fixed to the clock pulse generated by the PLL circuit, and the original digital data is reproduced.

In this case, it is preferable that the reading phase position fixedly set to the clock pulse corresponds to the center of the bit data included in the analog signal. This is because at the end of the bit data, the distinction of 0-1 becomes questionable through the modulation operation on the transmission side of the digital data, the transmission of the communication line or space, the demodulation operation of the previous stage on the reception side, and the like. .

In any case, the clock pulse generated by the PLL circuit must have the same frequency (modulation speed) as the digital data and the phase must be fixed with respect to the bit data of the digital data.

FIG. 4 is an explanatory diagram of a conventional clock recovery circuit. In the figure, (a) shows a circuit configuration and (b) shows a signal time chart. Here, a clock pulse is formed from an analog signal obtained by detecting the FM modulation signal, the analog signal is read at a phase position fixed to the clock pulse, and original digital data is reproduced.

In FIGS. 4A and 4B, the detection circuit 40
Removes the component of the carrier signal from the input FM modulated signal to form an analog signal 41A of digital data in which bit data is serially connected. Limiter 4
1 limits the amplitude of the analog signal 41A to HL
The binary signal 41D of the level is converted.

The clock recovery circuit 43 receives a clock pulse 45T from the binary signal 41D output from the limiter 41.
To form. The sampling circuit 46 causes the analog signal 41A at the falling timing of the clock pulse 45T.
The original digital data is restored by reading the amplitude of 1 and identifying 1 and 0.

The edge extraction circuit 4 of the clock recovery circuit 43
2 generates a timing pulse 42P each time the edge of the binary signal 41D of the limiter 41 is detected. The PLL circuit 45 uses the timing pulse 42 of the edge extraction circuit 42.
Clock pulse 45 that oscillates and outputs itself according to P
Timing pulse 42P by changing the frequency and phase of T
Form a clock pulse 45T which rises every time is input.

[0010]

In the conventional clock generation circuit, the digital data included in the analog signal has 11 bits.
If the same signs as ..., 00, etc. continue, the frequency lock in the PLL circuit becomes suspicious and there is a possibility that digital data may be erroneously read from the analog signal.

For example, in the clock generating circuit 43 of FIG. 4, when the same sign continues in the digital data, the output 41D of the limiter 41 is continuous in H (L), and in the meanwhile, in the edge extracting circuit 42, The edge cannot be detected, and the output of the edge detection output 42P disappears.

As a result, when the frequency lock in the PLL circuit 45 is released, the frequency (wavelength) or phase of the clock pulse 45T is deviated, and the sampling circuit 46 can misread digital data from the analog signal 41A. Sex comes out.

That is, in the PLL circuit 45, the frequency and phase of the clock pulse 45T that oscillates and outputs itself are changed, and the timing pulse 42 of the edge extraction circuit 42 is changed.
Since these are matched with P, timing pulse 4
When the period of 2P apparently changes due to the same sign, the frequency and phase of the clock pulse 45T are changed toward the changed apparent frequency and phase.

Here, normally, the continuation of the same code is randomly generated, and does not continue long enough to noticeably change the frequency and phase of the clock pulse 45T output from the PLL circuit 45. However, the output 41D HH of FIG. 4 (b)
If the parts that become LL (the rising and falling edges are lost) are accidentally combined and continue, the clock pulse 45T is disturbed and the output 4 of the limiter 41 is changed.
For each bit data in 1D, the PLL circuit 45
There is a high possibility that the lock state of the clock pulse 45T will be released.

When the locked state of the PLL circuit 45 starts to be released, the data read error rate in the sampling circuit 46 increases, and when the locked state of the PLL circuit 45 is completely released, the identification operation in the sampling circuit 46 is completely unsuccessful. It will be possible.

An object of the present invention is to provide a clock recovery circuit in which the locked state of the PLL circuit with respect to the bit data of the analog signal is accurately maintained even if the same sign continues.

[0017]

FIG. 1 is an explanatory diagram of a data reproducing circuit of an embodiment described later. The clock recovery circuit according to claim 1 will be described with reference to the reference numerals of the components of FIG. However, in the embodiment, the clock recovery circuit according to claim 1 is shown in a limited mode, and the clock recovery circuit according to claim 1 is not limited to the mode shown in FIG.

In FIG. 1, a clock recovery circuit according to a first aspect of the present invention comprises a binarizing means 11 for binarizing the amplitude of an analog signal obtained by detecting a digitally modulated signal and demodulating the binarized signal. In a clock regeneration circuit, which includes an edge detection unit 12 that detects an edge of a converted output and forms a timing pulse, and a PLL unit 15 that synchronizes an oscillation signal based on the timing pulse output of the edge detection unit 12. The timer means 14 is reset for each timing pulse to start time measurement and forms an interpolation timing pulse at a fixed timing, and the interpolation timing pulse is inserted in the interval of the timing pulse to the PLL means 15. Synthetic means 1 for inputting
3 is provided.

According to a second aspect of the present invention, there is provided the clock recovery circuit of the first aspect.
In the clock regeneration circuit of, the timer means starts time measurement at the falling edge of the timing pulse,
It is a means for forming an interpolation timing pulse after a lapse of the bit length of the digital data.

[0020]

In FIG. 1, in the clock recovery circuit according to the first aspect, when the same sign continues in the digital data, the timer means 14 outputs the interpolation timing pulse, and the synthesizing means 13 determines the interval of the timing pulse of the edge detecting means 12. , This interpolation timing pulse is inserted. As a result, the influence of the continuous same sign of the digital data on the timing signal for locking the PLL means 15 is reduced.

The timer means 14 may generate the interpolation timing pulse only once after the time corresponding to one bit of the digital data, however, as long as the same sign continues, at every time corresponding to one bit of the digital data. Alternatively, the interpolation timing pulse may be generated any number of times.

In the clock recovery circuit of the second aspect, since the time measurement is started at the falling edge of the timing pulse, the interpolation timing pulse is output at a timing slightly delayed from the time when the next timing pulse should be generated. Therefore, even if the rising edge of the next timing pulse is slightly delayed, there is no concern that the interpolation timing pulse is formed prior to the next timing pulse. That is, there is no concern that both the interpolation timing pulse and the timing pulse will be input to the PLL means at the rising edge (falling edge) of the same bit data.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is an explanatory view of a data reproducing circuit of the embodiment, FIG. 2 is an explanatory view of an FM multiplex broadcasting receiver of the embodiment, and FIG. 3 is a signal time chart. In Figure 2, (a) is the device configuration, (b)
Indicates a band configuration. Here, the data reproduction circuit of FIG.
The time chart of FIG. 3, which constitutes a part of the FM multiplex broadcast receiver of FIG. 2, shows the input / output timing states of the respective parts of FIG.

The FM multiplex broadcasting is MSK (Minimumm
This is a digital data broadcast that is FM-modulated by the Shift Keying method, and character information is used by using an empty part that is not used for FM radio broadcast in one channel band (100 kHz) of the commercial FM radio broadcast in the 76 to 90 MHz band. Or broadcast simple image information.

In FM multiplex broadcasting, road information, traffic jam information, latest accident information, regulation information, etc.
Continuously broadcast weather information, parking lot availability information, required transit time for specific sections, warnings, warnings, etc., regardless of the broadcasting program. Therefore, the driver can access the required type of information at the desired location at any time without waiting for the traffic information inserted at intervals of the broadcast program or missing the traffic information at the required location. .

In FIG. 2 (a), the FM multiplex broadcast receiver of the embodiment separates the MSK signal from the FM multiplex broadcast, reproduces and stores the data, and stores the necessary information according to the search operation by the operator. The FM multiplex broadcast receiving unit 20 for outputting and the interface unit 28 for displaying the information stored in the FM multiplex broadcast receiving unit 20 are configured.

The tuner 21A extracts one channel of 100 kHz band from the radio wave received through the antenna A, and further has a center frequency f _C = 76 kHz as a center.
Select the band from 0 to 92 kHz and select MSK (Minimumm Shi
The signal component y (t) that has been FM-modulated by the ft Keying method is output. The tuning system 21B is a tuner 21
Controls channel selection in A.

The FM multiplex broadcast receiver 20 has two memories 2
6, 27 are provided. One memory 26 accumulates and updates the received data. The other memory 27 stores the reception frequency of a specific channel capable of receiving the FM multiplex broadcast.

The detection circuit 22 removes the carrier signal component from the MSK signal to form a detection signal. The data reproducing circuit 23 detects the detection signal and reproduces the original digital data.

The error correction data combination section 24 performs predetermined error detection and code correction processing on the digital data reproduced by the data reproduction circuit 23. Data processing unit 25
Stores the reproduced information in the memory 26 by classifying the reproduced information. When the operator selects the necessary information through the operation unit of the interface unit 28, the data processing unit 25 reads out the necessary data from the memory 26 according to the selection command,
It is sent to the interface unit 28.

In FIG. 2 (b), the L + R component of 0 to 15 kHz, the pilot signal of 19 kHz, and the range of 23 to 53 kHz are included in the 100 kHz band allocated to one channel of FM broadcasting.
The L-R component of Hz is included. Then, in the channel on which the FM multiplex broadcast is multiplexed, MSK (Minimumm) is set in the band of 60 to 92 kHz centered on the center frequency f _C = 76 kHz.
FM multiplex broadcast components FM-modulated by the Shift Keying method are arranged.

In the FM multiplex broadcast component, 1 is the mark frequency (f _C + Δf: 80 kHz) and 0 is the space frequency (f _C
-Δf: 72 kHz) to form digital data, which is transmitted at a data rate of 16 kbps.

In FIG. 1, the data reproducing circuit 23 of FIG.
Is a limiter 11 that binarizes the amplitude of an analog signal (baseband signal) formed through a detection operation, an edge extraction circuit 12 that generates a timing pulse each time an edge of a binary output of the limiter 11 is detected, PL that synchronizes its own oscillation signal with the cycle and phase of the input pulse signal
The L circuit 15 and the like are provided. Then, the sampling circuit 16
Then, the amplitude of the analog signal is read at a specific phase position fixed to the clock pulse generated by the PLL circuit 15 and restored to serial digital data.

By the way, when the digital data such as 1100 has the same sign, the rising edge (falling edge) of the bit data break is lost from the output of the limiter 11, and the edge extraction circuit 12 forms a necessary timing pulse. Can not.

Therefore, the timer circuit 14 is reset every time the edge extraction circuit 12 outputs a timing pulse, starts time measurement, and when the bit time is reached, generates an interpolation timing pulse replacing the timing pulse.

The synthesizing circuit 13 sets the timer circuit 1 at the interval of the timing pulse output from the edge extracting circuit 12.
The interpolation timing pulse output from 4 is inserted, and even if the same sign continues in the digital data, the PLL circuit 15 is made to input a pulse for each break of bit data. The combining circuit 13 can be configured by, for example, an OR circuit using TTL elements.

The PLL circuit 15 includes a phase comparator 15A for detecting the phase difference between the input pulse and the output clock, a low pass filter 15B, and a VCO 15C for changing the oscillation frequency according to the input voltage. The PLL circuit 15 integrates the output clock and the input pulse and removes a high frequency component, thereby extracting the frequency difference and the phase difference between the output clock and the input pulse, and outputting in the direction of reducing the frequency difference and the phase difference. Change the frequency and phase of the clock.

In the timer circuit 14, the high frequency clock generated by the clock pulse generator 14 is applied to the counter 1
Counted by 4B. The timing pulse generator 14C is set with a set value of the count number corresponding to 1 bit time of digital data.
When the count output of B matches the set value, the timing pulse generator 14C generates an interpolation timing pulse.

The counter 14B is reset by the timing pulse output from the edge extraction circuit 12,
At the trailing edge (falling edge) of the timing pulse, the clock output of the clock pulse generator 14 starts counting.
The clock pulse generator 14 is composed of a stable oscillator using a crystal oscillator.

In the embodiment of FIG. 1, the counter 14B is reset by the output pulse of the edge extraction circuit 12, and the interpolation timing pulse is generated only once. However, the counter 14B is reset by the OR output of the output of the edge extraction circuit 12 and the output of the timing pulse generator 14C (for example, the output of the synthesizing circuit 13), and as long as the same sign continues, every bit length The interpolation timing pulse may be continuously generated.

In any case, as compared with the clock generation circuit of the conventional example of FIG. 4, even if the same sign continues in the digital data, the result is that the intervals of the pulses input to the PLL circuit 15 become uniform, and the input pulse The PLL circuit 15 that adjusts the oscillation output toward the cycle and the phase can continue to output a stable clock even if the same sign continues.

In FIG. 3, the detection circuit 22 of FIG. 2 forms an analog signal 11A and inputs it to the limiter 11 of FIG. The limiter 11 is an H-L level binary signal 11D.
Are formed and input to the sampling circuit 16 and the edge extraction circuit 12.

In the edge extraction circuit 12, the binary signal 11D
The timing pulse 12P is generated at the rising and falling edges of. The edge extraction circuit 12 is composed of a differentiating circuit, and adjusts the time constant of the falling edge of the differential pulse so that the length of the timing pulse 12P is slightly shorter than the bit length of the digital data, for example, 1 of the bit length. % (6 μsec).

Therefore, the counter 14B of the timer circuit 14 of FIG. 1 starts counting with a delay of this time from the rising (falling) of the binary signal 11D, and with a delay of this time from the next break of the digital data. Interpolation timing pulse 14P is generated.

Therefore, when the same sign is not continuous, the rising (falling) of the binary signal 11D occurs prior to the interpolation timing pulse 14P, and the counter 14B
Is reset without outputting the interpolation timing pulse 14P, and it is not necessary to continuously output two pulses to the output 13P of the synthesizing circuit 13 in response to one rising (falling) of the binary signal 11D.

In the present embodiment, the length of the timing pulse 12P is set to about 10% of the bit length of digital data in order to apply it to a radio communication application in which phase distortion easily occurs in the demodulated signal. Therefore, the length of the timing pulse 12P may be compressed to about 5% of the bit length of the digital data for the purpose of transmitting the signal through the fixed line.

With the output 13P of the synthesizing circuit 13 thus formed, the PLL circuit 15 has the clock pulse 15 whose oscillation frequency and phase are synchronized with the output 13P.
Form T. Then, the sampling circuit 16 reads the amplitude of the analog signal 41A at the falling timing of the clock pulse 15T, identifies 1 and 0, and restores the original digital data.

[0048]

According to the clock recovery circuit of claim 1,
Even if the same code continues in the digital data or a regular code array with a long cycle is accidentally generated, pulses at a constant interval are continuously supplied to the PLL means, and a stable frequency and phase are obtained from the PLL means. The clock pulse continues to be output at.

Therefore, P for the phase of digital data
The locked state of the LL means is kept constant and does not come off. As a result, the identification position of the digital data in the analog signal is fixed and the data reading error due to the deviation of the identification position is prevented. Further, the locked state of the PLL means will not be released and the data cannot be identified.

According to the clock generating circuit of the second aspect, even if the rising edge (falling edge) of the output of the binarizing means is slightly delayed, it is not necessary to generate two timing pulses at one rising edge (falling edge). . Therefore, it is possible to prevent a situation in which two timing pulses corresponding to one rising (falling) destabilize the locked state of the PLL means.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a data reproducing circuit according to an embodiment.

FIG. 2 is an explanatory diagram of an FM multiplex broadcast receiver according to an embodiment.

FIG. 3 is a signal time chart.

FIG. 4 is an explanatory diagram of a conventional clock recovery circuit.

[Explanation of symbols]

 11 Limiter 12 Edge Extraction Circuit 13 Synthesis Circuit 14 Timer Circuit 15 PLL Circuit 16 Sampling Circuit 14A Clock Pulse Generator 14B Counter 14C Timing Pulse Generator

Claims (2)

[Claims] 1. A binarizing means (11) for binarizing the amplitude of a demodulated analog signal by detecting a digitally modulated signal, and an edge of a binarized output of the binarizing means (11). An edge detecting means (12) for detecting and forming a timing pulse; a PLL means (15) for synchronizing an oscillation signal based on a timing pulse output of the edge detecting means (12);
In the clock regeneration circuit having: a timer means (14) which is reset for each timing pulse to start time measurement and forms an interpolation timing pulse at a timing of a fixed time; and the interpolation timing pulse at an interval of the timing pulse. A clock regenerator circuit comprising: a synthesizing means (13) which is inserted and input to the PLL means (15). 2. The clock recovery circuit according to claim 1,
The clock regenerating circuit is characterized in that the timer means is a means for starting time measurement at the falling edge of the timing pulse and forming an interpolation timing pulse after a lapse of a time substantially equal to the bit length of the digital data.