JP3354609B2 - RDS detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[Industrial applications] ARI as a traffic information system
The present invention relates to an FM radio receiver capable of demodulating an RDS (Radio Data System) signal transmitted via (Autofahrer Rundfunk Information) broadcast, and more specifically to an RDS lock detection signal detection circuit used for demodulation of an RDS signal. .

[0002]

2. Description of the Related Art Conventionally, ARI broadcasting has been known as a traffic information system for reducing traffic congestion and the like.
In this ARI broadcasting system, an FM radio station that broadcasts traffic information can be identified by constantly adding a subcarrier of 57 kHz to the radio wave. Further, the start and end of the traffic information and the target area can be distinguished by the DK and BK signals obtained by amplitude-modulating the subcarrier at a specific frequency.

[0003] Also known is an FM multiplexed data broadcast (RDS), which is a broadcast system for adding a 57 kHz subcarrier to FM radio waves and multiplexing digital data for channel selection and the like. The data multiplexed in this RDS broadcast is
Various messages mainly composed of 104 bits and mainly for a channel selection function are standardized.
The transmission rate of RDS data is 1.1875.
A two-phase PSK (Phase Shift Keying) modulation is performed on the kHz clock. Further, the sub-carrier (57 kHz) is subjected to carrier-suppressed amplitude modulation using the two-phase PSK signal, and the double-sideband (DSB) signal is multiplexed with the audio signal and transmitted. Here, the subcarrier of the RDS data is set to have the same phase or quadrature as the third harmonic of the pilot signal (19 kHz) indicating the stereo broadcast. In a broadcast requiring compatibility with an ARI signal, the RDS modulation signal and the ARI signal are set to have the same frequency, are always set to a quadrature phase, and are simultaneously transmitted.

FIG. 2 shows an RDS modulation signal and an AR signal in an FM signal.
FIG. 3 shows a spectrum when multiplexed with the I signal.
1 shows a schematic block diagram of a basic configuration of an FM multiplex data broadcast receiver.

[0005] As shown in FIG. 2, the RDS modulation signal is 57 kHz.
It is distributed at a low level near the z subcarrier, and does not affect the voice band. In the FM multiplex data broadcasting receiver, as shown in FIG. 3, for the FM multiplex broadcasting received by the antenna 101, a desired station is selected by the front end 102, an IF (intermediate frequency) amplifier 103, and an FM detector (DET). ) 104 and a multiplexer (MPX) demodulation circuit 105, when the audio signal is a stereo broadcast, the audio signal is separated into L (left) and R (right) channel audio signals and output. The output signal from the IF amplifier is also supplied to the controller 110 via the level detection circuit 113. When the signal level has not reached a certain value, the level detection circuit 113 outputs an SD (Signal Detect) signal. Further, the detection output of the FM detector 104 is supplied to the filter 106, and the RDS modulation signal of the subcarrier of 57 kHz is separated. A clock of the separated RDS modulation signal is reproduced by the RDS decode / clock regenerator 107, and the RDS data is demodulated. Further, the output signal of the RDS decode clock regenerator 107 is output to the group / block synchronization / error detector 108 and the error correction circuit 109.
The code information is supplied to the controller 110 via the controller 110, and the code information is analyzed and stored in the memory 111 such as a RAM. At this time, based on a channel selection command from the operation unit 112, the controller 110 performs a channel selection operation on the front end 102. The RDS data is reproduced by the FM multiplex data broadcast receiver having the above configuration.

FIG. 4 is a waveform chart for explaining the principle of extracting the RDS clock signal. Two-phase PSK signal (FIG. 4B) included in the RDS modulation signal (FIG. 4A)
Indicates the periodicity of the RDS clock signal (arrow in FIG. 4C)
Are hidden, and by extracting this periodicity, RD
The S clock signal can be reproduced.

For this reason, the time when the two-phase PSK signal is inverted is first identified (FIG. 4 (c)), and then the RD signal is synchronized with the window signal (FIG. 4 (d)) synchronized with the RDS clock signal.
The periodicity of the S clock signal is extracted (FIG. 4E), and an RDS clock signal is reproduced from this signal (FIG. 4E).
(F)).

FIG. 5 is a block diagram showing a configuration of a conventional RDS detection circuit. This conventional RDS detection circuit includes a clock recovery unit 2, a PLL circuit 3, and an RDS lock detection unit 4. Here, the PLL circuit 3 includes a multiplier 3a, a sequential loop filter 3b, and a variable frequency divider (VCO) 3c.

Hereinafter, a specific operation will be described. The clock reproducing unit 2 converts the two-phase PSK signal (FIG. 4B) input from the input terminal 1 into an RDS clock signal (FIG. 4F).
Is extracted. At this time, the PLL circuit 3 outputs the window signal (FIG. 4D) and the R signal included in the two-phase PSK signal.
The periodicity (FIG. 4C) of the DS clock signal is always synchronized. The multiplier 3a compares the phase of the reference clock signal supplied from the variable frequency divider (VCO) 3c with the phase of the RDS clock signal recovered by the clock recovery unit 2. The output of the multiplier 3a is supplied to a variable frequency divider (VCO) 3c via a sequential loop filter 3b, and controls the variable frequency divider (VCO) 3c. When the phase difference between the reference clock signal and the reproduced RDS clock signal disappears, the PLL circuit 3 enters the locked state. At this time, a signal orthogonal to the reference clock signal input to the multiplier 3a is defined as a window signal (FIG. 4D), and the window signal is a signal obtained by extracting a change point of the two-phase PSK signal (FIG. 4).
(C)), a stable RDS clock signal (FIG. 4 (e)) can be extracted.

[0010] The RDS lock detecting section 4 receives the RDS clock signal reproduced by the clock reproducing section 2 and a variable frequency divider (V
CO) 3c to detect a phase difference from a reference clock signal supplied thereto, determine whether or not the PLL circuit 3 is locked, and output an RDS lock detection signal when locked.

FIG. 6 shows a state (a) where the RDS clock signal can be extracted and a state (b) where the RDS clock signal cannot be extracted. In the initial state immediately after the input of the two-phase PSK signal, the phase relationship between the change point of the two-phase PSK signal and the window signal is such that the clock signal can be extracted (FIG. 6).
There are two cases: (a)) and a state where it cannot be taken out (FIG. 6 (b)).

A state where a clock signal can be extracted (FIG. 6)
In the case of (a)), the clock recovery unit 2 in FIG. 5 reproduces the RDS clock signal from the signal extracted from the window signal, and after the PLL circuit 3 locks, the RDS lock detection unit 4 outputs the RDS lock detection signal. Output, AND gate 7
To supply. At this time, the RDS lock detection signal is at a low level.

However, when the clock signal cannot be taken out (FIG. 6B), the clock reproducing unit 2 in FIG. 5 reproduces the RDS clock signal because the signal extracted by the window signal is discontinuous. Can not do. Therefore, the clock recovery unit 2 detects a discontinuous point of the extracted signal and supplies an initial synchronization identification signal to the AND gate 7. The AND gate 7 supplies the initial synchronization identification signal to the variable frequency divider (VCO) 3c of the PLL circuit 3 when the RDS lock detection signal is at a high level, that is, when the lock of the PLL circuit 3 is not established. At this time, the PLL circuit 3 switches to the initial synchronization mode, and this initial synchronization mode continues until the state where the clock signal cannot be extracted (FIG. 6B) switches to the state where the clock signal can be extracted (FIG. 6A). . Clock signal can be extracted (Fig. 6
When switching to (a)), the discontinuous point of the extracted signal disappears, and the clock reproducing unit 2 of FIG. 5 reproduces the RDS clock signal from the signal extracted from the window signal,
After the PLL circuit 3 locks, the RDS lock detection unit 4 outputs an RDS lock detection signal.

As described above, in any of the above cases, the RDS lock detection section 4 finally outputs the RDS lock detection signal.

[0015]

However, in the case of the above-described conventional RDS detection circuit, the initial synchronization identification signal is directly transmitted to the PL.
It is supplied to the L circuit 3 for control. Therefore, the RDS modulation signal is disturbed by external noise such as multipath noise,
When the periodicity of the RDS clock signal in the two-phase PSK signal is disrupted, an initial synchronization identification signal is supplied to the PLL circuit 3,
The PLL circuit 3 switches to the initial synchronization mode. When the mode is switched to the initial synchronization mode, the lock of the PLL circuit 3 is forcibly released, and the RDS lock detection signal becomes unstable. In particular, when external noise extends for a long time, it is difficult to obtain a stable RDS lock detection signal.

An object of the present invention is to stabilize RDS lock detection and control a PLL circuit by a stable RDS data signal.

[0017]

In order to achieve this object,
An RDS lock detecting circuit according to the present invention reproduces and outputs an RDS clock signal for demodulating RDS data from an RDS signal, and outputs an initial synchronization identification signal when the RDS clock signal cannot be reproduced. ) And a PLL for detecting a phase difference between a reference clock signal supplied from a built-in reference clock generating means (3c) and the RDS clock signal, and synchronizing the operation timing of the radio receiver with the RDS clock signal.
A circuit (3) for detecting the phase difference between the RDS clock signal and the reference clock signal, thereby obtaining the PLL.
An RDS lock detection unit (4) for determining whether or not the circuit is locked to the phase of the RDS clock signal, and outputting an RDS lock detection signal when locked. A latch circuit (6) for latching the RDS lock detection signal;
Control means (7) for controlling the PLL circuit (3) by using the logical product of the DS lock detection signal and the initial synchronization identification signal is provided.

[0018]

According to the configuration of the present invention, a latch circuit (6) for latching the RDS lock detection signal is provided between the PLL circuit (3) and the RDS lock detection section (4). The PLL circuit (3) can be controlled by using the logical product of the low-level RDS lock detection signal and the initial synchronization identification signal. Clock regeneration unit (2)
, The initial synchronization identification signal is supplied to the AND gate (7), but since the RDS lock detection signal is at a low level, the initial synchronization identification signal is not supplied to the PLL circuit (3) and the PLL circuit (3) Can stabilize the RDS lock detection signal without frequently switching to the initial synchronization mode.

[0019]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. FIG. 1 shows a block diagram of a configuration of an RDS detection circuit according to the present invention. In the drawing, the same components as those in FIG. 5 are denoted by the same reference numerals.

In the configuration of the RDS detection circuit according to the present invention,
A latch circuit 6 is provided between the RDS lock detection unit 4 and the AND gate 7 of the conventional RDS detection circuit shown in FIG. Hereinafter, the operation of the RDS detection circuit according to the present invention will be described.

The operation of the RDS detection circuit according to the present invention
The operation from the initial state immediately after the input of the phase PSK signal to the lock of the PLL circuit is the same as the operation of the conventional RDS detection circuit, and the description thereof will be omitted. When the clock signal is reproduced from the clock reproducing unit 2 and the lock of the PLL circuit 3 is established, R output from the lock detecting unit 4 is output.
The DS lock detection signal becomes low level, and the low level RDS lock detection signal is latched by the latch circuit 6. Thus, after the PLL circuit 3 is locked, the latched low-level RDS lock detection signal is supplied to one input terminal of the AND gate. Therefore, even after the lock is established, the RDS modulation signal is disturbed by external noise, the periodicity of the RDS clock signal in the two-phase PSK signal is disturbed, and the initial synchronization identification signal is supplied to the other input terminal of the AND gate 7. Supplied to the input terminal of
Since the DS lock detection signal is at a low level, the initial synchronization identification signal is not supplied to the PLL circuit 3.

For resetting the latch circuit 6, the SD signal supplied from the SD input terminal 8 when reception becomes impossible is used.

[0023]

According to the configuration of the present invention, the conventional RD
By providing the latch circuit in the S detection device, the PLL circuit 3 can be controlled by multiplying the latched low-level RDS lock detection signal by the initial synchronization identification signal. As a result, even if the RDS modulation is disturbed by external noise after the PLL circuit 3 is locked, the periodicity of the RDS clock signal is disturbed, and even if the initial synchronization identification signal is supplied from the clock recovery unit 2 to the AND gate 7, the RDS lock detection is performed. Since the signal is at a low level, the initial synchronization identification signal is not supplied to the PLL circuit 3. Therefore, the PLL
Circuit 3 does not switch to the initial synchronization mode,
The lock detection signal can be stabilized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an RDS detection circuit according to the present invention.

FIG. 2 is a diagram showing a spectrum when an RDS modulation signal and an ARI signal are multiplexed on an FM signal.

FIG. 3 is a schematic block diagram illustrating a basic configuration of an FM multiplex data broadcast receiver.

FIG. 4 is a waveform diagram for explaining the principle of extracting an RDS clock signal.

FIG. 5 is a block diagram illustrating a configuration of a conventional RDS detection circuit.

FIG. 6A is a signal waveform diagram in a state where an RDS clock signal can be extracted, and FIG. 6B is a signal waveform diagram in a state where an RDS clock signal cannot be extracted.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... 2 phase PSK signal input terminal 2 ... Clock reproduction part 3 ... PLL circuit 3a ... Multiplier 3b ... Loop filter 3c ... Variable frequency divider (VCO) 4 ... RDS lock detection part 5 ... RDS lock detection signal output terminal 6 ... Latch circuit 7 AND gate 8 SD signal input terminal

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-63-87040 (JP, A) JP-A-4-280510 (JP, A) JP-A-64-44644 (JP, A) JP-A-2- 104041 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04L 27/22 H03L 7/08 H03D 3/00

Claims (1)

(57) [Claims] 1. Clock recovery for reproducing and outputting an RDS clock signal for demodulating RDS data from a radio data system (RDS) signal, and outputting an initial synchronization identification signal when the RDS clock signal cannot be reproduced. (2), a phase difference between a reference clock signal supplied from a built-in reference clock generating means (3c) and the RDS clock signal, and the operation timing of the radio receiver is determined by the RDS clock signal.
PLL circuit for synchronizing with DS clock signal (3)
Detecting the phase difference between the RDS clock signal and the reference clock signal,
An RDS lock detection section (4) for determining whether or not the phase of the S clock signal is locked, and outputting an RDS lock detection signal when locked.
In the detection circuit, a latch circuit (6) for latching the RDS lock detection signal, and a control means for controlling the PLL circuit (3) using a logical product of the latched RDS lock detection signal and an initial synchronization identification signal ( 7) An RDS lock detection circuit comprising: