JPH0754615B2 - Error correction control device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction control device in a digital signal recording / reproducing device for converting an analog signal into a digital signal and recording / reproducing it on a recording medium.

2. Description of the Related Art In recent years, in the audio field, development of a digital audio tape recorder (hereinafter referred to as DAT) for converting an analog signal into a digital signal and recording it on a magnetic tape has been advanced.

The signal processing technique used in the above-described conventional DAT will be described below with reference to the drawings. FIG. 5 shows an example of a signal format recorded on a magnetic tape which is currently proposed.

In FIG. 5, 1 is an 11-bit synchronizing signal, 2 is an address code, and in the present example, it is composed of 2 bits, and each block sequentially advances from 00 → 01 → 10 → 11 → 00 → ……. 3 is a 3-bit flag indicating recording conditions,
Reference numeral 4 is the first audio data, and in this example, digital audio data composed of 16 bits is composed of 96 bits for 6 words. Reference numeral 5 is a parity code for correcting an error in audio data, 6 is second audio data having the same configuration as the first audio data 4, and 7 is an error detection code for detecting the presence or absence of an error in a block. In this example, a cyclic code (hereinafter referred to as CRC) is used to detect an error for 261 bits from the address code 2 to the second audio data 6 excluding the sync signal 1. A block is composed of a total of 288 bits shown by the above-mentioned symbols 1 to 7.

FIG. 6 is a block diagram showing a reproducing circuit for processing a digital signal sequence (hereinafter simply referred to as “reproduced data”) reproduced from the magnetic tape with the configuration shown in FIG. Sixth
In the figure, 8 is an input terminal for inputting reproduction data, and 9
Is a demodulation circuit for returning the modulated reproduction data to the original NRZ signal, 10 is a synchronization detection circuit for detecting the synchronization signal from the reproduction signal (in this example, demodulation is performed because a pattern that does not conform to the modulation law is used as the synchronization signal. (The sync signal is extracted from the previous playback data), 11 is a CRC check circuit for detecting an error in the playback data excluding the sync signal in the block using CRC, 12 is the time until error detection by CRC, That is, a delay circuit for delaying the reproduced data for one block, 13 is an address code extracting circuit for extracting an address code from the reproduced block, and 14 is a wow, flutter, jitter, etc. of the reproduced data generated in the tape running system. TBC memory for eliminating the influence of the sync signal, 15 is the sync signal detected by the sync detection circuit 10, the address code output from the address code extraction circuit 13, and the CRC check. A write address generation circuit for generating reproduced data to the TBC memory 14 and a write address of the error flag by the error flag output from the clock circuit 11, 16 is from the TBC memory 14 based on the clock from the crystal. A read address generation circuit for generating a read address of the reproduced data and the error flag, 17 is an error correction circuit for performing a predetermined error correction based on the reproduced data and the error flag read from the TBC memory 14, 18 Is TBC memory 14
It is a capstan servo circuit for driving the capstan 19 that controls the running speed of the magnetic tape 20 according to the difference between the write address and the read address.

The operation of the reproducing circuit configured as described above will be described below.

First, the reproduction data reproduced from the magnetic tape 20 is input to the input terminal 8, demodulated into an NRZ signal by the demodulation circuit 9, and the synchronization signal is detected by the synchronization detection circuit 10. Further, the demodulated reproduction data is inspected by the CRC check circuit 11 for the presence of an error. In this case, as is clear from the block configuration of FIG. 5, in order to determine the presence or absence of an error in the block and confirm the reliability of the address code, all 277 bits except the sync signal in the block are checked. Needs to be read into the CRC check circuit 13. In order to perform this time adjustment, the delay circuit 12 delays the reproduction data for one block. The address code extraction circuit separates and extracts only the address code from the demodulated reproduced data for one block. However, as described above, the reliability of the address code extracted here is not known until after the CRC check.

The write address generator 15 generates a write address to the TBC memory 14 corresponding to the reproduction data in the block based on the sync signal separated and extracted by the sync detection circuit 10, and the address extracted by the address code extraction circuit 13. The write block address to the TBC memory 14 is generated by the code and the error flag which is the check output of the CRC check circuit 11. That is, for the address code determined to be correct by the CRC check, that value is output as it is as the write block address to the TBC memory 14, and if the address code is determined to be unreliable by the CRC check, the address code Focusing on continuity, the TBC memory 14 is incremented by sequentially incrementing the correct address code value of the previous block.
It is configured to be used as a write block address to. Playback data and CRC passed through the delay circuit 12
The error flag which is the error detection output of the check circuit 11 is written in the TBC memory 14 according to the write address specified by the write address generation circuit 15. In this example, the TBC memory 14 has a memory area of 4 blocks corresponding to the address code "0" to "3" represented by 2 bits, and the reproduced data and the error flag written are usually about 2 blocks. After the lapse of time, the read address generation circuit 16 reads the crystal according to the read address of the crystal precision, thereby removing the influence of wah, flack, jitter, and the like. The reproduction data read from the TBC memory 14 is output after being subjected to a predetermined correction operation by the error correction circuit 17. On the other hand, in the capstan servo circuit, the traveling speed of the magnetic tape 20 is controlled by the capstan 19 so that the phase relationship between the write address and the read address supplied to the TBC memory 14 is always constant mainly by the respective block address information. To control.

The writing and reading of data in the TBC memory 14 will be described in detail below with reference to FIG. In FIG. 7, A indicates the block address of the write address, B indicates the CRC check result of the block including the respective address codes, ◯ indicates that it is correct, and X indicates that it is suspicious. Further, C represents a block address of the read addresses of the TBC memory 14.
In section 1 in FIG. 7, an error is detected in the block “2” of the write block addresses to the TBC memory 14, and therefore the address code extracted from this block is determined to be unreliable and the write address The generation circuit 15 generates an address code "2" following the correct address code "1" of the previous block as the address code of this block, and writes the reproduced data in the block area "2" of the TBC memory 14. In FIG. 7, the block address obtained by incrementing the write block address A based on the correct address code value, not the original address code, is shown in parentheses such as “(2)”. . On the other hand, the read block address C is read from the write block address A after a time difference of about 2 blocks. Since the write block address A is actually generated separately from the data reproduced from the magnetic tape, it contains wow, flutter, and jitter components, and the time difference between the two block addresses always expands and contracts accordingly. However, the phase relationship is controlled by the capstan servo circuit 18 so as to be almost guaranteed as described above.

Next, the error correction method will be briefly described. FIG. 8 is an example of an array of parity codes recorded on the tape. In digital recording, in order to efficiently correct the reproduced data error due to dropout etc. that occurs on the magnetic tape, a data sequence for error correction composed of multiple data and error correction code, so-called parity sequence, is separated on the tape. A method called interleaving is used. In FIG. 8, six predetermined data words 1-6
, One parity word 1 is generated to form one parity sequence, and they are arranged in blocks spaced by a distance of 8 blocks. Data word 1 with block having address code "0" (indicated by x in Fig. 8)
Paying attention to, a predetermined data word 2 included in the same address code “0” 8 blocks apart, and a predetermined data word 3 included in the address code “0” 8 blocks apart, ... It constitutes series 1. Similarly, as shown in FIG. 8, a parity sequence 2 consisting of the circled words, a parity sequence 3 consisting of the triangles ... I am configuring. If the parity word is a simple parity code as the error correction code, it is possible to correct any one-word error that constitutes the parity sequence by combining with the error flag by the CRC check.

Next, the relationship between the address code and the error correction capability will be described. An example is a case where an error due to dropout or the like that occurs on the magnetic tape continuously occurs over 10 blocks. When errors continuously occur for a long period of time, accurate capstan servo control cannot be performed, and thus the tape running speed during that period may be slower or faster than usual. In FIG. 9, I indicates that the tape running speed in the error section is slow and II is fast, and when writing the reproduction data to the TBC memory, the address code extracted from the reproduction data is not used, but simply in block units. It shows a case where a write block address to the TBC memory is generated. In either case of Fig. 9 I or II, the parity sequence in the block sequence read from the TBC memory is erroneous after the error section. Therefore, not only correct correction operation cannot be performed, but erroneous correction is performed in some cases. As a result, abnormal noise is output. On the other hand, FIG. 10 shows a case where the address code extracted from the block of the reproduction data is used for writing data to the TBC memory in response to the same error occurrence. 10th
In both cases of Figure I and II, when the correct playback data is obtained again after the end of the error section, the correct data is written to the TBC memory area again, so the playback data from the TBC memory maintains the correct order. Therefore, the error correction for the error section is also correctly performed. Since it is important to always maintain the original time series of the data in order to obtain the predetermined correction capability, in this example, the address code in the reproduction signal is used to write the reproduction data to the TBC memory. There is. (For example, Japanese Unexamined Patent Publication No. 57-50307) Problems to be Solved by the Invention However, in the above-mentioned configuration, particularly in an apparatus in which a plurality of tracks are divided and digital recording is performed, reproduction data is reproduced for each track. Since it is independently affected by wah, flutter, head skew, etc., it is impossible to multiplex and share one track of the playback circuit for each track. Therefore, the playback circuit for each track alone cannot be used. I need. For example, a recently proposed DAT system using a compact cassette has a structure in which 20 channels are used to record digital audio signals for two channels, and the circuit scale is larger than the CRC code as a block error detection code. Since the Reed-Solomon code that becomes larger is used, it has the drawback that a large circuit is required to extract the address code for each track before writing to the TBC memory and to check the error. Was there.

In view of the above problems, the present invention performs an error correction capable of performing TBC processing without disturbing the order of reproduced data and maintaining error correction capability even when recording and reproducing a digital signal using a plurality of tracks. A control device is provided.

Means for Solving the Problems In order to achieve this object, the error correction control device of the present invention is
A write address generating circuit for supplying a write address of the TBC memory and the TBC memory; a read address generating circuit for supplying a read address of the TBC memory;
An error detection circuit that detects the presence or absence of an error in at least digital data and an address code of a block read from the TBC memory, and a predictive address code that sequentially and sequentially cycles from the address code value of a predetermined block for each block An address code predictor for generating
An address code comparator that compares the value of the predicted address code with the address code extracted from the block read from the TBC memory, and the discontinuity of the address code by the output of the error detection circuit and the output of the address code comparator. Address control circuit for controlling the write address generation circuit by detecting the error, and a predetermined error correction operation for the digital data read from the TBC memory by the output of the error detection circuit and the output of the address control circuit. It is composed of an error correction circuit for performing the operation.

According to the present invention, the reproduction data reproduced from the magnetic tape by the above-mentioned structure is stored in the predetermined TBC memory area by the block address which is not directly related to the address code in the reproduction data designated by the write address generating circuit of the TBC memory. The data is written, and after a predetermined time delay, it is read according to the block address designated by the read address generation circuit of the TBC memory. The reproduced data read from the TBC memory is subjected to an error check by an error detection circuit to confirm the reliability of the address code. On the other hand, the address code predictor initializes an error-free address code value at the start of data reproduction, and thereafter increments the value for each block to generate a predicted address code. The address code comparator compares the value of the predicted address code with the address code extracted from the reproduction data read from the TBC memory and detects the difference. The address discontinuity control circuit performs predetermined control on the write address generation circuit according to the error flag which is the error check result in the error detection circuit and the output of the address code comparator, and the error correction circuit performs the predetermined control. By performing a predetermined correction operation on the reproduction data read from the TBC memory according to the error flag and the output of the address discontinuity control circuit, a correct reproduction data string is always maintained and corrected by a simple circuit configuration. The ability can be secured.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an error correction control device in an embodiment of the present invention, and FIG. 2 is its waveform diagram. In FIG. 1, 21a to 21n are input terminals to which reproduced data of tracks a to n are input, 22a to 22n are demodulation circuits, and 23a to 23n are synchronization detection circuits, which are the same as those of the conventional example. Reference numeral 24 is a write address generation circuit for writing the reproduction data of each track to the TBC memory on the basis of the synchronization signals separated and extracted by the synchronization detection circuits 23a to 23n of each track, and 25 is for four blocks for each track. TBC memory having a memory area, 26 is a read address generation circuit for reading the reproduction data from the TBC memory 25 in track order, and 27 is an error for detecting the presence or absence of an error in units of blocks of the reproduction data read from the TBC memory 25. Detection circuit, 28 is TBC memory 25
An error correction circuit for performing a predetermined error correction operation on the reproduced data read from the device, 29 is a prediction obtained by initializing a predetermined correct address code value at the start of data reproduction and thereafter incrementing the value for each block. An address code predictor that generates an address code, 30 is an address code comparator that compares the value of the predicted address code with the address code separated and extracted from the reproduction data read from the TBC memory 25, and outputs the difference, 31 is a write address generation circuit 24 and an error correction circuit according to the error flag output from the address code comparator 30 and the error detection circuit 27.
This is an address discontinuity control circuit that performs predetermined control on 28. Although not shown in FIG. 1, the control regarding the capstan servo is the same as that of the conventional example.

The operation of the error correction control device configured as described above will be described below. The block structure of the reproduction signal of each track is the same as that of FIG. 5 used in the description of the conventional example, and the blocks stored at the same time on the a to n tracks used for recording and reproduction have the same address code. I shall.

The data recorded and reproduced on the tracks a to n are input to the input terminals 21a to 21n.

Since the reproduced data at the time of input is affected by wow, flutter, and skew for each track, demodulation and synchronization detection for each track are performed by the demodulation circuits 22a to 22n,
This is performed by the synchronization detection circuits 23a-23n. The write address generation circuit 24 generates a TBC memory write address for the in-block data of each track on the basis of the synchronization signal of each track, and a write block common to each track for designating a memory area for four blocks. Generate an address. (TB in Fig. 2
(C circled as a write block address) The write block address in this case does not directly correspond to the address code in the block to be written. The reproduction data is written in the designated TBC memory area in each track time division, and after a time delay of about 2 blocks, the read address supplied from the read address circuit 26 (marked with a circle as the TBC read block address in FIG. 2 is added. Read in track order. This is shown in the waveform diagram of FIG. That is, the reproduction data at the writing stage to the TBC memory 25 is input in parallel with each track, but the reproduction data can be read from the TBC memory 25 in track serial by performing time axis compression. The reproduction data read out in the track serial is judged by the error detection circuit 27 whether or not there is an error, and an error flag is output.

On the other hand, the address code predictor 29 uses TB at the start of data reproduction.
Generates a predictive address code that increments with a clock step by step by initializing only once the error-free address code extracted from the block read from the C memory 25 once, and then continuing the playback state. To do. Address code comparator 30 uses TBC memory 2
The difference between the value of the address code extracted from the block read from 5 and the value of the predicted address code is detected and output.
Further, in the address discontinuity control circuit 31, the difference between the address code output from the address code comparator 30 and the predicted address code, and the error flag from the error detection circuit 27 to the TBC memory 25 generated in the write address generation circuit 24. Of the write block address and the control of the correction operation in the error correction circuit 28 are determined.

The control method is summarized in FIG. If the error flag determines that the address code is not reliable, no control is performed. When there is no error flag and the reliability of the address code is high, the write address generation circuit 24 and the error correction circuit 28 are controlled by the comparison output of the address code comparator 30. That is, the address code detected by the address code comparator 30 and the predicted address code coincide with each other during normal data reproduction.

Consider a case where a difference is detected between the address code value of the block read from the TBC memory 25 and the predicted address code value due to a continuous error or the like. When the difference is ± 1 block, the address discontinuity control circuit 31 changes the value of the write block address generated by the write address generation circuit 24 by ± 1 (in this embodiment, the control for the write block address is limited to ± 1). However, this is because it is limited to the control within the range where the write address and the read address do not overlap in the TBC memory area having 4 blocks on each track, and this is not the case depending on the TBC memory capacity). By this control, the reproduced data string read from the TBC memory 25 can be restored to the correct time series within a few blocks. However, the reproduction data read from the TBC memory 25 until it is restored to the correct time series is incorrect data in the time series. Therefore, in the address discontinuity control circuit 31, it is irrelevant whether or not there is an error in the reproduced data until the comparison output of the address code comparator 30 returns to the coincidence state again and it is judged by the error flag that the comparison output is highly reliable. First, the error correction circuit 28 is controlled so as to perform a correction operation on the assumption that all data are erroneous.

Next, the difference between the address code and the predicted address code is ±
In the case of 2, in the present embodiment, it is judged that it is dangerous to control the write block address due to the above-mentioned TBC memory capacity, and the control is not performed. Therefore during this time TBC
Since there is a possibility that time-sequential reproduction data will be read from the memory and an error correction operation will be performed by the error correction circuit 28, an error will occur during the maximum length of the interleaved sequence affected by the address code discontinuity. The correction operation in the correction circuit 28 is prohibited, and the data with an error flag is controlled as uncorrectable and an error flag is added as it is and output, and a correct address code value is again set after the end of the correction prohibited section. The predictor 29 is initialized and the normal state is restored.

The operation of the above embodiment will be described below with reference to FIG. 4 when an error occurs continuously and a discontinuity of ± 1 block is detected in the reproduced data. It is assumed that errors continuously occur in the error section shown in FIG. 4I, during which the capstan servo is disturbed and the tape running speed becomes slower than the steady state. Outside the error section, the reproduction data is written for each track in the corresponding block area of the TBC memory 25 according to the write block address generated by the write address generating circuit 24 as shown in FIG.
Even in the error section, the write block address is generated by sequentially incrementing it. Even after returning to the normal reproduction data, the continuity of the write block address is maintained for several blocks. On the other hand, the reproduced data read from the TBC memory 25 is track-serial, and the error detection circuit 27 sequentially checks the error in the data in the blocks of each track and also the address code comparator.
At 29, the address code extracted from the block is compared with the predicted address code output from the address code predictor 29. The address code predictor 29 presets the correct address code value at the start of data reproduction and sequentially increments it thereafter.Therefore, while the normal block string is being read from the TBC memory 25, the predicted address code and the actual TBC memory are actually read. No address discontinuity is detected because the address code values extracted from the block read from 25 match unless the block has an error. Next, in FIG. 4I, when the error section ends and the block sequence is disturbed, correct reproduction data is obtained.
When read from the TBC memory 25, the address code "0" extracted from an error-free block is different from the predicted address code "1".
Detected in. Therefore, the address discontinuity control circuit 31 is configured to change the write block address generated in the write address generation circuit 24 from “” to “” and to be sequentially incremented thereafter. Therefore TBC
The block sequence of the reproduction data read from the memory 25 can be restored to a normal block sequence in two blocks after the error section ends, and the error can be corrected in the correct sequence. (Reproduced data before returning to the normal block sequence is corrected as an error by the error correction circuit 28.) In FIG. 4 II, it is assumed that the tape running speed becomes faster than the steady state in the error section. ing. In this case, since the address code value of the error-free block read from the TBC memory 25 after the end of the error section is "2", the predicted address code value is "1", so the address discontinuity control circuit The write block address is changed from “” to “” by 31. Therefore, the block sequence of the reproduction data read from the TBC memory 25 is restored to the normal block sequence in four blocks after the end of the error section.
(In this case as well, the reproduced data until returning to the correct block sequence is similarly corrected by the error correction circuit 28.) As described above, according to the present embodiment, the reproduced data read from the TBC memory 25 is The address code is separated and extracted, and the presence or absence of an error is determined by the error detection circuit 27, the address code discontinuity is determined by the address code predictor 29 and the address code comparator 30, and the write address is generated by the address discontinuity control circuit 31. In the digital signal recording / reproducing apparatus which divides the data into a plurality of tracks and records / reproduces them by controlling the write block address to the TBC memory 25 generated in the circuit 24 and the error correction circuit 28, the address code is separated for each track. It is possible to secure the continuity of the reproduced data sequence with a simple configuration without providing an extraction and error detection circuit. Yes, and therefore correct error correction is always guaranteed. In addition, a reproduction data delay circuit until error detection, which was indispensable in the conventional method of detecting the presence or absence of an error before the reproduction data is written to the TBC memory (6th
12) in the figure is no longer necessary, and demodulated data can be written directly to the TBC memory without time delay, so not only when using multiple tracks, but also in a digital signal recording and reproducing device that records and reproduces data on a single track. Can be simplified.

In this embodiment, since the reproduced data is read from the TBC memory 25 in the order of tracks, the extracted address codes and error flags are obtained as many as the number of tracks. In this case, since the blocks recorded at the same time have the same address code in each track,
The address discontinuity control output is the same for all tracks unless an error is overlooked. Therefore, the result of the error-free tracks may be used as the representative value of all tracks, but in order to further improve the reliability, the results of all tracks may be processed by majority.

Although the 2-bit address code is used in this embodiment, the reliability of discontinuity detection is improved as the number of bits is increased.

Further, in the present embodiment, the TBC memory area has four blocks, so the controllable write block address range is described as ± 1 block, but this can be expanded according to the expansion of the TBC memory area. is there. Also, once the control by the address discontinuity control circuit is performed on the TBC write block address, the phase relationship between the write block address and the read block address gradually returns to the original normal phase by the capstan servo. The normalization of the block sequence of the reproduced data before and after the continuous error section according to the embodiment can be repeated any number of times.

Although the present embodiment has been described by taking the digital signal recording / reproducing apparatus using the magnetic tape as an example, it goes without saying that the recording medium is not limited to the magnetic tape and can be applied to a wide range of digital signal recording.

Further, the error detection code is not limited to the CRC code.

As described above, the present invention has a TBC memory and a write address generation circuit that generates a write address of the TBC memory,
A read address generation circuit for generating a read address of the TBC memory, an error detection circuit for detecting the presence or absence of an error in at least an address code and digital data among the blocks read from the TBC memory, and a predetermined block An address code predictor that generates a predictive address code that sequentially and sequentially cycles from the address code value, and an address that compares the value of the predictive address code with the address code extracted from the block read from the TBC memory. A code comparator, an address discontinuity control circuit for detecting the discontinuity of the address code by the output of the error detection circuit and the output of the address code comparator and controlling the write address generation circuit, and the error detection circuit Of the T and the output of the address discontinuity control circuit. By including an error correction circuit that performs a predetermined error correction operation on the digital data read from the BC memory, a TB is provided in a digital recording / reproducing apparatus that performs recording / reproduction using a plurality of tracks.
It is not necessary to provide address code extraction and error detection circuits for each track independently before writing the reproduction data to the C memory, and it is not necessary to provide a reproduction data delay circuit necessary for error detection, and one circuit can extract the address codes of all tracks. And error detection to keep the time series of the reproduced data correct,
Therefore, it is possible to sufficiently guarantee the original error correction capability. Therefore, it is possible to obtain great effects in reliability, downsizing, cost reduction, etc. of the device.

[Brief description of drawings]

FIG. 1 is a block diagram of a reproducing circuit of a digital signal recording / reproducing apparatus in an embodiment of the present invention, FIG. 2 is a waveform diagram in the block diagram of FIG. 1, and FIG. Control input / output chart of continuous control circuit,
FIG. 4 is a waveform diagram at the time of continuous error in one embodiment of the present invention, FIG. 5 is a block diagram of a signal in a conventional example, FIG. 6 is a block diagram of a reproducing circuit of a digital signal recording / reproducing apparatus in a conventional example, FIG. 7 is a waveform diagram showing a write block address and a read block address of TBC memory in the conventional example, FIG. 8 is a layout diagram of parity codes in the conventional example, and FIG. 9 is an address for writing data to the TBC memory in the conventional example. FIG. 10 is a waveform diagram at the time of continuous error when the code is not used, and FIG. 10 is a waveform diagram at the time of continuous error when the address code is used for writing data to the TBC memory in the conventional example. 24 …… Write address generation circuit, 25 …… TBC memory, 2
6 ... Read address generation circuit, 27 ... Error detection circuit, 28 ... Error correction circuit, 29 ... Address code predictor, 30 ... Address code comparator, 31 ... Address discontinuity control circuit.

Claims (1)

[Claims] 1. A digital data reproduced from a recording medium and divided into at least a fixed number, an address code which circulates continuously, and an error which detects an error in at least the digital data and the address code. A time-axis correction memory (hereinafter referred to as TBC memory) that writes and reads a digital signal sequence that forms a block with a detection code, a write address generation circuit that generates a write address of the TBC memory, and a read of the TBC memory A read address generation circuit that generates an address, an error detection circuit that detects at least the presence or absence of an error in the digital data and the address code in the block read from the TBC memory, and an address code value of a predetermined block Address code that sequentially circulates from block to block A generated address code predictor, an address code comparator that compares the value of the predicted address code with the address code extracted from the block read from the TBC memory, the output of the error detection circuit and the address code comparator. The address discontinuity control circuit that controls the write address generation circuit by detecting the discontinuity of the address code by the output of, and read from the TBC memory by the output of the error detection circuit and the output of the address discontinuity control circuit. An error correction control device comprising an error correction circuit for performing a predetermined error correction operation on the outputted digital data.