JPH0463579B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" This invention is applicable to a digital VTR that records and plays back digital video signals.
The present invention relates to an address data correction method applied to a data transmission device to which address data that changes by a certain number of blocks is added.

"Background Art and Its Problems" In a digital VTR, a recorded signal has the data structure shown in FIG. Block synchronization signal
SYNC is located at the beginning of one block, and after that,
The arrangement is such that an identification signal (ID) and address data (AD) are located, followed by data (video data and redundant data for error correction). The identification signal is for identifying the frame, field, or recording channel of the video data of the block, and the address data is for indicating the address within one frame or one field to which the data of the block belongs. The address data is data that changes by a certain number of differences, for example, a serial number.

In conventional digital VTRs, separate error detection or error correction encoding is applied to each of the identification signal, address data, and data, and a redundant code of this error detection or error correction code is inserted. Therefore, there was a problem of increased redundancy.

``Object of the Invention'' The present invention detects errors in received address data without performing error-detectable encoding by utilizing the fact that address data changes regularly, and detects errors in received address data. The object of the present invention is to provide a method for correcting address data. According to this invention, the redundancy of one block can be reduced. Another object of the present invention is to realize an address data correction method that allows address data to be corrected to a certain extent even during non-normal reproduction in which the running speed of the magnetic tape is different from that during recording.

"Summary of the Invention" This invention synchronizes a plurality of pieces of received address data, detects the difference between successive pieces of the synchronized address data, and calculates the detected difference and a fixed number. A flag signal indicating the presence or absence of an error is formed by comparison, and in the case of an error, the correct data indicated by the flag among the plurality of address data, and the address data closest in time to the error data. For,
The error is corrected by calculating a predetermined number corresponding to this time difference.

"Embodiment" Hereinafter, an embodiment in which the present invention is applied to a digital VTR will be described with reference to the drawings.

As shown in FIG. 2, in this embodiment, an error detection code such as an adjacent code (b-
Recording is performed by adding parity codes P and Q (adjacent code). If there are m words of identification signal and address data (a word is 8 bits, for example) from A ₁ to Am, and n words of data from D ₁ to _{D o} , then the two parity codes P and Q can be calculated using the following equations. It is formed by

P= _n 〓 ⁱ⁼¹ Ai _o 〓 ^j=1 Dj Q= _n 〓 ⁱ⁼¹ T ^m+n+1-i Ai _o 〓 ^j=1 T ^n+1-j Dj In the above formula, (mod .2) represents the addition of T
is the companion matrix of adjacent codes
shows.

A recording signal to which such an error detection code is added is recorded on a magnetic tape by a rotating head. For example, two parallel tracks are simultaneously formed by two channel heads, and a recording signal for 1/4 field is recorded on each track. Of the identification signals, the frame ID signal, field ID signal, and channel ID signal do not change within one track. Further, the address data is a consecutive number indicating the order of all blocks included in one field. The reproduction signal reproduced from the magnetic tape by the rotary head is transmitted through a rotary transformer, a reproduction amplifier, a waveform shaping circuit, a bit clock extraction circuit, a block synchronization detection circuit, and a multiplexer (not shown) as indicated by 1 in FIG. Supplied to the input terminal.

This reproduced data is supplied to the channel decoder 2. This channel decoder 2 is provided in correspondence with a channel encoder which converts 1 word of 8 bits into 1 word of 10 bits during recording, and reproduced data converted to 1 word of 8 bits appears at its output. This reproduced data is supplied to a TBC (time base correction circuit) 3, and time base fluctuations in the reproduced signal are removed. The output of this TBC3 is ID/
The signal is supplied to the AD interpolation circuit 4. As will be described later, this ID/AD interpolation circuit 4 performs interpolation using the regularity of each of the identification signal and address data, and the buffer memory that delays the reproduced data for the time required for this interpolation is the TBC memory. It is also used as

The output data of the ID/AD interpolation circuit 4 is supplied to the error correction circuit 5, and error detection and error correction are performed on the data. The video data is subjected to error correction encoding separately from the identification signal and address data. For example, a predetermined number of blocks are arranged in a matrix, and data contained in the same column and row is subjected to error correction encoding using simple parity or adjacent codes. The output of this error correction circuit 5 is supplied to an error detection circuit 6, and errors in the identification signal, address data, and data are detected. During normal playback, the identification signal and address data are determined to be correct by the ID/AD interpolation circuit 4, so the error detection circuit 6 essentially only detects errors in the data and parity codes P and Q. will be done.

Although not shown, the error detection circuit 6 is provided with a delay circuit that delays the reproduced data during the period during which the above-described error detection is performed, and the reproduced data and the error flag are supplied to the frame memory 7 in synchronization. . In the frame memory 7, reproduced video data is written to an address corresponding to the address data. The error flags formed by the ID/AD interpolation circuit 4 are also supplied to the frame memory 7 at the same timing, and only the video data for which both error flags are 1 (high level) and it is determined that there is no error is stored in the frame. Writing of video data that is written to the memory 7 and determined to have an error with an error flag of 1 to the frame memory 7 is prohibited, and only the error flag is written. Although the video data has already been corrected by the error correction circuit 5, the error detection circuit 6 finally detects errors that cannot be corrected and erroneous corrections.

Video data and error flags are sequentially read from frame memory 7 and supplied to correction circuit 8. This correction circuit 8 uses average value interpolation or the like to make errors less noticeable. The output of the modification circuit 8 is then supplied to the D/A converter 9, and an analog reproduced video signal appears at its output terminal 10.

The ID/AD interpolation circuit 4 in one embodiment of the invention described above has the configuration shown in FIG. 1
The playback data for each sample (8 bits) is
The output _of latch _D1 is supplied to memory 11 and latches _D2 and _D3 . This memory 11 delays the data by the time during which the identification signal and address data are interpolated, and
That time axis variation is removed. Latches D ₂ and D ₃ contain sample clock and enable pulse ₂ ,
EN ₃ supplied. This enable pulse ₂
becomes 0 at the first sample of one block of reproduced data, and this sample is taken into latch _D2 . Also, enable pulse ₃ is to load the second sample into latch _D3 .
One block of identification signal and address data are taken into these latches D ₂ and D ₃ . Latch D ₂ no 8
Among the bits, the upper three bits are an identification signal. That is, one bit is used each for frame identification, field identification, and channel identification. In addition, the lower 5 bits of latch _D2 and the latch
A total of 13 bits (8 bits of _D3 ) are address data.

A 3-bit identification signal is applied to the cascade of latches _L11 - _L20 , and 13-bit address data is applied to the cascade of latches _L1 - _L10 . Two consecutive blocks of address data A _o and A _o-1 taken out at the outputs of the latch L ₁₀ and latch L ₉ are supplied to the subtraction circuit 12, and its output (A _o −A _o-1 )
is supplied to the comparison circuit 13. This comparison circuit 13
is supplied with an input of 1, and becomes 1 (high level) when (A _o −A _o-1 = 1), and (A _o −A _o-1 \=1)
A comparison output which is 0 (low level) is formed when . This 1-bit comparison output becomes a flag, which is supplied to the cascade of latches _F1 to _F10 .

The outputs of latches F ₅ and F ₆ are provided to OR gate 14 . Also, latches F ₁ , F ₂ , F ₃ , F ₄ , F ₇ , F ₈ ,
A total of 9 outputs, including the outputs of F ₉ and F ₁₀ and the output of OR gate 14.
The bit is used as an address input to the ROM 15.
From the ROM 15, 13-bit outputs Q ₀ to Q ₁₂ are read out. The flags stored in the latches F ₁ to _{F 10} and the address data stored in the latches L ₁ to _{L 10} correspond to each other, and the flags are supplied to the ROM 15 and controlled by the output of the ROM 15. Address data is interpolated.

The address data output from the latches L ₁ , L ₂ , L ₃ , L ₄ , and L ₅ are sent to the gates G ₁ , G ₂ , G ₃ , G ₄ ,
G ₅ , and the output of any one of the gates G ₁ to _{G 5} is input to one of the subtracter 16 and the adder 17 . Further, the address data output from the latches L ₆ , L ₇ , L ₈ , and L ₉ are sent to the gates G ₆ , G ₇ ,
G ₈ and G ₉ , and the output of any one of these gates G ₆ to _{G 9} is used as the other input of the subtracter 16 . Gates G ₁ to _{G 4} are controlled by the 4-bit output of decoder 18, and gate G ₅ is controlled by a signal obtained by inverting the output of OR gate 14 by inverter 19. Further, gates G ₆ to G ₉ are connected to gates 4 of the decoder 20.
Controlled by bit output. Gates _G1 to _G9 are
It turns on when the control signal is 0, and turns off when the control signal is 1. These gates G ₁ to _{G 9} are
Can be configured by tri-states.

The decoder 18 is supplied with the outputs Q ₀ and Q ₁ of the ROM 15, and the decoder 20 is supplied with the outputs of the ROM 15.
Q ₂ and Q ₃ are supplied. Further, the output of the OR gate 14 is supplied as an enable input to the decoder 18, so that when the output of the OR gate 14 is 1, the outputs of the decoder 18 are all 1 regardless of the input. The outputs Q ₀ and Q ₁ of the ROM15 are the latch F ₁
Of the latches _L1 to _L4 whose error flags are 1 among the error flags _F4 , the gate to which the output of the highest one is supplied to the latch _L5 is turned on.
The outputs Q ₂ and Q ₃ of the ROM 15 are set so that the gate of the latch closest to L 5 among the latches F ₇ to _{F 10} or one of the latches L ₅ to L ₉ , which is one more than _one , is turned on. do.

Further, the output of the subtracter 16 is used as one input of the comparison circuit 21. The outputs Q ₄ to _{Q 7} are supplied from the ROM 15 as the other input of the comparison circuit 21 . Let the gate turned on by the outputs Q ₀ and Q ₁ of ROM15 be Gl (1≦l≦4), and the output of ROM15
The gate turned on by Q ₂ and Q ₃ is Gk (7≦k≦
10), the value of (k-l) is ROM15
The outputs are Q ₄ to _{Q 7} . At this time, the subtracter 16 calculates (output of Gk - output of Gl), and the comparison circuit 21 determines whether this result is equal to the value of (k-l) from the ROM 15. This comparison circuit 21 generates a comparison output that becomes 1 when the two match, and this output is supplied to the OR gate 22.

That is, if the address data stored in latch _L5 is in error, it is determined whether the address data output from gates Gl and Gk are continuous. During non-normal playback, when the playback head crosses the video track, the block addresses become discontinuous and the difference between the output of gate Gk and the output of gate Gl is not equal to (k-l). , the output of the comparison circuit 21 becomes 0. The output of OR gate 22 is applied via AND gate 23 to latch _D5 . This latch _D5 outputs an error flag regarding address data. Therefore, if the output of comparator circuit 21 is 0, the output of AND gate 23 will be 0, and the error flag from latch _D5 will be 0. This error flag indicates that the address data is correct when it is 1, and indicates that the address data is incorrect when it is 0.
The output of indicates that it is not available.

Furthermore, it appears at the output of any of gates G ₁ to _{G 5} .
Adder 1 to which 13-bit address data is supplied
7 is supplied with the 4-bit output Q ₈ to Q ₁₁ of the ROM 15 via an AND gate 24, and the address data after interpolation is obtained at the output of this adder 17. The AND gate 24 is controlled by the output of the OR gate 14 via the inverter 19, and when the output of the OR gate 14 is 1, the output of the AND gate 24 is 0, and one input of the adder 17 is 0. . In other words, when the flag taken into latch _F5 or _F6 is 1, it is considered that the address data stored in latch _L5 is correct, so only gate _G5 is turned on among gates _G1 to _G5 . However, this address data _A5 is supplied to the adder 17 via the gate _G5 , and appears as it is at the output of the adder 17.

The upper 5 bits of the output of this adder 17 are latched.
_D6 and its lower 8 bits are fed to latch _D7 . Latch _D6 is also supplied with a 3-bit identification signal interpolated as described below. Furthermore, the data output from memory 11 is latched.
Supplied to _D8 . The outputs of these latches D ₆ , D ₇ , D ₈ are combined into one output line 25,
Output control pulse ₆ for each latch,
OT ₇ and ₈ output one sample at a time in a predetermined order.

Furthermore, when the flags stored in the latches _F5 and _F6 are both 0, the gate Gl selected by the outputs _Q4 to _Q7 of the ROM15 is turned on, and this gate
The value of latch Ll becomes one input of adder 17 via Gl. Therefore, this address data
Al is for address data A ₅ of latch L ₅ ,
Due to its continuity, the number is smaller by (A ₅ - Al).
Therefore, the ROM 15 generates these values as outputs Q ₈ to Q ₁₁ and adds them to the address data Al in the adder 17.

Furthermore, the output Q ₁₂ of the ROM 15 is connected to the AND gate 23.
If the output Q ₁₂ is 0, the output of the AND gate 23 will be 0. The flags of latches F ₅ and F ₆ are both 0, and the flags of latches F ₁ to F ₄ are all 0, or the flags of latches F ₇ to _{F 10} are all 0.
In this case, interpolation of address data becomes impossible, and the outputs Q ₀ to Q ₁₁ of the ROM 15 may be appropriate values. In this case, the output _Q12 of the ROM 15 becomes 0, and the error flag indicating that the address data of this block is in error is set to the latch _D5.
is output from. Otherwise, the output Q ₁₂ of ROM 15 is 1.

Interpolation of address data in one embodiment of the invention described above will be explained with reference to FIG.
Continuous reproduction data of blocks B _-3 to _B10 as shown in FIG. 5A is supplied, and address data A _-3 to _A10 included in each block is shown in FIG. 5B. Assume that there is a true/wrong relationship like this. In FIG. 5B, the ◯ mark indicates that there is no error, and the x mark indicates that there is an error.

This address data is supplied to the cascade of latches _L1 to _L10 and also to the subtractor 12,
(A _o −A _o-1 ) is calculated. It is determined by the comparison circuit 13 whether this result matches 1, and the result is shown in FIG. 5C, which corresponds to the correct/incorrect relationship shown in FIG. 5B. Then, a flag (corresponding to address An) which becomes 1 when the flag matches 1 is generated, and this flag is supplied to latches F ₁ to F ₁₀ . At a certain timing, a flag is stored in the latches _F1 to _F10 as shown in FIG. 5D, and the corresponding address data is stored.
A ₁ to A ₁₀ are connected to latches L ₁ to A 10 as shown in FIG.
Stored in L ₁₀ .

The object of interpolation (correction) is the address data stored in latch _L5 . Unlike the example shown in FIG. 5, if the flag stored in latch _F5 or _F6 is 1, ( _A5 - _A4 )
Or (A ₆ −A ₅ ) matches 1, which means that address data A ₅ is correct. In this case, address data A ₅ is passed through gate G ₅ , adder 17 and latches D ₆ and D ₇ to output line 25.
It is taken out as is. Also, the data of this block is read out from the memory 11 and connected to the latch _D3.
The signal is taken out to the output line 25 via.

In the example shown in FIG. 5, address data A ₅
If there is an error in the address data
Among A ₁ to _{A 4} , the address data closest to A ₅ and correct is A ₃ . Therefore, ROM1
The gate G ₃ is turned on by the outputs Q ₀ and Q ₁ of 5, and this address data A ₃ is supplied to the adder 17 . The outputs Q ₈ to _{Q 11} of ROM15 are the latch L ₃
Corresponding to selecting the value of , the value of (A ₅ -A ₃ =2) is obtained, so the adder 17 obtains interpolated address data A ₅ .

In interpolation regarding reproduced data of the same track, there is no possibility that the above-mentioned interpolation operation by the adder 17 will result in erroneous interpolation. However, during non-normal playback, the rotary head scans across a plurality of tracks, so if the correct address data used for interpolation is for another track, incorrect interpolation will occur. However, in one embodiment of the invention, if such an erroneous interpolation is made, the subtractor 16
The comparator circuit 21 sets the error flag output from the latch _D5 to 0, thereby informing subsequent circuits that the output address data is invalid.

As mentioned above, when the address data _A3 stored in the latch _L3 is selected, the ROM15
, the flag with the largest number among the latches F ₇ to F ₁₀ is 1, and the gate G ₇ of the latch L ₇ (see FIG. 5B) closest to the latch L ₅ is turned on. Q ₂ and Q ₃ are generated from ROM15. Therefore, in the subtracter ₁₆ , address data _A3 of latch _L3 is subtracted from address data _A7 of latch L7. Then, in the comparison circuit 21, the ROM 15
It is checked whether the outputs Q ₄ to Q ₇ (A ₇ −A ₃ =4) of the subtracter 16 match the outputs of the subtracter 16. In the case of playback data from the same track, there is continuity in the address data values, so they match,
An output of 1 is generated from the comparator circuit 21. but,
If a change in the track played between blocks _B3 and _B7 occurs, continuity will be lost and the comparator circuit 2
The output of 1 becomes 0, indicating that this address data is invalid.

Furthermore, the quality of the playback data is extremely poor and the latch
If the flags output from F ₅ and F ₆ are both 0, and the flags output from latches F ₁ to _{F 4} and latches F ₇ to _{F 10} are all 0, interpolation is impossible. , the output _Q12 of ROM15 becomes 0,
The error flag output to the subsequent circuit becomes 0.

Interpolation of the identification signal in the embodiment of the invention described above will be explained. The 3-bit identification signal is
Supplied to the cascade connection of latches L ₁₁ to L ₂₀ , the latches
The identification signals appearing at the outputs of L ₁₁ -L ₁₅ and the output of latch D ₄ are supplied to majority logic circuit 26 .
At the same time, the outputs of latches F ₁ -F ₆ are supplied to majority logic circuit 26. The majority logic circuit 26 is provided with a majority logic circuit for each frame identification signal, field identification signal, and channel identification signal.

This identification signal has the same value for all consecutive blocks in one track. Then, by referring to the flag series appearing in the outputs of latches _F2 to _F6 , select 0 out of the set of identification signals that are considered to be correct.
Alternatively, a large number of 1 are adopted. The frame identification signal included in the majority logic circuit 26 is shown in FIG. The ROM 27 constitutes a majority logic circuit, and a latch is applied to this ROM 27.
A frame identification signal (FRID) among the identification signals stored in L ₁₁ to _{L 15} and flags of latches F ₁ to F ₆ are input. If there is no error in the address data, it is considered that there is no error in the identification signal for that block, so whether the input frame identification signal is valid or invalid is determined by the flag. In other words, the frame identification signal from latch L ₁₁ indicates that the flag from latch F ₁ or F ₂ is 1.
The frame identification signal from latch _L12 is valid when the flag from latch _F2 or _F3 is 1.
The frame identification signal from latch L ₁₃ is valid when the flag from latch F ₃ or F ₄ is 1.
The frame identification signal from latch _L14 is valid when the flag from latch _F4 or _F5 is 1.
The frame identification signal from latch _L15 is valid when the flag from latch _F5 or _F6 is 1.
It is considered valid when

Along with this validity determination, the ROM 27 stores the valid values of the latches L ₁₁ , L ₁₂ , L ₁₃ , L ₁₄ , and L ₁₅ and the frame identification signal FRID _o-1 of the previous block from the latch D ₄ . A majority logic decision is made in which the output FRID _o is the value with more 1s or 0s out of the set consisting of . If the number of 1's or 0's in this set is the same, or if all signals other than frame identification signal FRID _o-1 are invalid, this frame identification signal FRID _o-1 is output. Although not shown, a ROM that performs similar operations is also provided for the husband and wife of the field identification signal and channel identification signal. The interpolated 3-bit identification signal output from majority logic circuit 26 is then supplied to latch _D6 .

In one embodiment of the invention described above, the latch
The error flag output from _D5 is used to control the writing of data into frame memory 7, together with the error flag from the aforementioned error detection circuit 6 (see FIG. 3). That is, when one of the error flag from the ID/AD interpolation circuit 4 and the error flag from the error detection circuit 6 to which the present invention is applied is 0, writing of data to the frame memory 7 is prohibited.

"Application example" When interpolating address data, the latch
Instead of using the data in the blocks before _L5 , the correct address data included in the blocks after this may be used.

[Effects of the Invention] According to the present invention, address data can be corrected without adding special error detection and error correction codes to address data, and redundancy can be reduced. Furthermore, in the present invention, even if the regularity of address data is lost, such as during non-normal playback of a digital VTR, as long as this regularity exists to some extent, such as with playback data of the same track, , the address data can be corrected. However, since the correct address data used for interpolation is from the block closest to the error data, the length that cannot be corrected when a track jump occurs can be minimized.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram showing an example of a data structure in a digital VTR to which this invention can be applied, FIG. 2 is a schematic diagram showing a data structure in an embodiment of this invention, and FIG. FIGS. 4 and 6 are block diagrams showing the overall configuration of an embodiment of the present invention, and FIGS. This is a time chart used to explain the operation of the AD interpolation circuit. 4...ID/AD interpolation circuit, 7...frame memory, 12, 16...subtractor, 13, 21...comparison circuit, 15, 27...ROM, 26...majority logic circuit.

Claims (1)

[Claims] 1. Address data received on the receiving side of a data transmission device that transmits digital data transmitted in blocks with address data formed such that there is a certain number of differences between successive address data. Synchronize multiple pieces of data, detect the difference between successive pieces of the synchronized address data, and compare the detected difference with the above-mentioned constant number to form a flag signal indicating the presence or absence of an error. However, in the case of an error, the correct address data indicated by the flag among the plurality of address data, and which is the closest in time to the error data, is corrected to correspond to this time difference. An address data correction method that corrects errors by calculating a predetermined number.