JPH0754503B2 - Microprocessor bus interface circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a microprocessor included in a functional block for connecting the functional block and a general-purpose microprocessor bus of a home device in which the functional block is incorporated. The present invention relates to a bus interface circuit.

(2) Conventional Technology Conventionally, such a microprocessor bus interface circuit was designed by limiting the type of the microprocessor to be connected to the bus interface circuit.
Therefore, the data transfer function and the microprocessor
When the function corresponding to the control signal of the bus is integrally configured or the data is transferred, the function between the function and the function corresponding to the control signal of the microprocessor bus is targeted by the microprocessor bus interface circuit. It was configured to communicate by an internal signal depending on the bus control signal of the processor.

As for the data transfer method, the I / O transfer method or the DMA transfer method was set in advance when the circuit was designed, and the address generator and bus control signal generator were designed. Therefore, the function of transferring data and the function of generating a bus control signal to be output to the microprocessor bus are integrally configured, or a part of the function is shared.

FIG. 4 is a diagram for explaining an example of I / O transfer according to the conventional technique. 100 is a microprocessor interface circuit according to the conventional technique, 101 is a microprocessor in a functional block, 102 is a data bus, and 103 is a control. A bus, 104 is a data transfer circuit, 105 is a data transfer control circuit, 106 is a general-purpose microprocessor to which functional blocks are connected, 107 is a control bus, and 108 is a data bus.

The operation of this will be described. The microprocessor 101 puts the data to be output from the functional block on the data bus 102, and writes the data to the data transfer circuit 104 by the control bus 103. The data transfer circuit 104 monitors the control bus 103 and, when detecting a write instruction, takes data from the data bus 102. Data transfer control circuit 1
Reference numeral 05 transfers / holds the data written from the microprocessor 101 inside the data transfer circuit 104. When there is data to be output to the general-purpose microprocessor 106 inside the data transfer circuit 104, the data transfer control circuit 105 puts a take-out request signal on the control bus 107 in order to make the general-purpose microprocessor 106 take over the data. In response to the take-back request, the general-purpose microprocessor 106 puts a control signal for reading data on the control bus 107. The data transfer circuit 104 monitors the control bus 107, outputs a data to the data bus 108 when detecting the reading instruction, and the general-purpose microprocessor 106 takes the data through the data bus 108. Data transfer control circuit 1
05 detects that the general-purpose microprocessor 106 has responded to the take-back request, and then withdraws the take-back request. The data transfer control circuit 105 monitors the control bus 107, and after the data reading sequence is completed, the data to be output next is transferred inside the data transfer circuit 104 and a take-back request is output to the control bus 107. When the general-purpose microprocessor 106 writes data to the functional block, the data is put on the data bus 108 and the write control signal is put on the control bus 107. The data transfer circuit 104 monitors the control bus 107, and when it detects a read instruction, it takes data from the data bus 108. The data transfer control circuit 105 monitors the control bus 107,
When it is detected that the data has been written in the data transfer circuit 104, the data in the data transfer circuit 104 is transferred and held, and a take-back request signal is put on the control bus 103 so that the microprocessor 101 can take the data. In response to the take-back request, the microprocessor 101 puts a control signal for reading data on the control bus 103 and takes in data from the data transfer circuit 104 through the data bus 102. The data transfer circuit 104 and the data transfer control circuit 105 monitor a bus control signal output from the general-purpose microprocessor 106 to the control bus 107 to input / output and transfer data, and further receive data corresponding to the general-purpose microprocessor 106. This function block is a circuit dedicated to the type of the target microprocessor, such as creating a request signal and outputting it to the control bus 107.

Due to such a configuration, it is impossible to support a microprocessor of a type not covered by the microprocessor bus interface circuit, or a circuit for converting the bus interface is added outside the functional block. Then, it was necessary to connect to the microprocessor bus. In addition, when modifying the functional block to change the type of the microprocessor that is the target of the microprocessor bus interface circuit, or when changing the transfer method such as changing the data transfer method to DMA, a new microprocessor Not only the part that needs to be changed depending on the bus control signal, but also the data transfer function part needs to be remodeled significantly, and in order to deal with the bus control signals of multiple microprocessors, In the microprocessor bus interface circuit, these bus control signal corresponding parts and data transfer function parts must be prepared only for the types of bus control signals corresponding to the microprocessor, and it is possible to support multiple data transfer methods. Therefore, the interface circuit was required only for the type of data transfer.

(3) Object of the Invention An object of the present invention is to enable a microprocessor bus interface circuit to correspond to bus control signals of a plurality of microprocessors so that a plurality of control signal corresponding parts and data transfer are provided in the microprocessor bus interface circuit. A microprocessor bus that solves the problems that a functional part or the like is required, and that significant modification or addition is required when changing or adding bus control signals and data transfer methods supported by the microprocessor bus interface circuit -To provide an interface circuit.

(4) Configuration of the Invention (4-1) Difference between Features of the Invention and Prior Art The present invention divides each functional unit constituting a microprocessor bus interface circuit, and separates those functional units from each other. Unlike the control signal of the microprocessor to which the processor bus interface circuit corresponds, the most main feature is that communication is performed by a general-purpose control signal that absorbs the difference between the processor types. The conventional technology is (1) the functional unit such as individual data transfer in the microprocessor bus interface circuit is separated from the functional units corresponding to other microprocessor control signals, (2)
Different from the bus control signal of the microprocessor to which the interface circuit corresponds in the microprocessor bus interface circuit, each functional unit operates according to the general-purpose control signal that absorbs the difference between the processor types. (3) Microprocessor Of the functional units in the processor bus interface circuit, the functional unit that is affected by the type of general-purpose microprocessor to which the interface circuit corresponds is the bus control signal output by the microprocessor in the microprocessor bus interface circuit. The difference is that it is configured so as to be limited to a functional unit that converts a general-purpose control signal to be used and a functional unit that generates a bus control signal corresponding to a microprocessor from the general-purpose control signal in the bus interface circuit.

(4-2) Embodiment FIG. 1 is a diagram for explaining the first embodiment of the present invention.
00 is a microprocessor interface circuit according to the present embodiment, 201 is a data transfer circuit, 202 is a bus control signal generation circuit, 203 is a general-purpose microprocessor control bus to which functional blocks are connected, 204 is a general-purpose microprocessor, and 205 is a bus. A control signal conversion circuit, 206 is a data bus, 207 is an address bus, 208 is an address creating circuit, 209 is an external address buffer, 210 is a memory, and 211 is a control register.

(1) In the case of I / O transfer When accessing (I / O transfer) by an input / output instruction of a general-purpose microprocessor from outside the function block, the data output from the function block by the data transfer circuit 201 is required to operate. There is an output transfer control signal RQO, which is a kind of general-purpose control signal, to inform the bus control signal generation circuit 202 of the existence. The bus control signal generation circuit 202 that has received the signal RQO
In the case of the I / O point, an output request interrupt is given to the control bus 203, and the input operation of the general-purpose microprocessor 204 is waited for.
The general-purpose microprocessor 204 is a bus control signal generation circuit 202.
When an output request interrupt is received from the control bus
Put a read control signal on 203. The bus control signal conversion circuit 205 converts the control signal input from the control bus 203 into a general-purpose control signal DO inside the functional module according to the type of general-purpose microprocessor, and then the data transfer circuit 20.
The data transfer circuit 201 outputs the data to the data bus 206 according to the general-purpose control signal DO. The data output to the data bus 206 is taken by the general-purpose microprocessor 204. Conversely, when the general-purpose microprocessor 204 outputs data, the bus control signal conversion circuit 205 converts the output control signal input from the control bus 203 into a general-purpose control signal DI corresponding to the type of general-purpose microprocessor, and then the data transfer circuit 201. Then, the data transfer circuit 201 receives the data from the data bus 206. The data transfer circuit 201 processes the received data and then uses the output transfer control signal RQI which is a kind of general-purpose control signal to generate the bus control signal generation circuit 202.
The bus control signal generation circuit 202 which has received the signal RQI notifies the general-purpose microprocessor 204 of a data write ready interrupt.

(2) In the case of DMA transfer When the functional block acts as a bus master to perform DMA transfer to the outside of the functional block, the operation of this will be explained as follows.
The data transfer circuit 201 informs the bus control signal generation circuit 202 that there is data to be output from the functional block by the output transfer control signal RQO, which is a kind of general-purpose control signal.
Upon receiving O, the bus control signal generation circuit 202 gives a control signal for acquiring the bus master right according to the general-purpose microprocessor to the control bus 203 in the case of DMA transfer, and generalizes the bus right of the control bus 203, the data bus 206, and the address bus 207. Obtained from the microprocessor 204. The bus control signal creation circuit 202 also requests the address creation circuit 208 to generate an output destination address to the outside of the functional block by using an output address creation command signal OA which is a kind of general-purpose control signal. The address is set in the buffer 209. The bus control signal generation circuit 202 outputs the memory write control signal corresponding to the type of the general-purpose microprocessor to the control bus 203 in order to output the data to the memory 210 by the DMA transfer method after acquiring the bus right, and also transfers the data. The general-purpose control signals DO and AO are output to the circuit 201 and the external address buffer 209 at the timing corresponding to the type of general-purpose microprocessor, and the data and address are output to the data bus 206 and the address bus 207.
When inputting from the memory 210 by the DMA transfer method, the bus control signal generation circuit 202, which has learned from the RQI that the input buffer of the data transfer circuit 201 is empty, responds to the general purpose microprocessor to the control bus 203 in the case of DMA transfer. Control bus 20
3, The bus right of the data bus 206 and the address bus 207 is acquired from the general-purpose microprocessor 204. The bus control signal generation circuit 202 also requests the address generation circuit 208 to generate an input address to the outside of the functional block using an input address generation command signal IA, which is a kind of general-purpose control signal, and the address generation circuit 208 uses the external address buffer. Set the address in 209. The bus control signal generation circuit 202, after acquiring the bus right, inputs the data from the memory 210 by the DMA transfer method. Therefore, it outputs the memory read control signal corresponding to the type of the general-purpose microprocessor to the control bus 203 and outputs the data. Transfer circuit 201 and external address buffer 209
Further, the general-purpose control signals DI and AO are output at a timing corresponding to the type of the general-purpose microprocessor, the address is output to the address bus 207, and the data is input from the data bus 206.

Further, when the control information is written in the control register 211 because the home device controls the functional block, the general-purpose microprocessor 204 transmits the control information to the data bus 206.
Then, the bus control signal conversion circuit 205 converts the output control signal of the general-purpose microprocessor 204 input from the control bus 203 into a general-purpose control signal DI corresponding to the type of the general-purpose microprocessor, and then outputs it to the control register 211. The control register 211 takes control information from the data bus 206.

With such a configuration, the same data processing function unit can be shared by a plurality of general-purpose microprocessor types and data transfer methods, and a new type of general-purpose microprocessor can be used in the bus interface circuit. The bus control signal conversion circuit 205 and the bus control signal creation circuit 202 can be dealt with simply by adding or changing them.

Further, even when the control information or the like is set in addition to the data transfer from the general-purpose microprocessor, the bus control signal conversion circuit 205 can be shared by the data processing function unit and the control register, so that an increase in hardware scale can be suppressed. .

FIG. 2 is a diagram for explaining the second embodiment of the present invention.
00 is the microprocessor interface circuit according to the present embodiment, 301 is the microprocessor inside the functional block, 3
Reference numeral 02 is a data bus, 303 is a control bus, and 304 is a data transfer circuit.

(1) In the case of I / O transfer When accessing (I / O transfer) by an input / output instruction of a general-purpose microprocessor from outside the functional block, the operation of this will be explained. The microprocessor 301 outputs to the outside of the functional block. Output the data to the data bus 302,
A control signal for writing is placed on the control bus 303 and writing is performed in the data transfer circuit 304. The data transfer circuit 304 informs the bus control signal generation circuit 202 that there is data to be output from the functional block by an output transfer control signal RQO which is a kind of general-purpose control signal. The bus control signal creation circuit 202 that receives the RQO, the I / O transfer control bus 203
The output request interrupt is raised to the general-purpose microprocessor 20
Wait for 4 input operation. When the general-purpose microprocessor 204 receives an output request interrupt from the bus control signal generation circuit 202, it places a read control signal on the control bus 203. The bus control signal conversion circuit 205 converts the control signal input from the control bus 203 into a general-purpose control signal DO inside the functional module corresponding to the type of general-purpose microprocessor, and then outputs it to the data transfer circuit 304. Data is output to the data bus 206 according to the general-purpose control signal DO. The data output to the data bus 206 is taken by the general-purpose microprocessor 204. Conversely, when the general-purpose microprocessor 204 outputs data, the bus control signal conversion circuit 205 converts the output control signal input from the control bus 203 into a general-purpose control signal DI corresponding to the type of general-purpose microprocessor, and then the data transfer circuit 304. And the data transfer circuit 304 receives the data from the data bus 206. The data transfer circuit 304 notifies the microprocessor 301 through the control bus 303 that there is data taken in from outside the functional block, and the microprocessor 3
01 receives data from the data transfer circuit 304 through the data bus 302. After the data transfer circuit 304 outputs the received data to the microprocessor 301, the data transfer circuit 304 notifies the bus control signal generation circuit 202 of the completion of processing by the input transfer control signal RQI which is a kind of general-purpose control signal, and receives the RQI and generates the bus control signal. The circuit 202 sends a data write ready interrupt through the control bus 203 to the general-purpose microprocessor 2
I'll give it to 04.

(2) In the case of DMA transfer When the functional block acts as a bus master to perform DMA transfer to the outside of the functional block, the operation of this will be explained as follows.
The microprocessor 301 outputs the data output to the outside of the functional block to the data bus 302, and the control bus 303
A write control signal is placed on and written in the data transfer circuit 304. The data transfer circuit 304 informs the bus control signal generation circuit 202 that there is data to be output by the output transfer control signal RQO which is a kind of general-purpose control signal, and the bus control signal generation circuit 202 which receives the RQO A control signal for acquiring the bus master right according to the general-purpose microprocessor is given to the control bus 203, and the bus right of the control bus 203, the data bus 206, and the address bus 207 is acquired from the general-purpose microprocessor 204. Bus control signal generation circuit 202
Also requests the address generation circuit 208 to generate an output destination address to the outside of the functional block using an output address generation command signal OA which is a kind of general-purpose control signal, and the address generation circuit 208 sets the address in the external address buffer 209. To do. After the bus control signal generation circuit 202 acquires the bus right,
In order to output data to the memory 210 by the DMA transfer method, a memory write control signal corresponding to the type of the general-purpose microprocessor is output to the control bus 203, and the type of the general-purpose microprocessor is output to the data transfer circuit 304 and the external address buffer 209. The general-purpose control signals DO and AO are output at a timing corresponding to, and the data and address are output to the data bus 206 and the address bus 207. When inputting from the memory 210 by the DMA transfer method, the bus control signal generating circuit 202, which has learned from the RQI that the input buffer of the data transfer circuit 304 is empty, uses the control bus 2 for the DMA transfer.
The control signals for bus mastership acquisition according to the general-purpose microprocessor are given to 03, and the control bus 203, data bus 20
6, the bus right of the address bus 207 is assigned to the general-purpose microprocessor 2
Acquire from 04. The bus control signal generation circuit 202 also requests the address generation circuit 208 to generate an input address to the outside of the functional block using an input address generation command signal IA, which is a kind of general-purpose control signal, and the address generation circuit 208 uses the external address buffer. Set the address in 209. The bus control signal generation circuit 202, after acquiring the bus right, inputs the data from the memory 210 by the DMA transfer method. Therefore, it outputs the memory read control signal corresponding to the type of the general-purpose microprocessor to the control bus 203 and outputs the data. A general-purpose control signal is sent to the transfer circuit 304 and the external address buffer 209 at a timing corresponding to the type of the general-purpose microprocessor.
AO and DI are output, an address is output to the address bus 207, and data is input from the data bus 206 to the data transfer circuit 304.

Further, when the control information is written in the control register 211 because the home device controls the functional block, the general-purpose microprocessor 204 transmits the control information to the data bus 206.
Then, the bus control signal conversion circuit 205 converts the output control signal of the general-purpose microprocessor 204 input from the control bus 203 into a general-purpose control signal DI corresponding to the type of the general-purpose microprocessor, and then outputs it to the control register 211. The control register 211 takes control information from the data bus 206.

With such a configuration, the same data transfer function unit can be shared by a plurality of general-purpose microprocessor types and data transfer methods, and a new type of general-purpose microprocessor can be used in the bus interface circuit. The bus control signal conversion circuit and bus control signal creation circuit can be added and changed.

Further, even when the control information or the like is set in addition to the data transfer from the general-purpose microprocessor, the bus control signal conversion circuit can be shared by the data transfer function unit and the control register, so that an increase in hardware scale can be suppressed. .

FIG. 3 is a diagram for explaining the third embodiment of the present invention.
00 is a microprocessor interface circuit according to the present embodiment, 401 is a memory in a functional block, 402 is a bus control signal generation circuit, 403 is an address generation circuit, 404 is an internal address buffer, 405 is an address bus inside the functional block, 406
Is a data transfer circuit.

(1) In the case of I / O transfer When accessing (I / O transfer) by an input / output instruction of a general-purpose microprocessor from the outside of a functional block, the operation of this is explained. The processor 301 sets the data to be output to the outside of the functional block in the memory 401, and then requests the bus control signal generation circuit 402 to transfer the data via the control bus 303. Upon receiving the data transfer request, the bus control signal creation circuit 402 requests the address creation circuit 403 to generate an address for data transfer from the memory 401 by the signal A1, and the address creation circuit 403 sends the internal address buffer 404. Set the address to. The bus control signal generation circuit 402 also outputs a control signal for acquiring the bus master right to the microprocessor 301 through the control bus 303, and the data bus 302, the control bus 303, and the address bus.
After acquiring the bus right of 405, the control signal for output to the memory is output to the control bus 303, the address of the transfer data is output to the address bus 405 by the signal A3, and the data is transferred from the memory 401 to the control bus 303. Output. The bus control signal generation circuit 402 is the data transfer circuit 4
06 is also controlled at the same time, and the data output to the control bus 303 is input to the data transfer circuit 406. The data transfer circuit 406 notifies the bus control signal generation circuit 402 that there is data to be output from the functional block through an output transfer control signal RQO which is a kind of general-purpose control signal. In the case of I / O transfer, the bus control signal generation circuit 402 that has received RQO raises an output request interrupt to the control bus 203 and waits for an input operation of the general-purpose microprocessor 204. When the general-purpose microprocessor 204 receives an output request interrupt from the bus control signal generation circuit 402, it places a read control signal on the control bus 203. The bus control signal conversion circuit 205 converts the control signal input from the control bus 203 into a general-purpose control signal DO inside the functional module corresponding to the type of general-purpose microprocessor, and then outputs it to the data transfer circuit 406.
The data transfer circuit 406 outputs data to the data bus 206 according to the general-purpose control signal DO. The data output to the data bus 206 is taken by the general-purpose microprocessor 204. Conversely, when the general-purpose microprocessor 204 outputs data, the bus control signal conversion circuit 205 converts the output control signal input from the control unit 203 into a general-purpose control signal DI corresponding to the type of general-purpose microprocessor, and then the data transfer circuit 406. Then, the data transfer circuit 406 takes in the data from the data bus 206. The data transfer circuit 406 informs the bus control signal generation circuit 402 by the signal RQ2 that there is data taken in from outside the functional block, and the bus control signal generation circuit 402 transfers the data to the memory 401 to the address generation circuit 403 by the signal A2. The address generation circuit 403 sets the address in the internal address buffer 404. Bus control signal generation circuit 4
The 02 also outputs a control signal for acquiring the bus master right to the microprocessor 301 through the control bus 303, acquires the bus right of the data bus 302, the control bus 303, and the address bus 405, and then inputs the memory to the control bus 303. In addition to outputting the control signal, the address of the transfer data is output to the internal address buffer 404 by the signal A3. Further, the bus control signal generation circuit 402 controls the data transfer circuit 406 to output data to the data bus 302,
Data is input to the memory 401 through the data bus 302. The data transfer circuit 406 outputs the data input from the outside of the functional block to the memory 401, then notifies the bus control signal generation circuit 402 of the completion of processing by the input transfer control signal RQI which is a kind of general-purpose control signal, and receives the signal RQI. The bus control signal generation circuit 402 sends a data write ready interrupt to the general-purpose microprocessor 2 through the control bus 203.
I'll give it to 04.

(2) In the case of DMA transfer When the functional block acts as a bus master to perform DMA transfer to the outside of the functional block, the operation of this will be explained as follows.
After the data output from the microprocessor 301 to the outside of the functional block is set in the memory 401, the control bus 3
Request the data transfer to the bus control signal generation circuit 402 through 03. In response to the data transfer request, the bus control signal generation circuit 402 requests the address generation circuit 403 to generate an address for data transfer from the memory 401 by the signal A1, and the address generation circuit 403 causes the internal address buffer 4 to operate.
Set the address to 04. Bus control signal generation circuit 402
Also outputs a control signal for acquiring the bus master right to the microprocessor 301 through the control bus 303, acquires the bus right of the data bus 302, the control bus 303, and the address bus 405, and then controls the output to the memory on the control bus 303. In addition to outputting the signal, the address of the transfer data is output to the address bus 405 by the signal A3, and the data is output from the memory 401 to the control bus 303. The bus control signal generation circuit 402 also controls the data transfer circuit 406 at the same time to input the data output to the data bus 302 to the data transfer circuit 406. The data transfer circuit 406 informs the bus control signal generation circuit 402 that there is data to be output by the output transfer control signal RQO which is a kind of general-purpose control signal, and the bus control signal generation circuit 402 which received the RQO
In the case of transfer, a control signal for acquiring the bus master right according to the general-purpose microprocessor is given to the control bus 203, and the bus right of the control bus 203, the data bus 206, and the address bus 207 is acquired from the general-purpose microprocessor 204. The bus control signal creation circuit 402 also requests the address creation circuit 403 to generate an output destination address to the outside of the functional block by using an output address creation command signal OA, which is a kind of general-purpose control signal. The address is set in the buffer 209. The bus control signal generation circuit 402 is
After acquiring the bus right, a memory write control signal corresponding to the type of the general-purpose microprocessor is output to the control bus 203 in order to output the data to the memory 210 by the DMA transfer method, and at the same time, the data transfer circuit 406 and the external address buffer 209. The general-purpose control signals DO and AO are output at the timings corresponding to the general-purpose microprocessor type, and the data and address are output to the data bus 206 and the address bus 207. When inputting from the memory 210 by the DMA transfer method, the bus control signal generating circuit 402, which has learned from the RQI that the input buffer of the data transfer circuit 406 is empty, responds to the control bus 203 by a general-purpose microprocessor in the case of DMA transfer. A control signal for acquiring the bus master right is given to acquire the bus right of the control bus 203, the data bus 206, and the address bus 207 from the general-purpose microprocessor 204. The bus control signal generation circuit 402 also requests the address generation circuit 403 to generate an input address to the outside of the functional block using an input address generation command signal IA, which is a kind of general-purpose control signal,
The address creating circuit 403 sets an address in the external address buffer 209. The bus control signal generation circuit 402 outputs the memory read control signal corresponding to the type of the general-purpose microprocessor to the control bus 203 to input the data from the memory 210 by the DMA transfer method after acquiring the bus right, and at the same time, outputs the data. The general-purpose control signals AO and DI are output to the transfer circuit 406 and the external address buffer 209 at the timing corresponding to the general-purpose microprocessor type, the address is output to the address bus 207, and the data is input from the data bus 206 to the data transfer circuit 406. Let

Further, when the control information is written in the control register 211 because the home device controls the functional block, the general-purpose microprocessor 204 transmits the control information to the data bus 206.
The bus control signal conversion circuit 205 outputs to the control register 211 after converting the output control signal of the general-purpose microprocessor 204 input from the control bus 203 into a general-purpose control signal DI corresponding to the type of the general-purpose microprocessor.
The control register 211 takes control information from the data bus 206.

With such a configuration, the same data transfer function unit can be shared by a plurality of general-purpose microprocessor types and data transfer methods, and even for a new type of general-purpose microprocessor, the bus interface circuit This can be dealt with simply by adding or changing the bus control signal conversion circuit and the bus control signal generation circuit.

Further, even when the control information or the like is set in addition to the data transfer from the general-purpose microprocessor, the bus control signal conversion circuit can be shared by the data transfer function unit and the control register, so that an increase in hardware scale can be suppressed. .

In addition, the address generator required for DMA transfer is used for DMA transfer inside the function block and D
Since it can be shared with MA transfer, it is possible to suppress an increase in hardware scale related to DMA transfer.

As is clear from these explanations, in the present invention, in the case of supporting a plurality of types of general-purpose microprocessors and a plurality of data transfer methods, one data transfer function unit in a function block is compared to the conventional technology. Since the microprocessor compatible part is selected and controlled to be used, the function blocks do not overlap, the hardware scale can be reduced, and the data transfer function part is compatible with the microprocessor even when compatible with a new general-purpose microprocessor type. It can be dealt with by changing only the parts, and it has the improvement effect that additions and changes are easy. By conforming to this configuration other than the data transfer function block, the microprocessor interface and address generator in the bus interface circuit can be shared.
The hardware scale of the functional blocks can be reduced, and when adding or changing the functions of the data transfer function unit itself, it can be done independently of the microprocessor-compatible unit, making additions and changes easy.

(5) Effects of the Invention As described above, according to the present invention, the microprocessor interface circuit can be selected and controlled depending on the type of the corresponding general-purpose microprocessor and the data transfer method. Section and a data transfer function section that is independent of the type of general-purpose microprocessor and the data transfer method, such as the transfer of input and output data in the circuit and the generation of output addresses. When supporting a general-purpose microprocessor, the hardware size of the microprocessor bus interface circuit can be reduced, and even when each function is changed / added, it can be easily realized and the hardware can be shared, thus reducing the hardware size. There is an advantage that the increase can be suppressed.

In addition, the bus control signal creation circuit can output the input address creation signal and the output address creation signal independently.
When the DMA transfer method is used, in addition to the above effects, there is an effect that data transfer can be performed without impairing bus utilization efficiency.

[Brief description of drawings]

FIG. 1 is a diagram illustrating a first embodiment of the present invention, FIG. 2 is a diagram illustrating a second embodiment of the present invention, and FIG. 3 is a diagram illustrating a third embodiment of the present invention. , Fig. 4 is based on conventional technology
The figure explaining the example of I / O transfer is shown. Reference numeral 200 in the figure denotes a microprocessor according to the present embodiment.
Interface circuit, 201 is a data transfer circuit, 202 is a bus control signal generation circuit, 203 is a general-purpose microprocessor control bus to which functional blocks are connected, 204 is a general-purpose microprocessor, 205 is a bus control signal conversion circuit, and 206 is a data bus , 207 is an address bus, 208 is an address generation circuit, 209 is an external address buffer, 210 is a memory, 211 is a control register, 300 is a microprocessor interface circuit according to the present embodiment, 301 is a microprocessor inside a functional block, and 302 is Data bus, 303 is a control bus, 304 is a data transfer circuit, and 400 is the microprocessor
Interface circuit, 401 is the memory in the functional block, 402
Is a bus control signal generation circuit, 403 is an address generation circuit, 404 internal address buffer, 405 is an address bus inside a functional block, and 406 is a data transfer circuit.

Front Page Continuation (72) Inventor Naofumi Nagai Address: 2356 Take, Yokosuka City, Kanagawa Pref., NTT Communication Systems Laboratories (56) References

Claims (1)

[Claims] 1. A microprocessor, which is built in a functional block, is connected to a general-purpose microprocessor bus to which a general-purpose microprocessor and a memory are connected, and which transmits and receives data to and from the general-purpose microprocessor and the memory through the general-purpose microprocessor bus. In the bus interface circuit, a data transfer circuit that sends out a transfer control signal notifying permission of transmission / reception to / from the general-purpose microprocessor bus and transmits / receives the data to / from the functional block or the general-purpose microprocessor bus; and the general-purpose microprocessor. A signal conversion circuit that receives a control signal issued by the general-purpose microprocessor bus and notifies the data transfer circuit of the timing at which the data transfer circuit transmits and receives the data to and from the general-purpose microprocessor bus; Based on the transfer control signal received from the transfer circuit, a control signal corresponding to the general-purpose microprocessor is output to the general-purpose microprocessor bus at a timing required by the general-purpose microprocessor to generate an input address creation command signal or an output address creation. The address buffer outputs the command signals independently, notifies the data transfer circuit of the timing when the data transfer circuit transmits and receives the data to and from the general-purpose microprocessor bus, and outputs the address to the general-purpose microprocessor bus. A bus control signal creation circuit for notifying the input address creation signal and the output address creation signal from the bus control signal creation circuit, and an input address for inputting data to the memory by the input address creation signal, The output address Address creation circuit for independently creating output addresses for outputting data from the memory according to the address creation signal, and the address created by the address creation circuit, and storing the address from the bus control signal creation circuit. A microprocessor bus interface circuit, comprising: an address buffer that receives a timing to be output to a general-purpose microprocessor bus and outputs the timing to the general-purpose microprocessor bus based on the timing.