JP3098550B2 - Bus control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus control system in which a bus is shared by a plurality of processors and data or commands are transferred between the processors.

[0002]

2. Description of the Related Art A conventional bus control system of this type will be described with reference to the drawings. FIG. 3 shows that a plurality of (for example, four) processors 8 to 11 are commonly connected to the control bus 5 and the unit command bus 6, and the plurality of processors 8 to 11 simultaneously use the control bus 5 and the unit command bus 6. 1 shows a multiprocessor system including a bus arbiter 7 that arbitrates, when requested, to give only one of the processors the right to use the bus according to a determined priority. Numerals 1 to 4 are bus securing request signals from the processors 8 to 11, respectively.

In the multiprocessor system shown in FIG. 3, a processor 8 is connected to one of processors 9 to 11.
FIG. 4 shows a time chart when data or command transfer is performed by accessing one processor. First, in the bus acquisition cycle E, the processor 8 sends a bus reservation request signal 1 of the control bus 5 and the unit command bus 6 to the bus arbiter 7. When the bus reservation request signal 1 is selected by the bus arbiter 7, the bus arbiter 7 sends the unit number 41 of the selected processor to the unit command bus 6, and sends a bus use permission signal 42 to a part of the control bus 5. This bus use permission signal 4
2 causes all processors to have a unit command bus 6
The upper unit number 41 is fetched, compared with the unit number of its own processor, and the processor 8 that matches as a result of the comparison returns a response signal 43 to a part of the control bus 5.

Next, in the transfer cycle F, the processor 8 sends a data transfer destination processor unit number and a command 44 to the unit command bus 6 and sends a data fetch instruction signal 45 to a part of the control bus 5. In response to the data fetch instruction signal 45, all processors fetch the destination processor unit number on the unit command bus 6 and compare it with the unit number of the own processor. A response signal 46 is returned to a part of. Then, the processor 8 transfers the data to the data transfer destination processor. When the data transfer is completed, the processor 8 drops the bus reservation request signal 1.

A technique related to this type of bus control method is disclosed, for example, in Japanese Patent Publication No. 87-11162.

[0006]

In the above-mentioned multiprocessor system, when a processor capable of high-speed response and a processor not capable of high-speed response are connected, a high-speed response is possible in the operation of the command transfer cycle shown in FIG. The time from when the processor receives the data fetch instruction signal to whether or not it accesses the own processor and returns a response is smaller than the time until the processor returns a response that is not capable of high-speed response. This relationship is shown in FIG.

However, since the processors are commonly connected to the control bus, they must operate synchronously. For this reason, the processor capable of high-speed response requires the time (G in FIG. 5) from the reception of the data capture signal to the return of the response by the processor not capable of high-speed response receiving the data capture signal and accessing the own processor. Time to recognize whether or not to return a response (H in FIG. 5)
As a result, there has been a problem that the responsiveness of a processor capable of high-speed response deteriorates.

SUMMARY OF THE INVENTION An object of the present invention is to provide a bus control system for transferring high-performance data and commands adapted to the response speed of each processor without deteriorating the responsiveness of processors capable of high-speed response. It is in.

[0009]

According to the present invention, a plurality of processors connected to a common bus and a request for use of the common bus are received from the plurality of processors. And a bus arbiter that arbitrates between the plurality of processors is divided into a processor group capable of high-speed response and a processor group not capable of high-speed response. A bus is provided for each processor group, and a bus irrelevant to the response speed is provided commonly to each processor group.

[0010]

Since the control bus of the common bus is related to the response speed, it is provided for each of a group of processors capable of high-speed response and a group of processors not capable of high-speed response. Other unit command buses and the like are provided commonly to all processors in the system. As a result, a processor capable of high-speed response does not need to match the response speed of a processor that is not capable of high-speed response, and can transfer data and commands at its own response speed, thereby improving the responsiveness of the entire system.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be specifically described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. In the present embodiment, the processors 8 and 9 are processors capable of high-speed response, and the processors 10 and 11 are processors that are not capable of high-speed response.

In FIG. 1, processors 8, 9, 10,
11 are grouped into processors 8 and 9 capable of high-speed response and processors 10 and 11 not capable of high-speed response, and are connected to the unit command bus 6 so that the processors in the group can arbitrarily communicate with each other. ing. A characteristic feature of the present invention is that a control bus related to the response speed is provided for each group. That is,
In FIG. 1, a control bus 5A for a processor group capable of high-speed response and a control bus 5B for a processor group not capable of high-speed response are provided, and the respective control buses 5A and 5B are connected to a bus arbiter 7. The bus arbiter 7 controls the right to use the buses of the processors 8 to 11 in the same manner as described above, and is individually connected to each processor by bus securing request signals 1 to 4.

First, the transfer operation between the processors 8 and 9 capable of high-speed response will be described with reference to the time chart of FIG.

In the bus acquisition cycle A, the processor 8 sends a bus reservation request signal 1 to the bus arbiter 7, and when the bus arbiter 7 selects the bus reservation request signal 1,
The unit number 21 of the selected processor is transmitted to the unit command bus 6, and the bus use permission signal 22 is transmitted to a part of the control bus 5A for the processor group which can respond at high speed. By the transmission of the bus use permission signal 22, only the processor connected to the control bus 5A has the unit number 2 on the unit command bus 6.
1 and compare it with the unit number of its own processor.
As a result of the comparison, the matched processor is the control bus 5
A response signal 23 is returned to a part of A.

Next, in the transfer cycle B, the data transfer source processor sends the unit number of the data transfer destination processor and the transfer command 24 to the unit command bus 6, and sends the data fetch instruction signal 25 to a part of the control bus 5A. Send out. This data capture instruction signal 2
5, only the processor connected to the control bus 5A fetches the transfer destination processor unit number on the unit command bus 6 and compares it with the unit number of its own processor.
The transfer command is received, and a response signal 26 is returned to a part of the control bus 5A. Then, the processor 8 transfers the data to the data transfer destination processor. When the data transfer is completed, the processor 8 drops the bus reservation request signal 1.

Next, the processor 1 which cannot respond at high speed
The transfer operation between 0 and 11 will be described with reference to the time chart of FIG.

For example, in the bus acquisition cycle C, the processor 10 sends the bus reservation request signal 3 to the bus arbiter 7, and when the bus reservation request signal 3 is selected by the bus arbiter 7, the unit number 21 of the selected processor is set to the unit command. A bus use permission signal 22 is transmitted to a part of the control bus 5B for the processor group that cannot respond at high speed. By transmitting the bus use permission signal 22, only the processor connected to the control bus 5B takes in the unit number 21 on the unit command bus 6 and compares it with the unit number of its own processor. The response signal 23 is returned to a part of the bus 5B.

Next, in the transfer cycle D, the data transfer source processor sends the unit number of the data transfer destination processor and the transfer command 24 to the unit command bus 6, and sends the data fetch instruction signal 25 to a part of the control bus 5B. Send out. This data capture instruction signal 2
5, only the processor connected to the control bus 5B fetches the destination processor unit number on the unit command bus 6 and compares it with the unit number of its own processor.
The transfer command is received, and a response signal 26 is returned to a part of the control bus 5B. Then, the processor 10 transfers the data to the data transfer destination processor. When the data transfer is completed, the processor 10 drops the bus reservation request signal 3.

When a processor having a different response speed from the above group is added, the system can be configured only by adding a control bus, so that an increase in signal lines between the processors can be minimized.

According to the present embodiment, a processor that requires a high-speed response can transfer data or a command regardless of the response speed of a processor that does not require a high-speed response. It can be used for

[0021]

As described above, according to the present invention, in a multiprocessor system, a processor group capable of high-speed response and a processor group not capable of high-speed response are grouped to provide a processor capable of high-speed response. Since the control bus for the group and the control bus for the processor group that cannot respond at high speed are provided, it is possible to transfer data or commands corresponding to the response speed of each group, and the processor capable of responding at high speed is provided. High-performance bus control can be performed without impairing responsiveness.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a bus control system according to an embodiment of the present invention.

FIG. 2 is a time chart of data transfer between processors.

FIG. 3 is a block diagram of a conventional bus control system.

FIG. 4 is a time chart of a conventional data transfer between processors.

FIG. 5 is a diagram illustrating a difference in response time from a processor.

[Explanation of symbols]

 1-4 bus securing request signal 5A, 5B control bus 6 unit command bus 7 bus arbiter 8-11 processor

Continuation of front page (56) References JP-A-57-60424 (JP, A) JP-A-62-286157 (JP, A) JP-A-2-12361 (JP, A) (58) Fields investigated (Int .Cl. ⁷ , DB name) G06F 13/38-13/42 G06F 15/16-15/177

Claims (1)

(57) [Claims] 1. A multiprocessor system comprising: a plurality of processors connected to a common bus; and a bus arbiter for arbitrating use of the common bus in response to a request for use of the common bus from the plurality of processors. The processor is divided into a processor group capable of high-speed response and a processor group not capable of high-speed response. Of the common bus, a bus related to the response speed is provided for each processor group. A bus control system, which is provided commonly for groups.