JPH0752978B2 - Call switch circuit - Google Patents

Description

The present invention relates to a speech switch circuit, and more particularly to a speech switch circuit for exchanging wide band / high speed signals.

[Prior Art] Conventionally, as this type of call switch circuit, for example, the one described in Minoru Akiyama “Modern Communication and Switching Engineering” published by Denki Shoin on page 252 is known.

FIG. 3 is a block diagram of a conventional exchange using a speech switch circuit.

According to FIG. 3, a switch using a call switch circuit according to the prior art has a multiplexer (MUX) 220 whose inputs are connected to incoming lines 221, 222, 223, 224, and an output of the multiplexer 220 is connected to an input through an incoming highway 110. A call switch circuit 210 that is a phase conversion unit, a demultiplexer (DEMUX) 230 in which an output of the call switch circuit 210 is connected to an input via an output highway 120, and a demultiplexer
It consists of outgoing lines 231, 232, 233, 234 connected to 230, a counter 240 whose output is connected to the control input of the multiplexer 220 and a counter 250 whose output is connected to the control input of the demultiplexer 230.

Here, for example, the incoming line 222 to the outgoing line 234, the incoming line 224 to the outgoing line 232
The case of connecting to will be described.

The incoming lines 221, 222, 22 of the multiplexer 220 shown in FIG.
Data D1, D2, D3, and D4 are respectively added as inputs to 3,224 from terminals not shown. Then multiplexer 2
20 is the time slot 261, 262, 2 on the input highway 110 in order according to the value output by the counter 240 for the data D1, D2, D3, D4.
63,264 time division multiplexed.

The call switch circuit 210 outputs the data D2 of the time slot 262 of the input highway 110 and the time slot of the output highway 120.
274, incoming highway 110 time slot 264 data D
Move 4 to each time slot 272 on exit highway 120.

The demultiplexer 230 uses the call switch circuit 210 to
The data D1, D2, D3, D4 input from the output highway 120 are distributed to the output lines 231, 232, 233, 234 in order by the output of the counter 250.

FIG. 4 is a block diagram showing the configuration of the call switch circuit 210 of FIG.

In the call switch circuit 210 of FIG. 3 shown in FIG. 4, the input is connected to the input highway 110 and the output is output to the highway 120.
, A control memory 212 whose input is connected to the counter 216 and whose output is connected to the output control input of the channel memory 211, and whose output is the input control input and control memory of the channel memory 211. It consists of a counter 216 connected to the output control input of 212.

According to FIG. 4, the demultiplexer 213 of the speech path memory 211
Writes the data D1, D2, D3, D4 in order to the memory cells 281, 282, 283, 284 in the speech path memory 211 according to the output of the counter 216.

On the other hand, addresses A1, A4, A3, A2 are written in the memory cells 291, 292, 293, 294 of the control memory 212 by a control system (not shown). In addition, the multiplexer 215 has a counter 216.
The address information A1, A4, A3, A2 of the memory cells 291, 292, 293, 294 is sequentially read according to the output of On the other hand, channel memory 2
The multiplexer 214 of 11 stores the data D of the memory cells 281,284,283,282 of the channel memory 211 according to the address information A1, A4, A3, A2 output from the multiplexer 215 of the control memory 212.
Read 1, D4, D3, D2.

Thus, on the output highway 120, the data D2 is phase-shifted to the time slot 274 and the data D4 is phase-shifted to the time slot 272, and the data D2 added to the input line 222 is output to the output line 234 and added to the input line 224. The obtained data D4 is output to the output line 232.

[Problems to be solved by the invention]

As described above, in the conventional call switch circuit,
It is necessary to store all the data for one frame in the speech path memory, and there is a drawback that a large amount of memory is required when constructing a speech switch circuit of high speed and large capacity.

An object of the present invention is to provide a speech switch circuit which does not have such drawbacks.

[Means for solving problems]

The call switch circuit of the present invention is a call switch circuit in which an input is connected to an input highway in which a plurality of signal multiplexing units are cascade-connected, and an output is connected to an output highway in which a plurality of signal separation units are cascade-connected. And a multiplexer having a plurality of memory cells to which addresses are written, and a multiplexer whose input is connected to each memory cell and which sequentially outputs the addresses written to the memory cells according to the output of the counter connected to the read address input. A memory and an address inserter for connecting the first input to the input highway, the second input to the output of the control memory, the output to the output highway, and switching between the first input and the second input. And the data input to the signal multiplex unit by each of the signal multiplex units and an address serving as an identifier of this data. Multiplexing on the input highway, outputting an address corresponding to a separating unit for separating each data on the input highway in the control memory, and outputting only an address part on the input highway in the address inserting unit from the control memory It is characterized in that the plurality of signal separation units separate only the data having the address matching the address given to each signal separation unit from the signals on the output highway.

[Action]

According to the present invention, data is exchanged by assigning an address to each of a plurality of time-division-multiplexed data and converting the address. As a result, a call switch circuit that does not require a call path memory can be obtained.

〔Example〕

 The call switch circuit of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an exchange using a call switch circuit according to an embodiment of the present invention.

According to FIG. 1, the exchange is connected to the incoming highway 110 by multiplex units 141, 142, 143 and 144, the incoming highway 110 to the input, and the outgoing highway 120 to the output, and the outgoing highway 120. It is composed of connected separating units 161, 162, 163, 164. The configuration of the call switch circuit 100 is shown in FIG.

An input line for inputting data and an address line for inputting an address are connected to each multiplexing unit. Further, an output line for outputting data and an address line for inputting an address are connected to each separating unit.

Here, for example, a case where the incoming line 136 of the multiplexing unit 142 is connected to the outgoing line 158 of the separating unit 164 and the incoming line 138 of the multiplexing unit 144 is connected to the outgoing line 156 of the separating unit 162 will be described.

Incoming lines 135, 13 of the multiplexing units 141, 142, 143, 144 shown in FIG.
Signals D and 6,137,138 from terminals not shown
1, D2, D3, D4 are added. Also, address lines 131, 132, 13
Addresses A1, A2, A3, and A4 are added to 3,134 from a control system (not shown).

The multiplexing unit 141 uses the address A1 input from the address line 131 in the address time slot 185 on the input highway 110 and the data input from the input line 135 in the data time slot 181.
D1 is multiplexed respectively.

Similarly, the multiplexers 142, 143, and 144 receive the address lines 1 in the address time slots 186, 187, 188 on the multiplexer input highway.
Addresses A2, A3, A4 input from 32, 133, 134 are multiplexed with data D2, D3, D4 input from incoming lines 136, 137, 138 in data time slots 182, 183, 184.

In the call switch circuit, the address added by the multiplexing circuits 141 to 144 is replaced to specify the separation unit that receives the data. That is, the call switch circuit is controlled by the control system (not shown) to control the incoming highway 110.
The address A2 of the upper address time slot 186 is converted into the address A4, the address A4 of the address time slot 188 is converted into the address A2, and the resultant is output to the output highway 120.

On the other hand, the address lines 151, 152, 15 of the separating units 161, 162, 163, 164
Addresses A1, A2, A3, A4 are added to 3,154 by a control system (not shown).

Separation units 161, 162, 163, 164 have addresses A1, A4, A3, of address time slots 195, 196, 197, 198 on the outgoing highway 120.
A2 is compared with the addresses A1, A2, A3, A4 input from the address lines 151, 152, 153, 154, respectively. Then, the separation unit 1
61, 162, 163, 164 are address time slots 195,
198, 197, 196 are detected to match addresses, data D1, D4, D3, D2 of data time slots 191, 194, 193, 192 are separated from outgoing highway 120, and outgoing lines 155, 156, 15 respectively.
Output to 7,158.

FIG. 2 is a block diagram showing the configuration of the call switch circuit 100 shown in FIG.

According to FIG. 2, the call switch circuit 100 of FIG. 1 includes an address insertion unit 104 having an input highway 110 connected to an input and an output highway 120 connected to an output, a counter 103,
The counter 103 comprises a control memory 105 connected to the read address input and the output connected to the input of the address insertion unit 104.

The memory cells 171, 172, 173, 174 of the control memory 105 have addresses A1, A4, A3, A respectively controlled by a control system (not shown).
2 is written.

The multiplexer 102 has addresses A1, A stored in the memory cells 171, 172, 173, 174 sequentially according to the output of the counter 103.
Outputs 4, A3, A2.

In the address insertion unit 104, the input highway 110 pushes the switch to the control memory 105 side only during the address time slot, and replaces the address on the input highway 110 with the one output from the control memory 105. As a result, the address insertion unit 104 rewrites the contents of the address time slots 185, 186, 187, 188 on the input highway 110 into the outputs A1, A4, A3, A2 of the control memory 105, and outputs them to the output highway 120.

Thus, the address A2 of the incoming address timeslot 186 will be the address A4 of the outgoing address timeslot 196.
In addition, the address A4 of the input address time slot 188 is converted into the address A2 of the output address time slot 198, the input line 136 of the multiplexing unit 142 to the output line 158 of the demultiplexing unit 164, and the multiplexing unit 144.
The incoming line 138 is connected to the outgoing line 156 of the separating unit 162.

〔The invention's effect〕

As described above, according to the present invention, signals can be exchanged without a speech path memory for storing one frame of signals, so that a large-capacity broadband / high-speed speech switch circuit can be easily realized. Is obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing an exchange using one embodiment of the present invention, FIG. 2 is a block diagram showing a configuration of a call switch circuit in FIG. 1, and FIG. 3 is a block diagram showing a conventional exchange. FIG. 4 is a block diagram showing a configuration of a call switch circuit in a conventional exchange. 100,210 …… Call switch circuit 102,214,215,220 …… Multiplexer 103,216,240,250 …… Counter 104 …… Address inserter 105,212 …… Control memory 141,142,143,144 …… Multiplexer 161,162,163,164 …… Separator 171,172,173,174,281,282,283,284,291,292,293,294…
… Memory cell 211 …… Channel memory 213,230 …… Demultiplexer

Claims (1)

[Claims] 1. A speech switch circuit having an input connected to an input highway in which a plurality of signal multiplexers are connected in cascade, and an output connected to an output highway in which a plurality of signal separators are connected in cascade. A plurality of memory cells to which are written, a control memory having an input connected to each memory cell, and a multiplexer that sequentially outputs the addresses written to the memory cells according to the output of the counter connected to the read address input, A first input connected to the input highway, a second input connected to the output of the control memory, an output connected to the output highway, and an address inserter for switching between the first input and the second input. , The data input to the signal multiplex unit by each of the signal multiplex units and an address serving as an identifier of this data are input to the input highway. A), outputs the address corresponding to the separation unit for separating each data on the input highway in the control memory, and replaces only the address part on the input highway with the information from the control memory in the address insertion unit. A call switch circuit, wherein in the plurality of signal separation units, only data having an address matching an address given to each signal separation unit is separated from signals on an output highway.