JPH0736781A - Method of cache management - Google Patents

Abstract

PURPOSE: To unnecessitate backup real storage with respect to a data logical view by controlling data mapped to a large virtual external address space or access to a page through a cache. CONSTITUTION: At the time of using the page, the page is mapped to a virtual external storage address(VESA) 25 and next mapped to the physical address 25 of an external storage. A reference page writes a VESA address 25 in the cache 27 to execute index by this. When a cache storing page is common with different logical views, the page is updated and in the other case, the page is copied to another cache location by different VESA.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer-managed storage, and more particularly to a method for managing a data cache portion of CPU external storage.

[0002]

2. Description of the Related Art Here, matters relating to the present invention regarding conventional computer technology will be briefly described. Topics covered include CPU operating system and resource managers in relation to staged internal / external storage, data cache and invalidation, demand page virtual store, virtual addressable cache, etc.

CPU and Staged Storage Modern data processing machines have a hierarchical structure, LRU.
It consists of an instruction processor connected to a staged storage (which stores software and data) managed by the (Least Recently Used) method. The fastest and fastest access storage is located closest to the instruction processor and at the top of the hierarchy. Slow storage (most of the information is written to it) occupies a low position in the hierarchy.

Storage increases cost significantly at higher speeds, and many computer systems divide the physical storage subsystem into several performance levels. Some of these levels are treated as peripheral I / O devices and are accessed through asynchronous paths (DASD, tape, etc.). Other levels (RAM, cache, etc.) are directly manipulated by the system hardware as part of internal storage and are accessed through the sync path.

"Internal storage" means that a part of the storage can be randomly accessed by one read / write operation (transfer). In the IBM system,
Internal storage is addressable byte by byte, except for extensions (“extended stores”). The extended store is randomly accessed with a block or page as an addressable unit (4096 bytes / page). The extended store is managed as a paging store based on LRU type real memory. "External storage" refers to the majority of storage that cannot be accessed randomly and must be accessed directly, as is the case with DASD.

An internal store is considered "synchronous" when the processor that references it is idle until a return is received. On the other hand, if the data to be sought exists in the external store (beyond the point called the "I / O boundary"), the referring processor will search and execute another task instead of waiting. Switching this task or process is dangerous. This is because the search path must be established for new data and the processing state of the previous task must be saved. When the search from the external storage is completed, there will be another CP
It is necessary to switch U to the previous process or task.

Cache and Cache Invalidation A "cache" is considered a collection of indexed, LRU-ordered pages in a buffer. Caches are usually placed on the path to data and instructions to reduce access time. In addition, “cache invalidation” refers to excluding or giving an instruction to the cache that the named page is invalid. This is because the base page was modified on another data path and the given cached version is no longer accurate. By the way, invalidation can be accomplished by leaving the cache in place or by marking the cache directory that the incorrect page is invalid.

CPU, Operating System, and Resource Manager A typical processor or CPU system, respectively, comprises an operating system, a processor internal memory, a local cache operatively formed, and a DAS.
Includes D-oriented external store, and lock / cache resource manager. The processes executed by the CPU perform read / write operations by the operating system. On the other hand, in read / write operations, cache /
A lock resource manager is used to establish a lockable access path in the directory for pages residing in the cache or refreshed from the external store to the cache.

Virtual Demand Paging Storage "Virtual storage" is an addressing of storage space that is significantly larger than that available in the CPU's internal storage. It takes advantage of locality of reference in both space and time. That is, the pattern in which a process refers to storage is non-uniform and tends to concentrate on a particular part. Therefore, a large amount of virtual storage can be backed up with very little real storage. The referenced data is swapped in from external storage if it is not available from internal storage.

In the virtual demand paging system, each process frequently references some subset of its virtual pages. The capacity for the system to manage pages is based on an upper bound on the number of slots or "page frames". That is, the page frame number is related to the amount of internal store set aside to support the page frame. A fault occurs when the sum of the subset of pages referenced by the process exceeds the number of page frames. “Fault”
Is synonymous with the fact that the referenced page does not exist in the internal store managed by the LRU method, and therefore the external storage needs to be accessed. The system in this state is said to be paging.

The Problem of Synonyms Ambiguity becomes a problem when two different names are used to refer to the same physical page, or when two different physical pages have the same name. These "synonyms" waste cache space and cause problems with cache invalidation. This is because caches usually have no way of associating many possible names for the same data.

Conventional Virtual Address Cache Woffinden et al., US Pat. No. 4,612,612, "Vir.
tually Addressed Cache "(published September 16, 1986) attempts to treat a cache as a virtual addressable entity, that is, the original virtual address is obtained and cached based on that address. In the book, TLB (Translation L
The virtual-to-real address translation performed immediately by the ook-aside Buffer) is not mentioned, but this translation operation facilitates cache lookups,
As is known from the past.

[0013] A drawback of the specification is related to the inherent difficulty of sharing a page. However, each page is treated individually because the page is cached by its virtual address. This is two virtual pages
It occurs even if an address references the same final address in real storage. Further, it is expected to some extent that virtual addresses in different address spaces can be mapped (hashable) to the same real address.

Files and Views A "data file" is a linear space of pages mapped into virtual frames. Real frame is external store DA
Stored in SD. Having multiple versions of a file (more precisely, multiple "views") often leads to "synonym problems". Also, a file version or view must have at least one page
A file that is common to another file version / view. Again, a version is a different view (view) of the same, self-explanatory, file, and the difference corresponds to the moment.

[0015]

SUMMARY OF THE INVENTION It is an object of the present invention to manage access to data or pages that map to a very large virtual external address space through a cache while not disturbing the logical view of the data. The idea is to devise a method that does not require assigning a backup physical store or real store to a view.

[0016]

SUMMARY OF THE INVENTION In the method of the present invention, to avoid both the synonym problem and multiple page copies common to different logical views (page organization files) for pages in a cache, Two levels of address indirection are used. The page is
When used, first of all, VESA (Virtual External S
torage address) and then referenced according to that address in linear space, which is then mapped to the physical address of the external storage. Also, the referenced page is
The VESA address is written to the cache as an indexing argument. That is, pages are written to the cache and indexed (ordered) by their VESA address. Therefore, multiple views can be formed by combining the names (VESA addresses). This eliminates the need to duplicate the common page and merge the copies into a view.

What is important here is that if a page stored in the cache is common to different logical views, it will be updated on the fly. In other cases,
Such pages are copied to different cache locations using different VESAs as shadows. Updating a common page on the fly to different logical views (collection of pages) reduces cache usage.

The method of the present invention is based on the previously drawn Woffinden.
In contrast to that patent, another indirection layer (VESA) is used. That is, the page is indexed in the cache by its VESA argument to avoid synonym conflicts. Therefore, the mapping to the external storage via the conversion from the logical address to the VESA and the VESA to the real address is required.

The advantages of the method of the present invention are as follows:
(A) Unique names are generated for caching, synonyms are avoided, (b) Unique names are used for locking, (c) Data is cached and written out only after modification, and (D) When the location of data in the real storage changes, the logical address remains the same (invariant), so the cache is not invalidated,
(E) No physical backup is needed for virtual files.

[0020]

【Example】

Host CPU Environment for Implementing the Method of the Present Invention The present invention provides an IBM operating system MVS.
IBM / 360 or 370 architecture C using
It can be conveniently implemented on a general-purpose computer such as a PU. I
For more information on the BM / 360 architecture CPU,
U.S. Pat. No. 3,400,371 to Amdahl et al. "Da
See "ta Processing System" (published September 3, 1968).

The operating system MVS is described in IBM Publications GC28-1150, "MVS /
Extended Architecture System Programming Library: S
ystem Macros and Facilities ”, Vol. 1. Details of standard MVS and other operating system services such as lock management, subsystem startup by interrupts or monitors, and task posting / waiting are covered. No. The evaluation of these operating system services appears to be stable among those skilled in the art.

Relationship of CPU, Cache, and Storage For purposes of this invention, a page is made up of a fixed number of page bytes (such as 4096). "Page" is synonymous with "block".

FIG. 1 shows the relationship between organized storage and CPUs. As shown in the figure, the CPU 1 accesses both the internal storage 3 and the external storage 5 through the paths 11 and 13. The internal storage 3 is a processor
It includes storage 2 (its contents are byte address and random addressable) and expanded storage 4 (its contents are page address and random addressable).
The external storage 5 includes DASD, and stores pages of data referred to by an application executed on the CPU 1.

To give a typical example, the application that started the CPU processor refers to the page by its virtual / linear space address or real space address to the cache. In that case, the cache 9 can be realized by hardware or software. In the case of software, the cache can be placed in any part of the internal storage 3. Expanded storage 4 if page is not available in cache 9
Alternatively, it is necessary to access the external storage 5.

If multiple pages are accessed at the I / O boundary 7 of the external storage, the pages may be accessed by Luiz et al., US Pat. No. 4,207,609, "Path Indepen."
dentDevice Reservation and Reconnection in a Multi
-CPU and Shared Device Access System ”(issued on June 10, 1980). By the way, when the internal storage is accessed,
The processor waits until the access is completed. When an access is made on an I / O boundary, the processor launches another task or process while waiting for the fetch (access) to finish.

Address Translation and Cache Allocation FIG. 2 illustrates the concepts of virtual / real address translation, associative memory assist, and cache allocation according to the present invention.

As shown in (1) of FIG. 2, the conversion from the virtual address to the real address is usually realized by hardware or high-speed microcode, and involves address conversion or mapping. That is, the address translation mechanism divides the virtual address into a page address and a relative page position in a typical machine IBM System / 370.

As mentioned above in connection with the description of demand paging, the internal storage set aside for paging is organized into fixed collections of pages called page frames. A page table can be used to associate a virtual address reference in a program with the real address of a page frame in internal storage. The effective page address can be confirmed by adding the relative address to the location of the page frame.
For more details, see “Operating Systems” by Lorin and Deitel (The Systems Programming Se
ries), which describes virtual storage, pp. 4 of Chapter 4. See 293-314.

FIG. 2B shows a TLB (Translation Lo).
The conventional method of speeding up virtual / real address translation using okaside buffer is shown. TLB15 is RAM
It is formed from (Random Access Memory) and operates as an LRU type associative memory. In this memory, the address of the accessed data is processed in parallel with the instruction decoded by the CPU.

As shown in (3) of FIG. 2, when the real cache 17 is placed in front of the real CPU main memory 19, the real cache 17 is placed in a page having a different virtual address and a different virtual address space. It can store torn pages. However, as a drawback of this real cache, access to the cache only occurs after the virtual / real address translation has been performed. In the real cache, the address lookup is performed first and then the table lookup occurs.

FIG. 3 shows a state in which the virtual cache 21 is arranged in front of the address translation and real internal storage 19.
This configuration is patterned with the hardware cache embodiment found in the Woffinden patent referenced above.
The following is an explanation of Woffinden.

"A typical buffer always contains a very small portion of the main store data. In a virtual address buffer, the location of the data is not a function of the real address of the main store, but a function of the virtual address. Therefore, the main store address is not mapped to a unique buffer address: two real addresses are stored in the same virtual address location in the buffer.
You can convert more than one. "

For the problem of synonyms, Woffinden's solution is simply stated as follows.

"One real address in the main store
The same data location corresponding to the location
Virtual address buffers may store more than one copy of the same data (referred to as synonyms) at different locations, as they may be addressed by different virtual addresses. So the real / virtual address translator translates the real address of the main store into all virtual addresses of the buffer when the modified data is stored in the buffer, in order to find the synonyms that exist in the buffer. . "

Cache Arrangement According to the Present Invention In the method of the present invention, the cache is a part of the internal storage that is generated and managed by software. This cache acts as an external storage cache. In addition, such a software cache operates differently from the hardware configuration of the CPU cache described in the Woffinden patent. Woffinden's C
In the PU cache, address derivation and access is in microseconds, while external storage software cache derivation and access is in milliseconds. As a result, it becomes possible to add or improve the processing.

FIG. 4 illustrates software caching according to the present invention and its placement. It shows two address translations, two levels of indirection. The first level is VE of virtual address or logical address 23.
The mapping to the SA (Virtual External Storage Address) space 25, and the second level is the mapping of the VESA to the external storage real address 5. Cache 2
Access to 7 is via VESA arguments only.
The cache 27 is positioned after the first mapping and before the second mapping.

Avoiding Synonyms Using VESA Ordered Pairs By employing two levels of indirection in the method of the present invention, the properties of base + displacement addressing described in conjunction with demand paging and virtual addressing are exploited. Here, consider a case where the application executed by the CPU 1 specifies the 100th relative page. If the page has multiple versions, the logical address for each version is the same. These are different versions of the same file.

In the present invention, the namespace to intermediate space mapping is from plural to singular. Therefore, two linear spaces sharing the same page have one V
Mapped to ESA (Virtual External Storage Address), the problem of synonyms does not occur. The use of intermediate external storage avoids the synonym problem.

FIG. 5 shows two versions of the same file and the external virtual cache 27. First file 2 in the figure
9 has a logical name AV1 (file A version 1). It consists of original pages 0 and 1. The second file 31 has the logical name AV2 (file A version 2). AV2 includes original page 0 and modified page 1 (page 1 '). Pages 0, 1, 1'are VES
A address (so-called virtual frame) VF0, VF1,
Maps to VF2. Only one copy of page 0 needs to be stored in cache 27.

In-Situ Update and Shadow Copy According to the method of the present invention, the common page is updated in-situ in response to an in-situ writing of a common page to the original file and the updated file. . This allows
You can use the updated values in any file (view). If the page to be written or updated is not common, then its shadow copy is written to cache and another external storage logical space is allocated to it.

FIG. 6 shows the different storage mixes in the files AV1, AV2 and the cache 27. Here, it is assumed that AV1 includes original page 0 and original page 1. AV2 is original page 0 and changed page 1 '
Is included. The manager of the cache 27 is VESA
Address VF0 to page 0, VF1 to page 1, V
Assign F2 'to page 1'. When an application updates page 0, an in-situ update occurs at VF0 because page 0 is common to AV1 and AV2. However, to update to page 1 ′, the changed page 1 ″ is written to the VESA address in the cache VF2 ″ and the old page 1 ′ is written to the cache VESA address V.
It is processed by leaving a shadow on F2 '.

Algorithmic Representation of Method Using Another Example FIG. 7 shows a double mapping of pages from files 1, 2 to VESA ordered cache and internal or external real storage. Here we consider as follows.

The initial state of the system is assumed to include a file 1 consisting of pages 1 and 2. Also, pages 1 and 2 are V
The ESA addresses VF12 and VF40 are mapped, and then the real addresses R2 and R96 are mapped. Next, assume that file 2 is first generated as an image of file 1. The first concordance on pages 1 and 2 is V
Includes F12 and VF40. The second concordance is R2,
Includes R96.

In order for page 2 of file 2 to be updated without sharing with file 1, first a new VESA
That is, it is necessary to allocate the VF 76 to the cache 27. The concordance or page map of File 2 is then changed. The updated page 2'is then written to cache location VF76. Real storage in the form of DASD locations or R102 is allocated and page 2'is copied here. By the way, VF40 remains as a shadow location for VF76.

When page 1 is written again, it is cached because it is shared between files.
No new assignment to 7 is required. The existing mapping to VF12 remains the same and the updated page 1'is written there. Similarly, the contents of VF12 are DAS
Copied to the real location R2 of D.

If changes to the cache 27 can be batched to the point where the cache is full, DASD
Transfer to real storage can be done once. As a result, the transfer efficiency is improved compared to the case where the backup individual store is updated a plurality of times.

When the file 1 is deleted before the writing (for example, the file 1 is a temporary file), the virtual frame which is its constituent element is never allocated to the real storage. Allocation to real storage is required only when the frame is actually written (there is no need for it because it is in the cache).

[0048]

As described above, according to the present invention, the synonyms at the time of caching are avoided, and the physical backup for virtual files becomes unnecessary.

[Brief description of drawings]

FIG. 1 shows the organization of storage associated with a large mainframe CPU.

FIG. 2 is a diagram showing the concept of virtual / real address conversion, associative memory assist, and cache arrangement according to the present invention.

FIG. 3 is a diagram showing a concept of virtual caching according to a conventional technique.

FIG. 4 is a diagram showing software caching and its arrangement according to the present invention.

FIG. 5 illustrates a method for avoiding synonym problems using VESA ordered pages of the cache in accordance with the present invention.

FIG. 6 is a diagram showing in-situ update and shadow copy.

FIG. 7 shows another example mapping with different views according to the present invention.

Front Page Continuation (72) Inventor George Eisenberger 54 Albemarle Road, White Plains, New York, USA (72) Inventor Alexander Stafford Let 402 McGregor Drive, Mahopak, NY, USA ( 72) Inventor Gems Joseph Mayaz, San Francisco, California, Columbus Avenue, No. 6, 950 (72) Inventor William Harold Terrafu, Mount Kisco, New York, United States 37, Fox Den Road (72) Inventor Jay Harold Anger, Knorrwood Court, Morgan Lake, New York, USA (without street number)

Claims (6)

[Claims] 1. A data view that does not disturb the logical view of the data and does not require any backup storage to be allocated to it.
A CPU-implemented method of accessing a page through a cache, wherein the logical view is in the form of at least a first and a second page organization file, the CPU being an operating system, a RAM-addressable page. An internal storage including a data cache formed from the external storage, an external storage formed from DASD addressable pages, and means for responding to a read / write operation of the CPU to access the internal / external storage, Address of a page of a first or second file in linear space that is first mapped to an external storage virtual address (VESA) and then to a physical address of the external storage in response to a CPU read / write operation. And refer to the address according to , If not located in the data cache, then writing the VESA address to the data cache as an indexing argument, and in response to the CPU write operation, a cache common to the first and second files. Update the page on the fly, otherwise update the updated page to another VESA
Copying to another cache location using an address. 2. The page access method according to claim 1, including the step of writing a page from a data cache to a physical address of an external storage only after modification. 3. The method according to claim 1, wherein when a physical address of a page in the external storage is changed,
A page access method that skips invalidating pages in the cache unless the VESA address changes. 4. A CPU-implemented method for managing a cache for external storage that includes data file versioning features and has first and second page organization files, the CPU comprising a RAM. Including internal storage formed from addressable pages and external storage formed from DASD addressable pages, (a) at least two named pages (AV1P
0, AV1P1) is created in a specified file, and device-independent locations are created in the external storage logical space (VF).
0, VF1), and (b) writing the page (AV1P0, AV1P1) into the cache and indexing the cache location of the page with the address (VF0, VF1) of the external storage logical space. , (C) the first and second
Pages not common to all files (AV2P0,
Allocating another external storage logical space (VF2 for AV2P1 ') in response to the AV2P1') and storing the updated page in a location of the other storage space in the cache, and (d) above. Responsive to updating the page common to the first and second files, updating the page in-place in the cache, otherwise writing its shadow copy to the cache,
Allocating another external storage logical space (VF2 ') thereto. 5. The method according to claim 4, wherein the space is allocated to an external storage and the updated page is copied to the space in response to the non-volatile cache, and (e) responding to the full cache. And a cache management method comprising forming a concordance between an external logical space location and a physical location in the external storage. 6. The method of claim 4, wherein the cache is a non-volatile cache selected from a set of addressable memories formed from bistable remanent magnetic material or bistable battery backup electrostatic material. Is a cache management method.