JP2618096B2 - Cache management method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage managed by a computer, and more particularly to a method of managing a data cache portion of an external storage of a CPU.

[0002]

2. Description of the Related Art Here, with respect to conventional computer technology, matters relating to the present invention will be briefly described. Topics include CPU operating systems and resource managers in relation to staged internal / external storage, data caches and invalidations, demand page virtual stores, virtual addressable caches, and the like.

CPUs and Staged Storage Modern data processing machines have a hierarchical configuration and LRU.
(Least Recently Used) It consists of an instruction processor connected to staged storage (stores software and data) managed by the method. The storage with the highest speed and the highest access speed is located closest to the instruction processor and at the top of the hierarchy. Slow storage (where most of the information is written) occupies a lower position in the hierarchy.

[0004] Because storage costs increase significantly with increasing speed, many computer systems divide the physical storage subsystem into several performance levels. Such levels include levels that are treated as peripheral I / O devices and are accessed through asynchronous paths (DASD, tape, etc.). Other levels (RAM, cache, etc.) are directly manipulated by system hardware as part of internal storage and are accessed through synchronization paths.

[0005] "Internal storage" means that a part of the storage can be randomly accessed by one read / write operation (transfer). In the IBM system,
Internal storage can be addressed in bytes, except for extensions ("extended stores"). The extended store is randomly accessed with a block or page as an addressable unit (4096 bytes / page). The extended store is managed as a paging store based on an LRU-based real memory. “External storage” refers to the majority of storage that cannot be accessed randomly and must be accessed directly, as in DASD.

[0006] An internal store is considered "synchronous" if the processor that references it is idle until a return is received. On the other hand, if the data to be sought is in an external store (beyond the point called "I / O boundary"), the referring processor searches for and executes another task instead of waiting. Switching this task or process is dangerous. This is because a search path must be established for new data, and the processing state of the previous task needs to be saved. When the search from the external storage is completed,
It is necessary to switch U to the previous process or task.

Cache and Cache Invalidation A "cache" is considered to be a collection of pages in a buffer that are indexed and arranged in LRU order. Caches are usually placed in the path to data and instructions to reduce access time. Further, "cache invalidation" refers to excluding from the cache or giving the cache an instruction that the named page is invalid. This is because the base page has been modified in another data path, and the version in the given cache is no longer accurate. Incidentally, invalidation can be accomplished by either leaving the cache intact, or by marking the cache directory with invalid pages as invalid.

CPU, Operating System, and Resource Manager A typical processor or CPU system is an operating system, a local cache operably formed from processor internal memory, a DAS, respectively.
Includes a D-oriented external store and lock / cache resource manager. A process executed by the CPU performs a read / write operation by an operating system. On the other hand, in the read / write operation, the cache /
A lock resource manager is used to establish a directory-lockable access path for pages that are in the cache or refreshed from the external store to the cache.

Virtual Demand Paging Storage “Virtual storage” is the addressing of storage space that is significantly larger than that available in the CPU's internal storage. It exploits the locality of reference in both space and time. That is, the pattern in which the process refers to the storage tends to be non-uniform and concentrated on a specific part. Therefore, a large-capacity virtual storage can be backed up with very few real storages. The referenced data is swapped in from external storage if it is not available from internal storage.

In a virtual demand paging system, each process frequently references a subset of its virtual pages. The capacity for the system to manage pages is determined based on the upper limit of the number of slots or “page frames”. That is, the number of page frames is related to the amount of internal store reserved to support page frames. A fault occurs when the sum of the subset of pages referenced by the process exceeds the number of page frames. “Fault”
Is synonymous with the fact that the referenced page does not exist in the internal store managed by the LRU method, so that it is necessary to access the external storage. The system in this state is said to be performing "paging".

Synonym Issues Ambiguity is a problem when two different names are used to refer to the same physical page, or when two different physical pages are given the same name. These "synonyms" waste cache space and create problems with cache invalidation. This is because caches usually do not have a way to associate many possible names for the same data.

Conventional Virtual Address Cache US Pat. No. 4,612,612 to Woffinden et al.
"Tually AddressedCache" (issued September 16, 1986) seeks to treat the cache as a virtual addressable entity, ie, the original virtual address is obtained and caching is performed based on that address. In the book, TLB (Translation L
Although the virtual / real address translation performed immediately by the ook-aside buffer is not mentioned, this translation operation facilitates cache lookup,
It is as conventionally known.

A drawback of the specification relates to the inherent difficulty in sharing pages. However, since pages are cached by their virtual address, each page is treated individually. This is two virtual pages
This occurs even if the address refers to the same final address in real storage. There is some expectation that virtual addresses in different address spaces can be mapped to the same real address (possible hashing).

Files and Views A "data file" is a linear space of pages mapped to a virtual frame. Actual frame is external store DA
Stored in SD. If a file has multiple versions (more precisely, multiple “views”), “synonym problems” often occur. Also, the version or view of the file, at least one page,
A file that is common to another file version / view. Again, a version is a view of the same, immediately recognizable file from different angles (views), the differences corresponding to the moment.

[0015]

SUMMARY OF THE INVENTION It is an object of the present invention to manage access to data or pages mapped to a very large virtual external address space through a cache without disturbing the logical view of the data. The idea is to devise a method that does not require a backup physical or real store to be assigned to a view.

[0016]

SUMMARY OF THE INVENTION In order to avoid both the problem of synonyms common to different logical views (page organization files) for pages in a cache and multiple page copies, the method of the present invention comprises: Two levels of address indirection are used. The page is
When used, first, VESA (Virtual External S
torage Address) and then referenced according to its address in linear space which is mapped to the physical address of the external storage. Also, the referenced page is
The VESA address is written to the cache as an indexing argument. That is, pages are written to the cache and indexed (ordered) by their VESA address. Therefore, a plurality of views can be formed by combining names (VESA addresses). This eliminates the need to duplicate the common page and combine that copy into the view.

What is important here is that if a page stored in the cache is common to different logical views, the page is updated on the fly. In other cases,
Such pages are copied to different cache locations using different VESAs as shadows. Updating a page common to different logical views (collections of pages) on the fly reduces cache utilization.

The method of the present invention is described in Woffinden,
Use another indirection layer (VESA), in contrast to the US Pat. That is, the page is indexed in the cache by its VESA argument to avoid synonym conflicts. Therefore, mapping from the logical address to the VESA and from the VESA to the real address via external storage is required.

The advantages of the method of the present invention include:
(A) a unique name is generated for caching and synonyms are avoided; (b) a unique name is used for locking; (c) data is cached and written out only after modification; and (D) When the location of data in the real storage changes, the cache is not invalidated because the logical address remains the same (unchanged),
(E) No physical backup for virtual files is required.

[0020]

【Example】

The present invention relates to a host CPU environment for implementing the method of the present invention.
/ 360 or 370 architecture C using
It can be conveniently implemented on a general-purpose computer such as a PU. I
For details on the BM / 360 architecture CPU,
U.S. Pat. No. 3,400,371 to Amdahl et al.
ta Processing System "(issued September 3, 1968).

The operating system MVS is described in IBM Publications GC28-1150, “MVS /
Extended Architecture System Programming Library: S
ystem Macros and Facilities ”, Vol. 1. Details of standard MVS and other operating system services such as lock management, activation of subsystems by interrupts or monitors, posting / waiting of tasks, etc. are mentioned. The evaluation of such operating system services appears to be stable among those skilled in the art.

Relationship Between CPU, Cache, and Storage For the purposes of this invention, a page is made up of a fixed number of page bytes (eg, 4096). “Page” is synonymous with “block”.

FIG. 1 shows the relationship between the organized storage and the CPU. As shown in the figure, the CPU 1 accesses both the internal storage 3 and the external storage 5 through the paths 11 and 13. The internal storage 3 is a processor
It includes storage 2 (its contents are byte addressable and random addressable) and extended storage 4 (its contents are page addressable and random addressable).
The external storage 5 includes a DASD and stores a page of data referred to by an application executed on the CPU 1.

As a typical example, the application that started the CPU processor refers to the page by its virtual / linear space address or real space address to the cache. In that case, the cache 9 can be realized by hardware or software. In the case of software, the cache can be placed at any part in the internal storage 3. If the page cannot be used in the cache 9, the extended storage 4
Alternatively, it is necessary to access the external storage 5.

If a plurality of pages are accessed at the I / O boundary 7 of the external storage, the pages are referred to by Luiz et al., US Pat. No. 4,207,609, “Path Indepen.
dentDevice Reservation and Reconnection in a Multi
-CPU and Shared Device Access System "(issued on June 10, 1980). By the way, when the internal storage is accessed,
The processor waits until the access ends. When an access is made at an I / O boundary, the processor activates another task or process while waiting for the fetch (access) to finish.

Address Translation and Cache Placement FIG. 2 illustrates the concept of virtual / real address translation, associative memory assist, and cache placement according to the present invention.

As shown in FIG. 2A, the conversion from a virtual address to a real address is usually realized by hardware or high-speed microcode, and involves address conversion or mapping. That is, the address translation mechanism divides a virtual address into a page address and a relative page position in a typical machine IBM System / 370.

As mentioned earlier in connection with the description of demand paging, the internal storage reserved for paging is organized into fixed collections of pages called page frames. A page table can be used to associate a virtual address reference in a program with the real address of a page frame in internal storage. The effective page address can be confirmed by adding the relative address to the location of the page frame.
See “Operating Systems” by Lorin and Deitel (The Systems Programming Se
ries) in Chapter 4, which describes virtual storage. 293-314.

FIG. 2B shows a TLB (Translation Lo).
A conventional method for speeding up virtual / real address translation using an okaside buffer is shown. TLB15 is RAM
(Random Access Memory) and operates as an LRU-type associative memory. In this memory, the address of the accessed data is processed in parallel with the instruction decoded by the CPU.

As shown in FIG. 2C, when the real cache 17 is placed in front of the real CPU main memory 19, the real cache 17 is placed in a page having a different virtual address and a different virtual address space. Can store stored pages. However, a disadvantage of this real cache is that access to the cache only occurs after virtual / real address translation has been performed. In a real cache, an address translation is first performed and then a table lookup occurs.

FIG. 3 shows a state where the virtual cache 21 is arranged before the address translation and the real internal storage 19.
This configuration is patterned in the hardware cache embodiment found in the aforementioned Woffinden patent.
The following is a quote from Woffinden.

"A typical buffer always contains a very small portion of the main store data. In a virtual address buffer, the location of the data is not a function of the main store real address, but a function of the virtual address. Therefore, the main store address is not mapped to a unique buffer address. The same virtual address location in the buffer has a real address of 2
You can convert more than one. "

For the problem of synonyms, Woffinden's solution is briefly described as follows.

"One real address in the main store
The same data location corresponding to the location
Because they may be specified by different virtual addresses, the virtual address buffer may store more than one copy of the same data at different locations (referred to as synonyms). Thus, the real / virtual address translator translates the real address of the main store to all the virtual addresses of the buffer to find synonyms present in the buffer when the changed data is stored in the buffer. . "

Cache Arrangement According to the Present Invention In the method of the present invention, a cache is a portion of the internal storage that is created and managed by software. This cache functions as an external storage cache. Also, such a software cache is different in operation from the hardware configuration of the CPU cache described in the Woffinden patent. Woffinden C
In PU caches, address derivation and access is in microseconds, whereas external storage software cache derivation and access is in milliseconds. This makes it possible to add or enhance processing.

FIG. 4 illustrates software caching and its arrangement according to the present invention. Two address translations, ie, two levels of indirection, are shown. The first level is the virtual or logical address 23 of the VE
The mapping to the SA (Virtual External Storage Address) space 25, and the second level is the mapping of the VESA to the external storage real address 5. Cache 2
Access to 7 is by VESA argument only.
The cache 27 is located after the first mapping and before the second mapping.

Avoiding Synonyms Using VESA Ordered Pairs Employing two levels of indirection in the method of the present invention takes advantage of the characteristics of base + displacement addressing described in conjunction with demand paging and virtual addressing. Here, it is assumed that the application executed by the CPU 1 specifies the 100th relative page. If the page has multiple versions, the logical address of each version is the same. These are different versions of the same file.

In the present invention, the mapping from the namespace to the intermediate space is that of plural to singular. Therefore, two linear spaces that share the same page are one V
It is mapped to ESA (Virtual External Storage Address), and the problem of synonyms does not occur. Using an intermediate external storage avoids the problem of synonyms.

FIG. 5 shows two versions of the same file and the external virtual cache 27. First file 2 in the figure
9 has a logical name AV1 (file A version 1). It consists of the original pages 0 and 1. The second file 31 has a logical name AV2 (file A version 2). AV2 includes the original page 0 and the changed page 1 (page 1 '). Pages 0, 1, 1 'are each VES
A addresses (so-called virtual frames) VF0, VF1,
Maps to VF2. Only one copy of page 0 needs to be stored in cache 27.

In-Place Update and Shadow Copy In accordance with the method of the present invention, a common page is updated in-place in response to an in-place write operation of a common page to the original and updated files. . This allows
The updated values can be used in any file (view). If the page to be written or updated is not common, its shadow copy is written to the cache, which is allocated another external storage logical space.

FIG. 6 shows the different storage mixes in files AV1, AV2 and cache 27. Here, it is assumed that AV1 includes original page 0 and original page 1. AV2 is the original page 0 and the changed page 1 '
Is assumed to be included. The manager of the cache 27 is VESA
Address VF0 to page 0, VF1 to page 1, V
F2 'is assigned to page 1'. When the application updates page 0, an in-place update occurs at VF0 because page 0 is common to AV1 and AV2. However, to update to page 1 ', the changed page 1 "is written to the VESA address in VF2" of the cache, and the old page 1' is written to the VESA address V
It is processed by leaving it as a shadow in F2 '.

Algorithmic Representation of the Method Using Another Example FIG. 7 shows the double mapping of pages from files 1 and 2 to the VESA ordered cache and internal or external real storage. Here, we think as follows.

It is assumed that the initial state of the system includes a file 1 composed of pages 1 and 2. Pages 1 and 2 are V
It is mapped to ESA addresses VF12, VF40 and then to real addresses R2, R96. Next, assume that file 2 is initially generated as an image of file 1. The first concordance on pages 1 and 2 is V
F12 and VF40. The second concordance is R2,
R96.

In order for page 2 of file 2 to be updated without sharing with file 1, first a new VESA
That is, it is necessary to allocate the VF 76 to the cache 27. Then, the concordance of file 2, that is, the page map is changed. Thereafter, the updated page 2 'is written to the cache location VF76. Real storage in the form of a DASD location or R102 is allocated and page 2 'is copied here. Incidentally, VF40 remains as a shadow location for VF76.

When page 1 is written again, the page is shared between files, so cache 2
No new assignment to 7 is needed. The existing mapping to VF12 remains the same, and the updated page 1 'is written there. Similarly, the contents of VF12 are DAS
D is copied to the real location R2.

If changes to the cache 27 can be batch processed to the point where the cache is full, the DASD
The transfer to the real storage can be performed once. As a result, the transfer efficiency is increased as compared with the case where the backup individual store is updated a plurality of times.

When the file 1 is deleted before the writing (for example, when the file 1 is a temporary file), the virtual frame which is the constituent element is never assigned to the real storage. It is only necessary to allocate real storage when the frame is actually written (it is not necessary because the frame exists in the cache).

[0048]

As described above, according to the present invention, synonyms during caching are avoided, and a physical backup for a virtual file is not required.

[Brief description of the drawings]

FIG. 1 is a diagram showing the organization of storage related to a large mainframe CPU.

FIG. 2 is a diagram showing the concept of virtual / real address conversion, associative memory assist, and cache arrangement according to the present invention.

FIG. 3 is a diagram illustrating a concept of virtual caching according to a conventional technique.

FIG. 4 is a diagram showing software caching and its arrangement according to the present invention.

FIG. 5 illustrates how to use the VESA ordered pages of the cache to avoid synonym problems in accordance with the present invention.

FIG. 6 is a diagram illustrating in-place updating and shadow copying.

FIG. 7 shows another example of mapping with different views according to the present invention.

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor George Eisenberger Albamar Road, White Plains, NY, USA 54 (72) Alexander Stafford Let, Inventor McGregor Drive, Mahopak, NY, USA 402 (72) Inventor Gems Joseph Myers San Francisco, California, United States, Columbus Avenue, No. 6, 950 (72) Inventor William Harold Tallahu, Fox Den Lord, Mount Kisco, NY, United States No. 37 (72) Inventor Jay Harold Anger New York, USA Morgan Lake, Knorrwood Court (no address) (56) References JP-A 64-18859 (JP, A) JP-A 1-239654 (JP, A)

Claims (3)

(57) [Claims] Claims: 1. A data view without disturbing a logical view of data and without having to allocate backup storage to it.
A method implemented in a CPU for accessing a page through a cache, wherein the logical view is in the form of at least a first and a second page organization file, the CPU comprising an operating system, a RAM addressable page. An internal storage, including a data cache formed from an external storage formed from DASD addressable pages, and means responsive to a read / write operation of the CPU to access the internal / external storage; In response to a CPU read / write operation, the address of a page of the first or second file in linear space that is first mapped to an external storage virtual address (VESA) and then mapped to a physical address of the external storage. Refer to the address according to Writing the VESA as an indexing argument to the data cache if the page write has not already been placed in the data cache; If the CPU write operation is not common to the first and second files, update the page placed in the cache directly.
Copying the updated page to another cache location using another VESA. 2. A method according to claim 1, further comprising the step of writing the page from the data cache to a physical address of the external storage only after the change. 3. A method implemented by a CPU for managing a cache for external storage having first and second page organization files including version information of a data file, the CPU comprising: An internal storage formed from possible pages and an external storage formed from DASD-addressable pages, (a) at least two named pages (AV1P0,
(AV1P1) in a predetermined file and assigning its location to an external storage logical space (VF0, VF1) independent of the file; (b) writing the page (AV1P0, AV1P1) in a cache, The address of the external storage logical space (VF
0, VF1); and (c) allocating another external storage logical space (VF2) in response to a page update (AV2P1 ′) not common to said first and second files; Storing the updated page at a location in said separate storage space in a cache; and (d) renewing said page on said cache in response to updating a page common to said first and second files. Updates directly and caches the shadow copy (VF) in response to the non-common page update (AV2P1 '').
2 ') and assigning another external storage logical space (VF2'') to the cache.