JPH0736154B2 - Data storage - Google Patents

Description

The present invention relates to a data storage device used for data storage in a computer system, and more particularly to a system for controlling the device itself by a microprogram type sequence control circuit. The present invention relates to a data storage device used.

[Conventional technology]

A control circuit in a conventional data storage device (device) has been configured by a very complicated hardware circuit that has various logic circuit elements such as an AND gate, an OR gate, and a flip-flop. The control information is stored in a memory, and the control information is taken out to a register circuit in synchronization with a clock signal. The so-called micro-addresser specifies the address corresponding to the control information of the next step of the memory circuit according to the taken control information and the state of the external signal. Program-based sequence control circuits are being used.

The sequence control circuit of such a system can perform extremely complicated control as long as the capacity of the memory is allowed. On the other hand, when the data storage device by the complicated control is used in an actual computer system, In the evaluation process of the device described above, there often occurs a situation in which a control operation that has not been exposed occurs and the control operation must be changed. Even in such a case, the device adopting the micro-program type sequence control circuit does not require modification of the circuit itself like the hardware circuit type device, and the control information is read out. It has the advantage of updating the contents of the dedicated memory (ROM). However, it is very difficult to replace a new ROM in which the contents of the control information have been updated with respect to the devices that are in large numbers in the users, and therefore it is difficult to make a quick improvement, and a large amount of expense is required. There is.

[Problems to be Solved by the Invention]

Problems to be solved by the present invention, in other words, the object of the present invention is to eliminate the drawbacks of the conventional data storage device as described above, and to cause a problem in the control operation due to a design error in the place of use. Even when the user has to change the control operation, the ROM provided in the memory content initialization circuit that is not used during the operation of the device is rewritable type and the data signal and the control signal between the host device and When the interface control circuit that is transmitting and receiving receives the control information rewriting command from the host device, it sends the rewriting address, the rewriting data, the rewriting address switching signal, and the rewriting instruction signal to the memory content initializing circuit,
By making it possible to rewrite the contents of the ROM in the memory content initialization circuit, the control information in the memory content initialization circuit can be changed quickly from the host device, and the modification cost can be saved. It is to provide a data storage device capable of performing.

[Means for Solving the Problems]

A data storage device according to the present invention includes an address switching signal, a load address signal, and load data for sequentially writing control information stored in advance in a rewritable read-only memory to a memory circuit in a sequence control circuit in response to a power-on signal. And a memory content initialization circuit for sending a signal to the sequence control circuit, and the control information sent from the memory content initialization circuit is stored in the memory and taken out to a register circuit in synchronization with a clock. According to the control information and the state of the interface information signal input from the interface control circuit, the operation of the interface control circuit is instructed and the address of the control information of the next step of the memory circuit is determined. Data communication between the sequence control circuit and the host device And a control signal is transmitted and received and a control information rewriting command is input from the host device, the rewriting address, the rewriting data, the rewriting address switching signal, and the rewriting instruction signal are controlled according to the control of the sequence control circuit. And the interface control circuit for rewriting the contents of the rewritable read-only memory.

〔Example〕

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

In FIG. 1, when the power-on signal 4 is activated when the power is turned on, the memory content initialization circuit 1 loads the control information stored in advance in the built-in rewritable read-only memory (ROM) and loads the control information. Address switching signal 5 and load address signal 7 as data signal 8
And the load signal 6 are sequentially output. The sequence control circuit 2 switches the address of the built-in memory circuit to the address specified by the load address signal by the input address switching signal 5, and sequentially writes the load data signal 8 as control information to the memory circuit by the load signal. I'm going. When this writing operation is completed, the address switching signal 5 becomes inactive and returns to the normal use state, and the interface information signal input from the interface control circuit 3 while taking out the control information in the memory circuit in synchronization with the clock signal 9 Depending on the state of 10, an operation instruction signal 11 is sent to the interface control circuit 3 to instruct the operation appropriately. Interface control circuit 3
Is usually an interface data signal with the host device
Although the operation instruction and the data exchange are performed by the 16 and the interface control signal 17, when the control information rewriting command provided as one kind of the operation instruction is received, the rewriting address is received under the control of the sequence control circuit 2. 12, the rewriting data 13, the rewriting address switching signal 14 and the rewriting instruction signal 15 are sent to the memory content initial setting circuit 1 to rewrite the contents of the ROM.

FIG. 2 is a circuit diagram showing details of the memory content initializing circuit 1 of the embodiment shown in FIG.

In FIG. 2, since the memory load control circuit 21 sends the control information stored in the read-only memory (ROM) 23 to the sequence control circuit 2 when the power-on signal 4 becomes “1” when the power is turned on, The address switching signal 5 is activated, the load address signal 7 indicates the address to write the control information, and the load signal 6 indicates the write operation. At this time, since the rewrite address switching signal 14 is normally inactive,
The ROM address switching circuit 22 transfers the load address signal 7 to the ROM.
Therefore, the control information of the address designated by the load address signal 7 in the ROM 23 is transmitted as the load data signal 8. When the contents of the ROM 23 are rewritten according to the instruction from the interface control circuit 3, the rewriting address switching signal 14 is activated, then the rewriting address of the ROM 23 is designated by the rewriting address 12, and the rewriting data 3 is used. The control information to be used is instructed, the data 13 is instructed, and the rewrite instruction signal 15 is instructed to execute the write operation. In order to enable such rewriting, an electrically erasable ROM or the like is used as the ROM 23.

FIG. 3 is a circuit diagram showing details of the sequence control circuit 2 of the embodiment shown in FIG.

When the power is turned on, the power-on signal 4 becomes "1", so the memory address switching circuit 32 outputs the load address signal 7 as it is as the memory address signal 44. When the load signal 6 is input from the memory content initialization circuit 1 in this state, the control information designated by the load data signal 8 is written into the address (address) designated by the load address signal 7 of the memory circuit 33. When the write operation of the control information is completed, the address switching signal 5 becomes "0", and the normal use state is set. Therefore, the control information stored in the memory circuit 33 is output as the memory output signal 45, is taken into the register circuit 34 in synchronization with the clock signal 9, and is further input to the instruction judging circuit 35 as the judging condition signal 46. The instruction judging circuit 35 advances the control according to the state of the interface information signal 10. The control sequence at this time judges the state of the interface information signal 10 according to the condition of the judging condition signal 46 from the register circuit 34, and The process proceeds by determining the next address according to the selection signal 41. That is, the memory address selection circuit 31 has a counter that is reset when the power is turned on and incremented by the clock signal 9, and the next address selection signal 41 is "0".
, The output of that counter is the internal memory address signal
However, when the next address selection signal 41 becomes "1", the branch address bit 42 received from the register circuit 34 is output as the internal memory address signal 43. Further, during normal operation, the address switching signal 5 is "0", and the memory address switching circuit 32 outputs the internal memory address signal 43 as it is as the memory address signal 44. The contents of the memory circuit 33 stored in the address are used as the next control information. By continuing the above operation, the sequence control circuit 2 advances the control while detecting that the interface information signal 10 has reached the desired condition.

Thus, when the power is turned on, the sequence control circuit 2 transfers the contents of the ROM 23 of the memory content initialization circuit 1 to the memory circuit 33,
Normally, the content of the memory circuit 33 is used as control information for control, so that when the control information rewriting command is received from the host device, the control information in the memory content initializing circuit 1 can be rewritten. That is, while using the control information in the memory circuit 33, the same content as that is entered.
Rewriting the control information in the ROM23 means rewriting the control information stored by the user himself. Once the power is turned off and then turned on again, the control is performed by the rewritten control information. be able to.

〔The invention's effect〕

As described in detail above, the data storage device of the present invention is configured such that the control information stored in the memory circuit incorporated in the sequence control circuit advances the control sequence while controlling the control information in the ROM in the memory content initializing circuit. Since it is possible to rewrite, it is possible to control the operation of the device by the rewritten control information just by turning off the power and then turning it on again. Even if it has to be changed, there is an effect that the control of the operation of the device can be easily changed without physical modification, and the cost can be reduced.

[Brief description of drawings]

1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing details of a memory content initialization circuit of the embodiment of FIG. 1, and FIG. 3 is an order of the embodiment of FIG. It is a circuit diagram which shows the detail of a control circuit. 1 ... Memory content initial setting circuit, 2 ... Sequence control circuit,
3 ... Interface control circuit, 21 ... Memory load control circuit, 22 ... ROM address switching circuit, 23 ... ROM, 31 ...
… Memory address selection circuit, 32 …… Memory address switching circuit, 33 …… Memory circuit, 34 …… Register circuit, 35 ……
Instruction judgment circuit.

Claims (1)

[Claims] 1. An address switching signal, a load address signal, and a load data signal for sequentially writing control information stored in advance in a rewritable read-only memory by a power-on signal to a memory circuit in a sequence control circuit. A memory content initialization circuit for sending to the sequence control circuit,
Depending on the control information obtained by storing the control information sent from the memory content initialization circuit in the memory circuit and taking it out to the register circuit in synchronization with the clock, and the state of the interface information signal input from the interface control circuit. A data signal and a control signal between the microprogram type sequence control circuit for instructing the interface control circuit to operate and determining the address of the control information for the next step of the memory circuit, and the host device. When the control information rewriting command is input from the host device, the rewriting address, the rewriting data, the rewriting address switching signal, and the rewriting instruction signal are sent to the memory content initializing circuit under the control of the sequence control circuit. Write the contents of the rewritable read-only memory Data storage device, characterized in that it comprises a obtaining said interface control circuit.