JPH07325757A - Storage management device - Google Patents

Abstract

PURPOSE:To increase the address converting speed for a storage management device which switches the storage spaces. CONSTITUTION:A setting instruction given from a processor 100 is detected by a decoding circuit 211, and a flip-flop 241 is activated. When a memory access is instructed by the processor 100, a memory control circuit 251 gives some of addresses set on an address bus 130 to the address input of a memory cell 271. Furthermore the circuit 251 gives the data set on a data bus 120 to the data input of the cell 271 via a buffer circuit 261. If the flip-flop 241 is not activated yet, no access is given to the cell 271 even when a memory access instruction is given from the processor 100.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage management device,
In particular, the present invention relates to a storage management device that switches storage spaces.

[0002]

2. Description of the Related Art Conventionally, in this type of technology, in order to effectively use a limited storage space, a plurality of banks are prepared for an extended memory area and any one bank is allocated to this extended memory area. This substantially expands the usable memory space. For example, Japanese Patent Laid-Open No. 4-223
Japanese Patent No. 540 describes a technique of a memory management device that switches and allocates banks to an extended memory by setting a bank switching register through a setup menu when the system is activated.

Referring to FIG. 8, in the conventional address map, any one bank is allocated to the extended memory area. As a result, the same memory address space is used for different functions by allocating different expansion memories for each system to be started up.

[0004]

In the above-mentioned prior art,
The bank to be used in the bank switching register in order to select any one bank from a plurality of banks is set at system startup. Therefore, there is a problem that the address conversion to the real address is required every time the memory is accessed according to this setting. Further, since the bank to be allocated is one arbitrary bank, there is a problem that the use is limited. Further, since the bank is set when the system is activated, it is difficult to switch the bank at any time during system operation.

An object of the present invention is to speed up the processing associated with address conversion in a storage management device that switches storage spaces.

Another object of the present invention is to provide a storage management device capable of simultaneously activating a plurality of storage spaces.

Another object of the present invention is to provide a storage management device capable of switching the storage space at any time during system operation.

[0008]

In order to solve the above-mentioned problems, a storage management device of the present invention is connected to a plurality of storage devices allocated to the same address space, and accesses the connected storage devices. The setting as to whether or not to do so is stored, and access to the connected storage device is managed according to this setting.

Another storage management device of the present invention is connected to a plurality of storage devices allocated to the same address space, and an instruction circuit for indicating whether or not the connected storage devices can be accessed. An instruction setting circuit that sets in the instruction circuit whether or not to access the connected storage device, and an access to the connected storage device based on a value of the instruction circuit set by the instruction setting circuit. And an access control circuit for controlling.

Further, the access control circuit can access the connected storage device by the instruction circuit if the access is to the connected storage device when an access to the storage device occurs. It is possible to output the address related to the access to the storage device only when it is instructed.

Further, the access control circuit outputs a plurality of bank registers each holding an address in the connected storage device and one of the addresses held by the bank register to the storage device. And when access to the storage device occurs,
If this access is an access to the connected storage device and the instruction circuit indicates that the connected storage device is accessible, the bank register corresponding to the bank concerned is accessed. The address to be held may be output from the selector to the storage device.

Further, the storage management device of the present invention can be configured to simultaneously write to a plurality of storage devices assigned to the same address space.

The instruction circuit can be composed of a 1-bit flip-flop or a register.

The instruction setting circuit may include a decoder, and the instruction circuit may be configured to be set when a specific value is detected by the decoder.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a first embodiment of the storage management device of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, an information processing system which is a target of a storage management device according to a first embodiment of the present invention is a processing device 100 that executes a program and manages the system, and n memory boards 201 to 201. 20n is the control bus 11
0, the data bus 120, and the address bus 130 are connected.

Memory board 201 including a storage management device
Is a decode circuit 211 that decodes an address, a flip-flop 241 that indicates whether or not the memory board is activated, a receiver circuit 221 that transmits data on the data bus 120 to the flip-flop 241, and the negation of the logical product. A NAND circuit 231 that generates logic, a memory cell 271 that stores and reads data, a memory control circuit 251 that controls the timing of an address and data for the memory cell 271, and data on the data bus 120 is transmitted to the memory cell 271. The data buffer circuit 261 is included.

The memory cell 271 of the memory board 201 is activated by the designation from the processing device 100 as follows. First, the decode circuit 211 detects that it is an instruction to activate the memory board 201, and activates one input of the NAND circuit 231. The instruction to activate the memory board 201 is issued by the processing device 1
00 from the control bus 110. That is,
A "write" signal, which is one control signal of the control bus 110, is provided to one input of the NAND circuit 231 and the control signal input of the memory control circuit 251. As a result, the NAND circuit 2
Based on the control from 31, the flip-flop 241 takes in the data on the data bus 120. This flip-flop 241 is a 1-bit flip-flop, and a specific 1 bit of the data bus 120 having a plurality of bit widths is given via the receiver circuit 221. That is,
Each bit of the data bus 120 is connected to a different memory board, and is connected to a flip-flop in each memory board. The signal held by the flip-flop 241 is used as a control signal for the memory control circuit 251.

When a memory access is instructed by the processor 100, that is, when a "read" signal or a "write" signal is given via the control bus 110, the memory control circuit 251 is notified of that fact. Also, at this time,
When the flip-flop 241 is activated, the memory control circuit 251 applies a part of the address of the address bus 130 to the address input of the memory cell 271. further,
At this time, the memory control circuit 251 gives the data on the data bus 120 to the data input of the memory cell 271 via the data buffer circuit 261. In other words, the processing device 1
Memory access from memory cell 271 if the flip-flop 241 is not activated even if the memory access is instructed from 00.
Access is not generated.

Referring to FIG. 2, the address map in the storage management device of the first embodiment of the present invention has an area of main memory B in addition to an area of main memory A. The substance of the area of the main memory B is a local memory divided into n windows. That is, of the n windows each having the same memory capacity as the main memory B, an arbitrary window is assigned as the main memory B. This window has the same memory capacity as the memory cell of each memory board. Therefore, since the flip-flop 241 is provided for each window, at least one arbitrary window can be activated in units of windows.

Referring to FIGS. 1 and 3, the processing apparatus 1
The procedure for giving an instruction from 00 to the memory board group is as follows. The processing device 100 first sets an address to be accessed in the address register AX,
Next, data is set in the data register DX. afterwards,
The processing device 100 accesses a predetermined address by issuing an access command. For example,
The instruction for activating the flip-flop 241 is as follows. First, the processing device 100 has the address “B0004 assigned to the flip-flop 241.
(Hexadecimal number) "is set in the address register AX (step 501). Here, the address assigned to the flip-flop 241 is taken in the input / output (I / O) area of FIG. The device 100 sets only the least significant bit corresponding to the memory board 201 to "1".
"00000001 (binary number)" is set in the data register DX (step 502).
When one flip-flop 242 is also desired to be activated at the same time, the processing device 100 sets "00000011 (binary number)" in the data register DX. Then, a memory write instruction for writing the data held in the data register DX to the address held in the address register AX is issued (step 503). As a result, the flip-flop of any memory board can be activated and the window to be allocated to the main memory B can be selected. It should be noted that if all users can freely switch this window, it may affect the processing of other users. Therefore, define it as a privileged instruction or only in the system setting routine. It is desirable to provide a protection function such as to use it.

Referring to FIGS. 1 and 4, when activating flip-flop 241, an address is first output from processing device 100 to address bus 130. In the example of FIG. 4, since the address “B0004” matches the address assigned to the flip-flop, the output of the decoding circuit 211 becomes active. Further, when a “write” signal instructing writing to the flip-flop 241 is applied from the processing device 100 to the control bus 110, the output of the NAND circuit 231 temporarily becomes low level. And
At the timing when the output of the NAND circuit 231 goes high due to the termination of the “write” signal on the control bus 110, the least significant bit of the data “00000001” output from the processing device 100 on the data bus 120. “1” of is taken into the flip-flop 241. As a result, the output of the flip-flop 241 becomes high level and the memory board is activated.

As described above, according to the first embodiment of the present invention, only whether or not the address on the address bus 130 is given to the memory cell 271 is controlled according to the preset state of the flip-flop 241. Therefore, the address conversion to the real memory is not necessary, and high-speed processing is possible. In addition, the first embodiment of the present invention is such that any of a plurality of n memory boards 201 to 20n,
That is, since the window can be activated,
Write data to multiple windows at the same time,
It becomes possible to select and use normal data when a failure occurs. Furthermore, in the first embodiment of the present invention, by issuing an access command to the address assigned to the flip-flop, it is possible to activate any of the memory boards 201 to 20n at any time during system operation.

Next, a second embodiment of the storage management device of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 5, the information processing system which is the target of the storage management apparatus of the second embodiment of the present invention executes the program and manages the system, as in the case of the first embodiment. Processor 100 and n memory boards 20
1 to 20n are connected by a control bus 110, a data bus 120, and an address bus 130.

Memory board 301 including storage management device
However, the first point is that it is configured to include a decoding circuit 311, a receiver circuit 321, a NAND circuit 331, a flip-flop 341, a memory control circuit 351, a data buffer circuit 361, and a memory cell 371. This is similar to the case of the embodiment. The memory board 301 further includes bank registers 391- for setting memory banks.
It includes A, B, C, D and a selector 381 for selecting one from these bank registers. Although four bank registers are provided here, it goes without saying that the number is not limited to this.

In the second embodiment, the setting of the flip-flop and the mode of memory access based on the setting are performed in the same manner as in the first embodiment.

The setting in the bank register 391 is performed in the same manner as in the flip-flop of the first embodiment shown in FIG. For example, in order to set the bank address for the bank register B, the address "in the input / output (I / O) area"
An access command is issued to BBxxx (x is an arbitrary hexadecimal number). As a result, "xxx" specified in the lower part of the address is fetched into the bank register B as a bank address. Which memory board the bank register B is set to has the bank address is instructed by each bit of the data bus 120, as in the case of the flip-flop.

Referring to FIG. 7, addresses in the input / output (I / O) area for the above flip-flop or bank register are shown. As described above, x in the address means that any hexadecimal number can be designated.

Referring to FIG. 5, a memory access instruction from the processing unit 100, that is, the control bus 110 is issued.
The memory control circuit 351 is notified of the “read” signal or the “write” signal given via the. At this time, if the flip-flop 341 is activated, the memory control circuit 351 decodes the address of the address bus 130 and determines which bank in the window corresponds to the access. Then, the memory control circuit 351 gives a control signal to the selector 381 so that the content of the bank register of the corresponding bank is used as an actual memory. Further, at this time, the memory control circuit 351 transfers the data on the data bus 120 to the data buffer circuit 361.
To the data input of the memory cell 371 via. Similar to the first embodiment, even if the memory access is instructed from the processing device 100, the access to the memory cell 371 does not occur unless the flip-flop 341 is activated.

Referring to FIG. 6, the address map in the storage management device of the second embodiment of the present invention has the area of the main memory B in addition to the area of the main memory A as in the first embodiment. is doing. This main memory B is divided into n windows, and each of these windows is further divided into m memory banks. An arbitrary memory bank can be set for each window by setting the above bank register.

As described above, according to the second embodiment of the present invention, although the address control in the memory control circuit 351 becomes complicated as compared with the first embodiment, it is assigned to the main memory B. The advantage is that the window space can be used for more than one function.
Further, since it is possible to activate any of a plurality of memory boards of the n memory boards 201 to 20n, that is, windows, and to allocate any memory bank, it is possible to write data in a plurality of windows at the same time and It is possible to select and use normal data when it occurs. Further, by issuing an access command to the address assigned to the flip-flop, any memory board 201 to 20 can be operated during system operation.
n can be activated at any time, and any memory bank can be assigned.

[0033]

As is apparent from the above description, according to the present invention, it is sufficient to control whether or not an address is given to a memory cell according to a state value preset for each memory board. Address conversion to memory is not required, and high-speed processing is possible.

Since a plurality of arbitrary memory boards, that is, windows can be activated, it is possible to write data in a plurality of windows at the same time and select and use normal data when a failure occurs. It will be possible.

Further, with respect to the above flip-flop,
Since the status value can be set during system operation, any window can be activated at any time.

Further, by allocating the window space to a plurality of bank memories, there is an effect that the window space can be used for a plurality of functions.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a first embodiment of a storage management device of the present invention.

FIG. 2 is a diagram showing an address map in the storage management device according to the first embodiment of this invention.

FIG. 3 is a flow chart showing an operation for setting a state in an embodiment of the storage management device of the present invention.

FIG. 4 is a time chart showing a state setting operation in one embodiment of the storage management device of the present invention.

FIG. 5 is a block diagram showing the configuration of a second embodiment of the storage management device of the present invention.

FIG. 6 is a diagram showing an address map in the storage management device according to the second embodiment of the present invention.

FIG. 7 is a diagram showing a setting target of state setting in the second embodiment of the storage management device of the present invention.

FIG. 8 is a diagram showing an address map in a storage management device according to a conventional technique.

[Explanation of symbols]

 100 processor 110 control bus 120 data bus 130 address bus 201 to 20n memory board 211 decoding circuit 221 receiver circuit 231 NAND circuit 241 flip-flop 251 memory control circuit 261 data buffer circuit 271 memory cell 301 to 30n memory board 311 decoding circuit 321 receiver Circuit 331 NAND circuit 341 Flip-flop 351 Memory control circuit 361 Data buffer circuit 371 Memory cell 381 Selector 391 Bank register

Claims (5)

[Claims] 1. A storage device connected to each of a plurality of storage devices allocated to the same address space, storing a setting as to whether or not to access the connected storage device, and the storage device connected according to this setting. A storage management device characterized by managing access to a storage device. 2. An instruction circuit connected to each of a plurality of storage devices allocated to the same address space and indicating whether or not the connected storage device is accessible, and accessing the connected storage device. An instruction setting circuit for setting whether or not to the instruction circuit, and an access control circuit for controlling access to the connected storage device based on the value of the instruction circuit set by the instruction setting circuit. Characteristic storage management device. 3. An instruction circuit connected to each of a plurality of storage devices allocated to the same address space, for indicating whether or not the connected storage device is accessible, and accessing the connected storage device. An instruction setting circuit for setting whether or not to the instruction circuit, and an access control circuit for controlling access to the connected storage device based on the value of the instruction circuit set by the instruction setting circuit, A storage management device that simultaneously writes to a plurality of storage devices allocated to the same address space. 4. The access control circuit, when an access to the storage device occurs, and if the access is an access to the connected storage device, the instruction circuit can access the connected storage device. 3. The storage management device according to claim 2, wherein the address related to the access is output to the storage device only when an instruction to the effect that the above is given is issued. 5. The access control circuit outputs a plurality of bank registers, each of which holds an address in the connected storage device, and one of the addresses held by the bank register, to the storage device. When an access to the storage device occurs, the access is an access to the connected storage device and the instruction circuit indicates that the connected storage device is accessible. 3. The storage management device according to claim 2, wherein the address held in the bank register corresponding to the bank related to the access is output from the selector to the storage device.