JPH07321202A - Forming method for multilayer interconnection - Google Patents

Abstract

PURPOSE:To obtain a forming method for multilayer interconnections with good electric contact between layers without the lowering of the productivity by process increase in the case of using wet etching in combination. CONSTITUTION:When a multilayer interconnection is formed, the lower electrodes 2b of the multilayer interconnection are made out of tantalum(Ta), and insulating layers 3 between interconnections are made of an insulating layer out of noncrystalline material mainly composed of silicon, and the surfaces of the Ta electrodes are plasma-processed just before the process of attaching the upper electrode film. By doing this way, insulating coats formed on the surfaces of the Ta electrodes on the occasion of attaching the insulating layers etc. are removed. Consequently, it becomes possible to lower contact resistance without using wet etching in combination.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a multi-layered wiring connected by a connection opening in a thin film element manufactured by a thin film process, and particularly for obtaining a good contact resistance in the connection opening. Regarding the method.

[0002]

2. Description of the Related Art In a thin film element having a multi-layered wiring of metal films, a plurality of metal films (wiring) formed with an insulating layer sandwiched therebetween.
In order to obtain electrical contact between the wirings, a connection opening (contact hole) is formed at a desired position of the insulating film to connect the wirings. The multilayer wiring in the thin film element having the above structure has a lower metal film deposited on a glass substrate,
This lower metal film is patterned to form a lower wiring,
An insulating film is formed to cover the lower metal film, a contact hole is formed at a desired position of the insulating film, an upper metal film is formed on the insulating film, and the upper metal film is patterned to form an upper wiring. By forming the.

[0003]

However, according to the above manufacturing method, an insulating film is formed on the surface of the lower metal film when depositing the insulating film and etching the insulating film. Since the lower wiring and the upper wiring are connected via this film, the contact resistance between the multilayer wirings becomes higher than a desired resistance value, and as a result, for example, charge transfer failure of the thin film element is caused. was there. When the lower wiring is formed of chromium (Cr) and the upper wiring is formed of indium tin oxide (ITO), the insulating film mainly composed of fluoride of Cr formed on the surface of Cr is CF _4. After being exposed to plasma, it is further exposed to O ₂ plasma to replace a part of fluorine in the insulating film with oxygen, and the film is removed by immersing it in an etching solution of hydrochloric acid-nitric acid-water system to obtain a desired contact. A method of ensuring resistance has been proposed (see Japanese Patent Publication No. 4-30178). By the way, in the above method, since dry etching and wet etching are used in combination, there is a problem that productivity is lowered due to an increase in steps in the manufacturing process of the thin film element.

The present invention has been made in view of the above-mentioned circumstances, and does not cause a decrease in productivity due to an increase in steps,
An object of the present invention is to provide a method for forming a multi-layered wiring, which can obtain good electrical contact between the multi-layered wiring.

[0005]

In order to solve the above-mentioned problems of the conventional example, the method of multilayer wiring according to the present invention is characterized by including the following steps. As the first step,
The tantalum (Ta) electrode is covered with an insulating layer made of an amorphous material mainly containing silicon. In the second step, the insulating layer is plasma-etched to form a connection opening. As a third step, plasma treatment is performed on the Ta electrode surface in the connection opening immediately before the deposition of the upper electrode film. Fourth
In the step of, the upper electrode connected to the Ta electrode through the connection opening is formed.

[0006]

According to the method of the present invention, the lower electrode of the multilayer wiring is formed of tantalum (Ta), the insulating layer between the wirings is formed of the insulating layer made of an amorphous material mainly containing silicon nitride, and By performing plasma treatment on the Ta electrode surface immediately before the step of depositing the electrode film, it is possible to remove the insulating coating formed on the Ta electrode surface when depositing the insulating layer. The insulating film can be removed only by dry etching without using.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS As an example of a method of manufacturing a multi-layer wiring according to the method of the present invention, a case of applying it to a method of manufacturing a TFT formed by a thin film process will be described with reference to FIGS.
A description will be given with reference to (a) and (b). A 100 nm thick tantalum (T
a) A film is deposited by a sputtering method or the like and patterned into a desired pattern by a photolithography method to form a gate electrode 2a and a lower wiring 2b of the TFT. Then, a first SiN film having a film thickness of 300 nm as a gate insulating film and an interlayer insulating film of the TFT 3, an a-Si film 4 ′ having a film thickness of 50 nm as an active layer which becomes a channel of the TFT, and a film serving as a channel protective film of the TFT. A second SiN film 5'having a thickness of 150 nm is continuously deposited by plasma CVD without breaking the vacuum (Fig. 1).
(A)). Next, the second SiN film 5'is patterned into a desired pattern to form a channel protective layer 5 on the gate electrode side (FIG. 1B). Next, the P-doped a-Si film 6'for ohmic contact is subjected to plasma CV.
D is deposited to a film thickness of 100 nm, and a titanium (Ti) film 7'with a film thickness of 200 nm is further deposited by the sputtering method (FIG. 1C). Then, the a-Si film 6'and the Ti film 7'are patterned using the same resist pattern to form the source electrode 6a and the drain electrode 6b. Furthermore, a
The -Si film 4'is patterned to form the semiconductor active layer 4 (FIG. 2A).

[0008] Next, the first SiN film 3 with a desired resist pattern, SF _6, by O ₂ gas for dry etching by a mixed gas of Freon 123 and O _2, is increased resist stripping effect After performing plasma ashing, the resist pattern is removed by a resist stripping solution to form a contact hole 8 in the first SiN film 3 on the lower wiring 2b (FIG. 2B). Further, a polyimide film 9 having a thickness of 1.15 μm is applied as an insulating film by a spin coating method and patterned to form a contact hole 10 on the contact hole 8 (FIG. 2).
(C)).

Next, plasma treatment of the lower wiring 2b in the contact portion, which is a characteristic portion of the method of the present invention, is performed (FIG. 3A). This plasma treatment is performed using a mixed gas of SF ₆ and O ₂ . The conditions for plasma treatment are
For example, SF ₆ / O ₂ mixture ratio: 60/40, RF power: 450 W, pressure: 11 Pa, processing time: 75 seconds. O ₂ gas is used for adjusting the etching rate and stabilizing the etching.
The plasma treatment is performed on the surface of the lower wiring 2b (Ta surface).
This is carried out in order to react the high-quality altered layer 20 formed in the above with SF ₆ and remove it by etching. The altered layer 20 includes a step of performing a heat treatment or an annealing treatment when the first SiN film 3 is deposited on the lower metal film forming the lower wiring 2b by CVD, and a dry etching of the first SiN film 3. During the subsequent O ₂ ashing, Ta of the lower metal film is
It is considered to be a substance (an insulating film such as an oxide film) formed by exposing the surface to O ₂ plasma.

Thereafter, aluminum (A
l) / molybdenum (Mo) laminated film is deposited by a sputtering method and patterned into a desired pattern to form the upper wiring 11, and the lower wiring 2b and the upper wiring 11 are connected via a contact hole. Thus, a thin film element including a multi-layer wiring can be obtained (FIG. 3B).

The lower wiring (Ta) 2b and the upper wiring (A) of the thin film element including the TFT and the multilayer wiring manufactured in the above process
For electrical contact with (1 / Mo) 11, the insulating film (altered layer) on the surface of the lower electrode is removed by performing plasma treatment, so that the contact resistance can be lowered. In the above embodiment, the size of the opening of the contact hole 8 of the first SiN film 3 is 6 μm □,
When the contact resistance between Ta / Al / Mo was measured, the following results were obtained. That is, when there is no plasma treatment, the contact resistance is several kΩ or more per contact hole, whereas when the plasma treatment is performed, it becomes about 20 Ω per contact hole, and it is confirmed that the contact resistance is significantly reduced. I was able to.

According to the above-described embodiment, the lower wiring 2b of the multilayer wiring is formed of tantalum (Ta), the insulating layer between the wirings is formed of the first SiN film 3, and the metal film to be the upper wiring 11 ( Immediately before the step of depositing the Al / Mo laminated film),
By plasma-treating the surface of the lower wiring (Ta) 2b, it is possible to remove the deteriorated layer (insulating coating) 20 (FIG. 3A) existing on the surface of Ta to lower the contact resistance. At this time, it is not necessary to use wet etching together to remove the insulating film, so that good electrical contact between the multilayer wirings can be obtained without causing a decrease in productivity due to an increase in steps.

In the above embodiment, the plasma treatment is performed by S
Although the mixed gas of F ₆ and O ₂ was used, the insulating film (altered layer) existing on the Ta surface can be removed by using only the SF ₆ gas. This is because the O ₂ gas is used for adjusting the etching rate and the like, as described above, and the insulating film (altered layer) is removed by etching with the SF ₆ gas. The insulating coating (altered layer) 20 can be removed by etching by using CF ₄ gas instead of SF ₆ gas. Further, although the insulating layer between the wirings is formed of the SiN film 3, SiO ₂ or the like
It may be formed of an insulating layer made of an amorphous material mainly containing silicon.

[0014]

According to the method of the present invention, the lower electrode of the multilayer wiring is formed of tantalum (Ta), and the insulating layer between the wirings is formed of an insulating layer made of an amorphous material mainly containing silicon. Immediately before the step of depositing the upper electrode film, the surface of the Ta electrode is subjected to plasma treatment to remove the insulating coating formed on the surface of the Ta electrode when depositing the insulating layer or the like to achieve low resistance. Therefore, it is not necessary to use wet etching together when removing the insulating film. Therefore,
Good electrical contact between the multilayer wirings can be obtained without lowering the productivity due to the increase in the number of processes.

[Brief description of drawings]

1A to 1C are process explanatory views showing a part of a method for manufacturing a thin film element to which the method of the present invention is applied.

2A to 2C are process explanatory views showing a part of a method for manufacturing a thin film element to which the method of the present invention is applied.

3A and 3B are process explanatory views showing a part of a method of manufacturing a thin film element to which the method of the present invention is applied.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Glass substrate, 2a ... Gate electrode, 2b ... Lower wiring, 4 ... Semiconductor active layer, 5 ... Channel protective layer, 6
a ... Source electrode, 6b ... Drain electrode, 8 ... Contact hole, 9 ... Polyimide film, 10 ... Contact hole, 11 ... Upper wiring, 20 ... Altered layer (insulating film)

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01L 29/40 A 29/786

Claims (1)

[Claims] 1. A step of coating a tantalum (Ta) electrode with an insulating layer made of an amorphous material mainly containing silicon, a step of plasma-etching the insulating layer to form a connection opening, and a connection. And a step of performing plasma treatment on the surface of the Ta electrode in the opening for use just before the deposition of the upper electrode film, and a step of forming an upper electrode connected to the Ta electrode through the opening for connection. And a method for forming multilayer wiring.