JPH0730426A - D/a conversion device - Google Patents

Abstract

PURPOSE:To provide a D/A converter having a high dynamic range. CONSTITUTION:A distributing circuit 3 distributes and outputs an input signal so that an analog signal is outputted from either one of the 1st and 2nd D/A converters 1, 2. An adder 5 mutually adds the outputs of the 1st and 2nd D/A converters 1, 2 with a prescribed ratio. Consequently an analog signal is outputted from the 1st D/A converter 1 when the level of the input signal is large, or from the 2nd D/A converter 2 when the level is small.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a D / A converter,
In particular, it seeks to obtain a higher dynamic range.

[0002]

2. Description of the Related Art With recent advances in digital signal processing technology, the importance of D / A conversion technology, which is an interface between a digital signal and an analog signal, is increasing.

A conventional D / A converter is shown in FIG. 8 and its description will be made (for example, published by Seibundou Shinkosha, "Radio and Experiment", March 1992, pages 24 to 25).

The input 16-bit, sampling frequency fs signal is 8 times oversampling digital filter 100 is 20-bit, sampling frequency 8fs
Is converted into a signal of and is given to the processor 101. Therefore, the processor 101 input is -524288 to +524287.
Is. In the processor 101, the input is -32768-
When +32767, 16-bit D / A converter (hereinafter,
Zero for 102) and DAC1
For 03, the input is output as it is. When the input is 32768 or less, for the DAC 102,
It outputs {input +32768} and outputs -32768 to the DAC 103. When the input is +32767 or more, the input value to the DAC 102 is {input-3276.
7} is output and +32767 for the DAC 103.
Is output.

The DACs 102 and 103 D / A convert the input signal and output it as an analog signal. These outputs are directly output from the DAC 102 and the DAC 103.
The output of is subjected to 1 / k (here, 1/16) in the attenuator 104 and then given to the adder 105.

[0006]

However, in the above configuration, unless the attenuation rate (1 / k) of the attenuator 104 is realized with extremely high accuracy, the input signal to the processor 101 is +32767, -32768. Discontinuity occurs in the output waveform at the point where the value exceeds, and distortion occurs. In particular, when the input to the processor 101 is a sine wave having a slight or slightly low level with +32767 as an offset, there is a problem that the effect of the distortion becomes remarkable.

In view of the above problems, the present invention provides a D / A converter which does not require attenuator precision so much.

[0008]

In order to achieve this object, a D / A converter according to the present invention comprises first and second D / A converters for converting a digital signal into an analog signal, and M.
Distribution means for distributing and outputting the input signal to the first and second D / A converters so that either one of them outputs an analog signal based on the level of the bit input signal; And an adder for adding the outputs of the two D / A converters with a predetermined ratio.

[0009]

With this configuration, since the analog signal is output from either one of the D / A converters in accordance with the level of the input signal, the accuracy of the attenuator is not required so much and the D / A converter is not required. Since the switching between the A converters does not occur frequently, the discontinuity of the output waveform rarely occurs.
A conversion can be realized.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a D / A converter according to the present invention. To explain this figure,
Reference numeral 2 denotes a D / A converter (hereinafter simply referred to as a DAC), which converts an input digital signal into an analog signal and outputs it. Two 16-bit inputs are used here.
Reference numeral 3 denotes a distribution circuit, which corresponds to the DAC1 and the DAC1 according to the level of the signal (here, 20 bits) input from the terminal D.
The input signals are distributed to 2. Here, the level of the input signal is a predetermined level (here, −32768-
+32767 range), the upper 16 bits of the input signal are immediately output from the terminal G and zero is output from the terminal L, and when the level of the input signal is within a predetermined range for a certain time (τ0) or more, the input The zero cross point of the signal is detected, and at this point, the terminal G outputs zero and the terminal L outputs the lower 16 bits of the input signal. 4 is an amplifier, here 16 times (24
The one with a gain of dB) is used. An adder 5 adds the output of the amplifier 4 and the output of the DAC 2 at a ratio of 1: 1 and outputs the result.

Next, the operation of FIG. 1 will be described with reference to FIG. When the input signal is within a predetermined level (0 ≦ t ≦
t0 (see (a) of FIG. 2), in the distribution circuit 3,
The lower 16 bits of the input signal are output from the terminal L as they are (see (b) of FIG. 2). Further, zero is output from the terminal G (see (c) in FIG. 2). When the level of the input signal exceeds a predetermined level at t = t0, the distribution circuit 3 immediately sets the output of the terminal L to zero, and the terminal G outputs the upper 16 bits of the input signal. At t = t1, the input signal again falls within the predetermined level, but at the first zero-cross point (t = t2), the elapsed time (τ1) after the input signal falls within the predetermined level is τ0 or less, so G,
The signal is output from L as it is. At t = t3, the input signal again falls within the predetermined level, but at the second zero-cross point (t = t4) from this time, the elapsed time (τ2) is τ0 or more, so at t = t4, from the terminal L The lower 16 bits of the input signal are output, and zero is output from the terminal G.

As described above, in the D / A converter according to the present invention, once the input signal level becomes higher than the predetermined level, only the DAC 1 connected to the terminal G side of the distribution circuit 3 outputs the signal for a fixed time. Therefore, even if the gain of the amplifier 4 is not so accurate as 24 dB, discontinuity does not occur in the waveform. Further, even at a point (t = t0) where the input signal level exceeds the predetermined range, if the gain of the amplifier 4 is approximately 24 dB, the discontinuity of the output waveform becomes almost inconspicuous. Further, at the point (t = t4) at which the DAC1 is switched to the DAC2, since the switching is performed at the zero cross point, there is almost no influence due to the deviation of the gain of the amplifier 4 from the design value.

For this reason, the precision of the amplifier 4 is not required so much, and since switching between the DACs 1 and 2 does not occur frequently, it is possible to obtain an excellent effect that the discontinuity of the output waveform hardly occurs. .

In the present embodiment, the 16 bits output from the terminal G of the distribution circuit 3 are the same as the upper 16 bits of the input signal, but the upper 16 bits are output by rounding. It is a good one.

FIG. 3 is a distribution circuit 3 shown in FIG.
It is a concrete example of. Explaining this figure, 11 is a level detector, the input of which is a predetermined level, here −
When it exceeds the range of 32768 to +32767, "1" is output. Reference numeral 12 is a zero-cross detector, which outputs "1" at that moment when the sign of the input changes. Reference numeral 13 is a control circuit, and when "1" is given to the terminal A, immediately the terminal G
Is "1", the terminal L outputs "0", and the terminal A is supplied with "0" for a certain period of time, the moment the terminal B is supplied with "1", the terminal G is "0" and the terminal L is It changes to "1". Reference numerals 14 and 15 denote gate circuits, which output the input as they are when "1" is applied to the terminal C and output zero when "0" is applied to the terminal C. The gate circuit 14 receives the upper 16 bits of the 20 bits of the input signal supplied from the input D, and the gate circuit 15 receives the lower 16 bits of the 20 bits of the input signal.

Next, the operation of FIG. 3 will be described. Input D
Input signal given by +32767 or more, or-
When it becomes 32768 or less, the level detector 11 detects this and outputs "1". Then, in the control circuit 13, since the terminal A becomes "1", the terminal G becomes "1" and the terminal L becomes "0". Since these signals are given to the gate circuits 14 and 15, the gate circuit 14 outputs the upper 16 bits of the input signal, and the gate circuit 15 outputs zero. Next, when the input signal falls within the range of −32768 to +32767 and a certain period of time elapses and the input signal crosses zero (that is, the sign of the input signal changes), the zero cross detector 12 detects this. Since it detects and outputs "1", the terminal G of the control circuit 13 becomes "0" and the terminal L becomes "1". Since these signals are given to the gate circuits 14 and 15, the gate circuit 14 outputs zero and the gate circuit 15 outputs the lower 16 bits of the input signal. In this way, the outputs as shown in FIGS. 2B and 2C can be obtained.

FIG. 4 shows a concrete example of the control circuit 13 in FIG. Explaining this figure, 21 is a timer, which immediately outputs "0" when the input becomes "1",
When the input is "0" for a certain period of time, "1" is output. Two
2 is an AND gate, and 23 is a D flip-flop with reset. The terminal R is a reset terminal, and when "1" is given, the outputs Q and Q of the D flip-flop become "0" and "1", respectively.

With this structure, when the input A becomes "1", the D flip-flop 23 is reset, and the output G becomes "1" and the output L becomes "0" immediately. Further, since the timer 21 outputs "1" when the input A is "0" for a certain period of time, the AND gate 22 outputs "1" when the input B is "1", and this output is D. It is given to the clock input terminal CK of the flip-flop 23, and the terminal Q of the D flip-flop 23 becomes "1" and the terminal Q bar becomes "0". By doing so, the control circuit 1 shown in FIG.
3 can be obtained.

FIG. 5 shows the distribution circuit 3 shown in FIG.
It is another concrete example of. In this figure, components having the same functions as those in FIGS. 1 to 4 are designated by the same reference numerals, and detailed description thereof will be omitted. Reference numeral 31 is an overflow limiter, which is +32 when the value of input 20-bit data is +32767 or more.
When 767 is output and it is -32768 or less,-
32768 is output. A multiplier 32 multiplies the inputs given to the terminals A and B and outputs the result from the terminal C. Here, the output from the terminal C is one that outputs the upper 16 bits of the value obtained by A × B by rounding. 33 is a subtractor. A weight coefficient generator 34 generates a weight coefficient W from the terminal X. Here, the weighting factor W is represented as 1.0 to 0.0 by using 10-bit data, and when the signal given to the terminal A becomes "1", the weighting factor W gradually decreases and becomes zero. When the signal applied to the terminal A is "0" for a certain period of time (τ0) or more, the weighting coefficient W from the terminal X is reached when the signal applied to the terminal B becomes "1". Is output as 1.0.

Next, the operation of FIG. 5 will be described with reference to FIG. First, the input signal given from the input D is -3276.
8 to +32767 (0 ≦ t ≦ t0, see (a) of FIG. 6), the weighting factor generator 34 determines that the weighting factor W = 1.
0 is generated (see FIG. 6B). Therefore, the multiplier 32
The data input to the terminal A of is the same value as the input D,
Further, since 1.0 is given to the terminal B, its output has the same value as the input D. This value is output from the output L and is subtracted from the input D by the subtractor 33 to output G.
Will be output. The input D of the + input of the subtractor 33 is −
The output of the multiplier 32 is given to the input, and the multiplier 3
Since the output of 2 is equal to the input D, the output of the subtractor 33 is zero. That is, at this time, the input signal is directly output from the output L, and zero is output from the output G.

Next, at t = t0, the value of the input D is +3276.
When it exceeds 7, the output of the level detector 11 becomes "1" and this is given to the terminal A of the weighting coefficient generator 34, so that the weighting coefficient W output from the terminal X begins to gradually attenuate (Fig. 6 (b), t ≧ t0). t0 ≦ t ≦
At t1, the input D is +32767 or more, so +32767 is output from the overflow limiter 31, and at t ≧ t1, the input D is +32767 or less, so the value is output as is, and this value is multiplied by the weighting coefficient W. It Therefore, the signal supplied to the input D is output from the output L while being gradually attenuated, and the residual difference is output from the output G. With this configuration, the outputs from the outputs G and L can be switched in the form of crossfade.

Next, at t = t2, the input D has a zero-cross point, but at t = t1, since a certain time has not passed since the level of the input D was within a predetermined range (τ3 <τ
0) The weighting factor W does not change. At t = t4, the input D has a zero cross point again, but this time, since a certain time has passed since the level of the input D was within the predetermined range at t = t3 (τ4 ≧ τ0), the weighting coefficient W immediately becomes 1.0.

By configuring the distribution circuit 3 as described above, when the input signal exceeds a predetermined level, it is possible to switch between the output G and the output L by crossfade, and thus switching that may occur at the time of switching. The noise can be further reduced.

In the above embodiment of FIG. 1, DA
Although the outputs of C1 and C2 are output by using the amplifier 4 and the adder 5, it goes without saying that an analog mixer with a different addition ratio may be used with the operational amplifier 41 as shown in FIG. Here, R3 = R1, R1 = R2
If / 16, a circuit equivalent to the circuit composed of the amplifier 4 and the adder 5 of FIG. 1 can be obtained. Although the output G is 16 bits in FIG. 3, it is 20 bits (20 bits of the input D is input to the gate circuit 14),
The same effect can be obtained by using a 20-bit input DAC1 connected thereto.

[0026]

As described above, according to the present invention, the input signal is distributed to the first and second D / A converters so that one of them outputs the analog signal based on the level of the input signal. Since the outputs of the first and second D / A converters are added with a predetermined ratio, the accuracy at the time of addition is not required so much. Since it is not frequently switched, it has an excellent effect that the discontinuity of the output waveform hardly occurs.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a D / A conversion device according to the present invention.

FIG. 2 is a waveform diagram showing waveforms of respective parts in FIG.

FIG. 3 is a block diagram showing a specific example of a distribution circuit 3 in FIG.

FIG. 4 is a block diagram showing a specific example of a control circuit 13 in FIG.

5 is a block diagram showing another specific example of the distribution circuit 3 in FIG.

FIG. 6 is a waveform diagram showing waveforms of respective parts in FIG.

FIG. 7 is a circuit diagram showing an analog mixer.

FIG. 8 is a block diagram showing a conventional D / A conversion device.

[Explanation of symbols]

 1, 2 D / A converter 3 distribution circuit 4 amplifier 5 adder 11 level detector 12 zero cross detector 13 control circuit 14, 15 gate circuit 32 multiplier 33 subtractor 34 weighting factor generator

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hideaki Hatanaka 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (3)

[Claims] 1. First and second D / A converters for converting a digital signal into an analog signal, and the first and second D-A converters based on the level of an M-bit input signal.
Distribution means for distributing and outputting an input signal so that an analog signal is output from one of the D / A converters, and the outputs of the first and second D / A converters have a predetermined ratio. And an adding means for adding
/ A converter. 2. The distributing means immediately outputs the upper N bits (M ≦ N <M / 2) of the input signal to the first D / A converter when the input signal exceeds a predetermined level. At the same time, zero is output to the second D / A converter, and when the input signal falls below a predetermined level for a certain period of time or more, it is input to the second D / A converter at the zero cross point of the input signal. Lower L bits of signal (M>L> M /
2. The D / A according to claim 1, wherein 2) is output and zero is output to the first D / A converter.
A converter. 3. The distributing means, when the input signal exceeds a predetermined level, cross-fades the first and second D / A converters so that the upper N bits (M ≦ N <of the input signal).
M / 2) is output from the first D / A converter and zero is output from the second D / A converter, and when the input signal falls below a predetermined level for a certain time or longer, the zero crossing of the input signal is performed. At the point, the lower L bits (M>L> M / 2) of the input signal to the second D / A converter are input.
Is output and zero is output to the first D / A converter.