JPH07297870A - Tdma data receiver - Google Patents

Abstract

PURPOSE:To implement automatic frequency control by taking correlation between reception data after base band delay detection and a known synchronization word and using a complex correlation and a correlation power. CONSTITUTION:A correlation arithmetic circuit 9 takes a base band signal corresponding to a known synchronization word from a synchronization word generating circuit 10 with received data for a block of synchronization words of I, Q signals and gives a complex correlation psi as an estimated phase error thetae due to a frequency offset to an averaging circuit 12 and a correlation power ¦psi¦ to a correlation power discrimination circuit 11. When the correlation power ¦psi¦ exceeds the threshold power, the discrimination circuit 11 gives its output to the averaging circuit 12 as a control signal, in which the complex correlation values psi in preceding and current reception slots are averaged and a resulting signal is fed to a phase compensation circuit 13. On the other hand, when the correlation power ¦psi¦ is less than the threshold power, the discrimination circuit 11 gives the complex correlation psi obtained in the precedingly received slot to the phase compensation circuit 13 after calculation of averaging as an estimated phase error thetae in a current reception slot. Then an estimate offset is used to compensate the phase and its output is given to discrimination circuits 14, 15, in which the signal is discriminated in terms of binarization and the result is outputted from a decoder 16.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time division multiple access (TDMA) data receiving apparatus used in digital radio communication, and at the time of frame synchronous reception, the received data after baseband differential detection and a known synchronous word are used. Correlate,
The phase error is compensated due to the frequency offset, and the automatic frequency control (AFC) is performed using the value of the correlation power.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram showing the structure of a conventional TDMA data receiving apparatus.
4-shift 4-phase phase modulation (QPSK) wave signal (hereinafter π / 4
The case of receiving a shift QPSK modulated wave signal) is shown.

In FIG. 4, 1 is an antenna for receiving a π / 4 shift QPSK modulated wave signal of TDMA, 2 is a receiving root Nyquist band pass filter (hereinafter abbreviated as RNBPF) for waveform shaping of the received signal, 3 is a limiter amplifier connected to the output of RNBPF2, and 4 is
A quadrature detector for frequency-converting the output of the limiter amplifier 3 to detect an in-phase component and a quadrature component of the baseband,
Reference numeral 5 is a local oscillator for supplying the quadrature detector 4 with a sine wave signal which is quasi-synchronized with the carrier frequency of the received signal,
FIG. 2 shows a phase diagram after baseband differential detection when a frequency offset is generated in this local oscillator.

Reference numerals 6 and 7 denote in-phase components of the quadrature detector 4,
An A / D converter for sampling the quadrature component output at a symbol data identification point for each symbol period and converting it into a digital signal, and 8 takes in the outputs X and Y of the A / D converters 6 and 7 and receives them. Π / 4 shift QPS
A baseband delay detection circuit that outputs the cosine and sine of the modulation phase difference of the K modulation wave signal as the in-phase component I and the quadrature component Q, respectively, and 9 is the synchronization word of the I and Q signals output from the baseband delay detection circuit 8. For the section of, the complex correlation value Ψ between the I and Q signals and the baseband signal value corresponding to the known sync word output from the sync word generation circuit 10 described later is calculated, and the value of this complex correlation value Ψ is Local oscillator 5
Correlation calculation circuit to be supplied to the phase compensation circuit 13 described later as information of the estimated value of the phase error θe caused by the frequency offset at 10, and 10 as the cosine and sine of the modulation phase difference corresponding to the known synchronization word as the baseband signal. A synchronization word generation circuit to be supplied to the correlation operation circuit 9, 13 is a frequency offset included in the output signals I and Q of the baseband delay detection circuit 8 using the value of the complex correlation value Ψ supplied from the correlation operation circuit 9. This is a phase compensation circuit for compensating the phase error θe caused by the above. FIG. 3 shows a phase diagram of the determination result after the phase compensation is performed by this phase compensation circuit.

Reference numerals 14 and 15 are decision circuits for binary-deciding the output of the phase compensation circuit 13, and 16 are decoders for converting the outputs of the decision circuits 14 and 15 into binary serial data.
Reference numeral 17 is a reception data output terminal for detecting the output of the decoder 16 as reception data.

Next, the operation of the above-mentioned conventional example will be described based on FIG. 4 and with reference to FIGS. In FIG. 4, the π / 4 shift QPSK modulated wave signal received from the antenna 1 is input to the quadrature detector 4 via the RNBPF 2 and the limiter amplifier 3, and is frequency-converted to a baseband signal through the quadrature detector 4. At this time, assuming that the symbol rate of the modulated wave signal is fR = 1 / T (T: symbol period), the outputs of the A / D converters 6 and 7 that sample the received signal at the symbol data identification point for each symbol period. X (n
T) and Y (nT) are as in (Equation 1) and (Equation 2). However, it is assumed that the noise is zero.

[0007]

[Expression 1] X (nT) = COS (φ (nT) + 2πΔfnT)

[0008]

[Formula 2] Y (nT) = SIN (φ (nT)) + 2πΔfnT In (Formula 1) and (Formula 2), φ (nT) is the received π / 4.
The modulation phase, Δf, of the shift QPSK modulated wave signal indicates a frequency offset amount which is an error between the center frequency of this modulated signal and the frequency of the local oscillator 5. In the baseband differential detection circuit 8, X (nT), Y (n
The operations of (Equation 3) and (Equation 4) are performed on T).

[0009]

## EQU3 ## I (nT) = X (nT) X ((n-1) T) + Y (nT)
Y ((n-1) T)

[0010]

## EQU4 ## Q (nT) = Y (nT) X ((n-1) T) -X (n
T) Y ((n-1) T) As a result, the in-phase output I of the baseband differential detection circuit 8
(nT), the quadrature output Q (nT) is the cosine and sine of the modulation phase difference Δφ (nT) of the received π / 4 shift QPSK modulated wave signal as shown in (Equation 5) and (Equation 6). To occur.

[0011]

[Equation 5] I (nT) = COS (Δφ (nT) + θe)

[0012]

[Equation 6] Q (nT) = SIN (Δφ (nT) + θe)

[0013]

[Formula 7] Δφ (nT) = φ (nT) −φ ((n−1) T) However, θe in (Formula 5) and (Formula 6) is the local transmission as represented by (Formula 8). This is a phase error caused by the frequency offset Δf in the device 5, and appears in the phase diagram on the I and Q planes as a phase rotation in a constant direction for each symbol as shown in FIG. In FIG. 2, the white circle indicates the correct received signal point (Δφ), and the black circle indicates the frequency offset Δ.
It is a signal point (Δφ + θe) whose phase is shifted by the influence of f.

[0014]

## EQU00008 ## .theta.e = 2.pi..DELTA.fT In the following description, a signal having an in-phase component and a quadrature component is expressed as a complex signal having an in-phase component in the real part and an quadrature component in the imaginary part.

The output of the baseband differential detection circuit 8 in the receiving slot of the local station is the complex signal S (n
Express as T).

[0016]

## EQU00009 ## S (nT) = I (nT) + jQ (nT) = exp (j (.DELTA..phi. (NT) +. Theta.e)) (j: imaginary number) Further, here, each reception slot has a synchronization word of L symbols. , It is assumed that the synchronization word of the reception slot of the local station is already known. Then, the baseband signal corresponding to this known sync word is expressed as a complex signal in S shown in (Equation 10).
Expressed as i (kT) (k = 0, 1, 2, ... L-1),
It is assumed that this complex signal is output from the synchronization word generation circuit 10.

[0017]

## EQU10 ## Si (kT) = exp (jΔφi (kT)) (k = 0, 1, ... L-1) Further, regarding the reception data S (nT) after the baseband differential detection in each reception slot. It is assumed that a sync word exists in the 1st to Lth symbols (S (0) to S ((L-1) T)). At this time, the correlation calculation circuit 9 calculates the complex correlation value Ψ with the known sync word Si (kT) as shown in (Equation 11) for the section of the sync word of S (nT).

[0018]

[Equation 11]

Also, in (Equation 11), k = 0, 1, ...
Since S (kT) at L-1 is a synchronization word, the relationship of (Equation 12) is established from (Equation 9) and (Equation 10).

[0020]

[Equation 12] S (kT) = exp (j (Δφi (kT) + θe)) (k = 0, 1, ... L-1) Therefore, (Equation 10) and (Equation 12) are transformed into (Equation 11) Substituting into

[0021]

[Equation 13]

The complex correlation value Ψ gives information on the phase error θe caused by the frequency offset. Phase compensation circuit 1
In 3, the value of the complex correlation value Ψ given by (Equation 13) is used,
The calculation shown in (Equation 14) is performed to compensate for the phase error θe included in the output S (nT) of the baseband differential detection circuit 8.

[0023]

[Equation 14]

When the noise of the phase compensation circuit 13 is zero, the compensation range is -π <θe <π (-fR / 2 <Δf <fR / 2). Output of phase compensation circuit 13 Se (nT) = Ie (nT)
In the decision circuits 14 and 15, + jQe (nT) is Δφ = π / 4 when the reception signal point Δφ (x mark) exists in the first quadrant on the I and Q planes as shown in FIG. Δφ = 3π / 4 when present in the quadrant, and Δφ = when present in the third quadrant
-3π / 4, if it exists in the 4th quadrant, Δφ = −π / 4 is determined (determination value Δφi: ◯ mark), and its output is further converted to binary serial data by the decoder 16 and received data output Output from terminal 17.

As described above, also in the conventional TDMA data receiving apparatus, the phase error caused by the frequency offset is estimated by correlating the received data after the baseband delay detection with the known sync word at the time of frame synchronous reception. However, the compensation, that is, automatic frequency control (AFC) can be performed.

[0026]

However, in the above-mentioned conventional TDMA data receiving apparatus, when the section of the sync word of the received data is distorted due to the influence of noise or fading, a complex correlation value with a known sync word is obtained. There is a problem that the estimation accuracy of the phase error due to the frequency offset given as is deteriorated, and if the estimated value is used for the phase compensation, the received data in the slot is deteriorated.

The present invention is intended to solve such a conventional problem by taking a correlation between received data after baseband differential detection and a known sync word, and using the complex correlation value and the correlation power value. , High precision automatic frequency control (A
FC).

[0028]

In order to achieve the above-mentioned object, the present invention results from frequency offset by correlating received data after baseband differential detection with a known sync word at the time of frame sync reception. In a TDMA data receiver that compensates for phase errors and performs automatic frequency control, is the value of the correlation power | Ψ | supplied from the correlation calculation circuit greater than or less than a set threshold value? And a correlation power determination circuit that supplies the determination result as a control signal to a slot-to-slot averaging circuit to be described later, according to a control signal from the correlation power determination circuit,
If the value of the correlation power | Ψ | exceeds the threshold value, the complex correlation value Ψ is fetched from the correlation calculation circuit, and the average value is calculated between it and the value of the complex correlation value Ψ obtained in the past reception slot. Ψa is calculated, and as a result, the average value Ψa is calculated as the phase error θ due to the frequency offset at the local oscillator of the quadrature detector.
When the value of the correlation power | Ψ | is less than the threshold value, the complex correlation value Ψ obtained in the current reception slot is considered to be unreliable and is supplied to the phase compensation circuit as the information of the estimated value of e. Is ignored and the value of the complex correlation value Ψ obtained in the previous reception slot is adopted as the estimated value of the phase error θe in the current reception slot, and the complex correlation value Ψ obtained in the past reception slot is calculated.
And the average value Ψa is calculated, and as a result, the average value Ψa is calculated.
Is added to the phase compensating circuit.

[0029]

Therefore, according to the present invention, the complex correlation value with a known sync word is calculated, and at the same time, the correlation power thereof is calculated, and the reliability of the complex correlation value as an estimated value of the phase error caused by the frequency offset is high. Whether it is high or low is judged from the value of the correlation power, and when the reliability is low, the estimated value is excluded and the complex correlation value obtained in the reception slot immediately before is calculated as the phase error θe of the current reception slot. Adopted as an estimate,
Further, the phase error is estimated with high accuracy by obtaining the average value with the estimated value obtained in the past reception slot, and the automatic frequency control (AFC) is performed.

[0030]

FIG. 1 is a block diagram showing the configuration of a TDMA data receiving apparatus according to an embodiment of the present invention. This is, as an example, the same .pi. / 4 shift QPS as the conventional example shown in FIG.
The case of receiving a K modulated wave signal is also applicable to a TDMA data receiving apparatus for differentially encoded N-phase PSK (N = 4, 8, 16, ...) Modulated wave.

The same functional blocks as those in FIG. 4 are designated by the same reference numerals, and the description thereof will be omitted. However, functionally different blocks will be described.

The correlation calculation circuit 9 in this embodiment outputs a known signal output from the I / Q signal and a later-described sync word generation circuit 10 for the sync word section of the I / Q signal output from the baseband delay detection circuit 8. The complex correlation value Ψ between the baseband signal values corresponding to the synchronization word and its correlation power | Ψ | are calculated, and the value of the complex correlation value Ψ is calculated by the local oscillator 5
Is supplied to the inter-slot averaging circuit 12, which will be described later, as information on the estimated value of the phase error θe due to the frequency offset at
Further, the value of the correlation power | Ψ | is supplied to the correlation power determination circuit 11 described later as reliability information of the phase error information.

The correlation power determination circuit 11 and the inter-slot averaging circuit 12 described above are additional circuits that characterize the present invention. Here, the correlation power determination circuit 11 determines whether the value of the correlation power | Ψ | supplied from the correlation calculation circuit 9 exceeds the set threshold value or is less than the threshold value, and The determination result is supplied as a control signal to an inter-slot averaging circuit 12 described later.

The inter-slot averaging circuit 12 described above responds to the control signal from the correlation power determination circuit 11 if the correlation power | Ψ | exceeds a threshold value. The complex correlation value Ψ is taken in from 9 and the average value Ψ is obtained with the value of the complex correlation value Ψ obtained in the past reception slot.
a is calculated, and as a result, the average value Ψa is supplied to the phase compensation circuit 13 described later as information of the estimated value of the phase error θe due to the frequency offset in the local oscillator 5, and the correlation power |
If the value of Ψ | is less than the threshold value, the complex correlation value Ψ obtained in the current reception slot is considered to be unreliable and this value is ignored, and the complex correlation value obtained in the previous reception slot is ignored. Ψ
Is used as the estimated value of the phase error θe in the current receiving slot, and the average value Ψa is calculated with the value of the complex correlation value Ψ obtained in the past receiving slot. Is supplied to a phase compensation circuit 13 described later.

The phase compensating circuit 13 uses the average value Ψa supplied from the inter-slot averaging circuit 12 to calculate the phase error θe due to the frequency offset contained in the output signals I and Q of the baseband delay detection circuit 8. To compensate.

Next, the operation of this embodiment will be described based on FIG. 1 with reference to FIG. 3. In the receiving operation of the conventional TDMA data receiving apparatus shown in FIG. π / 4 shift QPSK
This embodiment is the same until the known sync word (numerical expression 1 to several 10) output from the sync word generating circuit 10 based on the modulated wave signal is output. Therefore, the operation will be described below. Note that the phase diagram on the IQ plane appears as a phase rotation in a fixed direction for each symbol as shown in FIG.

First, for the reception data S (nT) after the baseband differential detection in each reception slot in the baseband differential detection circuit 8, the 1st to Lth symbols
Suppose there is a sync word at (S (0) -S ((L-1) T)). At this time, the correlation calculation circuit 9 calculates the complex correlation value Ψ and its correlation with the known synchronization word Si (kT) as shown in (Equation 15) and (Equation 16) for the section of the S (nT) synchronization word. Calculate the power | Ψ |

[0038]

[Equation 15]

[0039]

[Equation 16]

On the other hand, considering the influence of noise and fading superimposed on the received data, S (nT) in the above (Equation 9) is expressed again as (Equation 17).

[0041]

S (nT) = exp (j (Δφ (nT) + δ (nT) + θe) where δ (nT) in (Equation 17) is a time-dependent error component caused by noise or fading. At this time, since k = 0, 1, ..., And, S (kT) at L-1 in (Equation 15) is a synchronization word, the above (Equation 10),
From (Equation 17), the following relation holds.

[0042]

S (kT) = exp (j (Δφi (kT) + δ (kT) + θe) (k = 0, 1, ... L-1) Therefore, (Equation 10) and (Equation 18) are changed to ( Substituting into (Equation 15) and (Equation 16), the following results are obtained.

[0043]

[Formula 19]

[0044]

[Equation 20]

In (Equation 19) and (Equation 20), when δ (kT) = 0,

[0046]

Ψ = exp (jθe)

[0047]

| Ψ | = 1, the correlation power | Ψ | shows the maximum value 1, and the correct information is obtained as the estimated value of the phase error θe in the complex correlation value Ψ. On the other hand, when δ (kT) ≠ 0, from (Equation 20),

[0048]

[Expression 23] | Ψ | <1 and the result including the estimation error θe is obtained as the value of the complex correlation value Ψ, as shown in (Expression 19). Therefore (Equation 21) ~
From the result of (Equation 23), the correlation power | Ψ |
It can be seen that can be used as reliability information indicating whether or not it can be trusted as the information of the estimated value of the phase error θe due to the frequency offset. Here, the correlation power determination circuit 11 determines that the value of the complex correlation value Ψ is reliable when the value of the correlation power | Ψ | exceeds the threshold value, and the value of the correlation power | Ψ | If it is less than the value, it is determined that the value of the complex correlation value Ψ has a large error and is unreliable, and the result is supplied to the inter-slot averaging circuit 12 as a control signal.

[0049]

[Outer 1]

That is,

[0051]

[Equation 24]

Set as follows.

[0053]

[Outside 2]

[0054]

[Equation 25]

[0055]

[Outside 3]

[0056]

[Equation 26]

When the noise of the phase compensation circuit 13 is 0, the compensation range is −π <θe <π (−fR / 2 <Δf <fR / 2). Output of phase compensation circuit 13 Se (nT) = Ie (nT)
In the decision circuits 14 and 15, + jQe (nT) is Δφ = π / 4 when the received signal point exists in the first quadrant on the I and Q planes, and when it exists in the second quadrant as shown in FIG. Δφ =
3π / 4, Δφ = −3π / 4 when present in the third quadrant,
When it exists in the 4th quadrant, it is determined that Δφ = −π / 4,
Further, its output is converted into binary serial data by the decoder 16 and output from the reception data output terminal 17.

As described above, according to the above-described embodiment, the complex correlation value Ψ with the known synchronization word is obtained, and at the same time, the correlation power │Ψ│ is calculated, and the phase of the complex correlation value Ψ caused by the frequency offset is calculated. Whether the reliability is high or low as an estimated value of the error is determined from the value of the correlation power | Ψ |, and when the reliability is low, the estimated value is excluded and the complex correlation obtained in the preceding reception slot. The value Ψ is used as the estimated value of the phase error θe in the current receiving slot, and the average value with the estimated values obtained in the past receiving slots is obtained to estimate the phase error with high accuracy and perform automatic frequency control. (AFC) can be performed.

[0059]

As described above, the TDMA of the present invention.
The data receiving device calculates the complex correlation value with the known sync word, and at the same time, calculates the correlation power, and correlates whether the complex correlation value is high or low as the estimated value of the phase error caused by the frequency offset. Judging from the power value, when the reliability is low, the estimated value is eliminated and the complex correlation value obtained in the immediately preceding receiving slot is adopted as the estimated value of the phase error θe in the current receiving slot. By obtaining the average value with the estimated value obtained in the past reception slot,
It is possible to estimate a highly accurate phase error and perform automatic frequency control (AFC).

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a TDMA data receiving apparatus according to an embodiment of the present invention.

FIG. 2 is a phase diagram when a frequency offset is generated in the local oscillators of FIGS. 1 and 4.

FIG. 3 is a phase diagram of the output of the determination circuit after performing the phase compensation of FIGS.

FIG. 4 is a block diagram showing a configuration of a conventional TDMA data receiving device.

[Explanation of symbols]

1 ... Antenna, 2 ... Reception root Nyquist bandpass filter (RNBPF), 3 ... Limiter amplifier, 4 ...
Quadrature detector, 5 ... Local oscillator, 6, 7 ... A / D converter, 8 ... Baseband delay detection circuit, 9 ... Correlation calculation circuit, 10 ... Synchronization word generation circuit, 11 ... Correlation power determination circuit, 12 ... Inter-slot averaging circuit, 13 ... Phase compensation circuit, 14, 15 ... Judgment circuit, 16 ... Decoder, 17 ... Received data output terminal.

Claims (1)

[Claims] 1. A TDMA data reception for performing automatic frequency control by compensating a phase error caused by a frequency offset by correlating received data after baseband differential detection and a known synchronization word during frame synchronous reception. In the device, it is determined whether the value of the correlation power | Ψ | supplied from the correlation calculation circuit exceeds the set threshold value or is less than the set threshold value. Depending on the correlation power determination circuit supplied to the averaging circuit and the control signal from the correlation power determination circuit, if the value of the correlation power | Ψ | The average value Ψ is taken from the value of the complex correlation value Ψ obtained in the past reception slot by taking in the value Ψ.
a is calculated, and as a result, the average value Ψa is supplied to the phase compensation circuit as the information of the estimated value of the phase error θe due to the frequency offset at the local oscillator of the quadrature detector, and the correlation power |
If the value of Ψ | is less than the threshold value, the complex correlation value Ψ obtained in the current reception slot is considered to be unreliable and this value is ignored, and the complex correlation value Ψ obtained in the previous reception slot is The value is adopted as the estimated value of the phase error θe in the current reception slot, and the average value Ψa is calculated with the value of the complex correlation value Ψ obtained in the past reception slot. A TDMA data receiving device characterized in that an inter-slot averaging circuit supplied to a phase compensation circuit is added.