JPH07296514A - Digital signal reproducing device - Google Patents

Abstract

PURPOSE:To prevent a slice level fro, moving to a cross point with a different eye pattern. CONSTITUTION:In a comparator 23, a reproduced RF signal equalized based on the slice level where a correction variable supplied from an asymmetry detection circuit 26 and the slice level supplied from the slice level 24 are added, that is, corrected in an adder 25 is binarized. In the asymmetry detection circuit 26, the correction variable is decided from the regenerative binarized data from the comparator 23 and a reproduced clock from a PLL generation circuit 27 to be supplied to the adder 25. In a discriminated 28, a reproduced signal is generated from the regenerative binarized data and the reproduced clock.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal reproducing device which can be applied to all devices having a function of reproducing digital data, such as an optical disk device, a magnetic tape device and a magnetic disk device.

[0002]

2. Description of the Related Art For example, in a magneto-optical disk device, fluctuations in recording sensitivity of media, fluctuations in recording light power,
The length of the recorded mark fluctuates due to factors such as fluctuations in the environmental temperature, causing asymmetry of the mark length, that is, asymmetry. On the other hand, the clock used for processing the reproduced data is formed based on the edge information of the reproduced and binarized data.

As described above, due to the asymmetry, the phase of the reproduction clock is deviated, and the length of the data itself deviates from the normal length. As a result, the reproduction data cannot be read correctly. That is, since asymmetry becomes a major factor that worsens the error rate, suppressing asymmetry is a very important technique.

Conventionally, when recording binarized data, a mark `+ 1` of a recording code is kept for a long time t.
So that the ratio of `-1 'where there is no mark is 1: 1,
A modulation method that does not have a direct current component to be modulated, such as EFM
(Eight to Fourteen Modulation) Modulation is known. In this case, whether the binarized data is biased to the + side by integrating the recording code during the time t,
The asymmetry correction is performed by detecting whether there is a bias toward the − side and calculating the amount of asymmetry correction (the amount of deviation of the actual slice level from the optimum slice level for detecting the optimum mark length) by the detection.

[0005]

Here, as a method for detecting asymmetry, binarized data and an output obtained by delaying a PLL clock reproduced from the binarized data by a 1/4 channel clock cycle are exclusively used. It proposes an asymmetry detection method that detects whether the center value is biased to the + side or to the − side by performing a logical sum. FIG. 9 shows the relationship between the error voltage and the mark shift amount at this time.

As another method for detecting asymmetry, the phase is determined from the phase relationship between the rising clock reproduced from the rising edge of the binary data and the falling clock reproduced from the falling edge of the binary data. It proposes an asymmetry detection method that detects whether the center value is biased to the + side or to the − side by performing comparison. FIG. 10 shows the relationship between the error voltage and the mark shift amount at this time.

9 and 10, the error voltage is -T / 2≤ | (mark length detected)-
(Appropriate mark length) | In the range of T / 2, it changes linearly. However, beyond this range, the error voltage folds back. Therefore, when the asymmetry correction as described above is performed in the state of exceeding this range, FIG.
In some cases, the slice level was moved to a different cross point indicated by the dotted line instead of the normal cross point indicated by the solid line of the eye pattern shown in FIG.

Therefore, according to the present invention, the slice level can be moved to the regular cross point, and (1,
7) An object of the present invention is to provide a digital signal reproducing device capable of effectively detecting asymmetry and performing asymmetry correction even in a modulation method having a DC component such as RLL (Run Length Limit) recording. .

[0009]

SUMMARY OF THE INVENTION The present invention is directed to a lead-in area in which a pulse signal of a predetermined frequency having a duty ratio of 50% is recorded in front of a data area of a predetermined length, or a signal in a modulation method having no DC component. Is a digital signal reproducing apparatus for reproducing a recording medium having a pull-in area in which is recorded, comparing means for reproducing data reproduced from the recording medium with a slice level to obtain reproduced binary data, and pull-in. In the region, the reproduced binary data is integrated to detect the asymmetry, and based on the detected asymmetry, the first asymmetry correction means for performing the asymmetry correction, and in the data region, the asymmetry correction means. A PLL for generating a reproduction clock synchronized with the reproduction binary data, and a PLL
Means for synchronizing the reproduced binarized data with the reproduced clock from, the reproduced clock, and the reproduced reproduced binarized data, asymmetry is detected, and based on the detected asymmetry, It is a digital signal reproducing device characterized by comprising a second asymmetry correcting means for performing asymmetry correction.

[0010]

The digital signal reproducing apparatus according to the present invention can efficiently perform asymmetry correction of a signal recorded by digital data.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment for performing asymmetry correction according to the present invention will be described in detail below with reference to the drawings.
FIG. 1 shows a schematic block diagram of an asymmetry correction circuit. An RF signal reproduced from the recording medium (hereinafter referred to as a reproduced RF signal) is supplied to the input terminal indicated by 1. The supplied reproduction RF signal is supplied to the equalizer 2,
The EQ signal from the equalizer 2 is supplied to the comparator 3.

Here, in the adder 5, the asymmetry detection section 6 detects asymmetry, and the detected asymmetry is supplied from the asymmetry detection section 6 to the asymmetry correction section 7. In the asymmetry correction unit 7, a correction amount corresponding to the detected asymmetry is set, and the set correction amount is supplied to the adder 5. The adder 5 adds the slice level supplied from the slice level 4 and the correction amount supplied from the asymmetry correction unit 7. That is, the slice level supplied from slice level 4 is corrected.

In the comparator 3, the EQ signal supplied from the equalizer 2 is binarized with the slice level supplied from the adder 5 as a reference. This comparator 3
The reproduced binarized data output from is PLL (Phase Lo
cked Loop) generation circuit 8 and discriminator 9. A reproduction clock is generated in the PLL generation circuit 8 to which the reproduction binarized data is supplied, and the reproduction clock is P
It is supplied from the LL generation circuit 8 to the discriminator 9. Discriminator 9
Is a circuit for outputting the reproduced binary data from the comparator 3 in synchronization with the reproduced clock from the PLL generation circuit 8. Reproduced data is generated from the discriminator 9 and taken out from the output terminal 10.

FIG. 2 shows an example of the recording format of the recording medium according to the present invention. The present invention is applicable to a recordable recording medium (for example, MO disk, magnetic tape, etc.) or a read-only recording medium (CD-ROM).
Etc.) can be applied. FIG. 2A shows a recording pattern recorded in the pull-in area 11.
The position of the pull-in area 11 may be determined at the time of recording or may be pre-formatted on the recording medium in advance.

FIG. 2B shows a recording format recorded on the recording medium. The pull-in area 11 is an area for adjusting the slice level, and this area is 2
Recorded data having a duty ratio of 50%, such as a T pattern or a 4T pattern, is repeatedly reproduced. The data area 12 has a DC component (not DC-free), and is recorded in a recording format such as (1,7) RLL recording as an example. Here, the recording pattern recorded in the pull-in area 11 is written with the same laser power as when it was written in the data area 12.

FIG. 2C shows the relationship between the slice level and the time t. In this example, the asymmetry correction is performed in the pull-in area 11 so that the slice level gradually shifts to the proper slice level, that is, the slice level shifts so that the duty ratio becomes 50%. In the data area 12, the slice level becomes an appropriate slice level, and the asymmetry correction is efficiently performed regardless of whether or not it has a DC component (DC free), and the data recorded in the data area 12 can be reproduced. it can.

Here, FIG. 3 is a block diagram of an embodiment of a single PLL type asymmetry correction circuit. 21
An RF signal reproduced from the recording medium (hereinafter referred to as a reproduction RF signal) is supplied to the input terminal indicated by. The supplied reproduction RF signal is supplied to the equalizer 22 and is supplied to the comparator 23 as an EQ signal from the equalizer 22.

In the comparator 23, the slice level 2
The EQ signal supplied from the equalizer 22 is binarized with the slice level supplied from 4 as a reference. The reproduced binary data output from the comparator 23 is
It is supplied to the asymmetry detection circuit 26, the PLL generation circuit 27, and the discriminator 28. A reproduction clock is generated in the PLL generation circuit 27 to which the reproduction binarized data is supplied, and the reproduction clock is supplied from the PLL generation circuit 27 to the asymmetry detection circuit 26 and the discriminator 28.

In the asymmetry detection circuit 26, the reproduction clock is supplied from the PLL generation circuit 27, and the supplied reproduction clock is delayed by 1/4 channel clock (T represents a channel clock cycle, and is hereinafter referred to as T / 4 clock). ), And after the asymmetry is detected from the reproduced binary data from the comparator 23, the correction amount is supplied to the adder 25. In the adder 25, the slice level is corrected by adding the correction amount supplied from the asymmetry detection circuit 26 to the slice level supplied from the slice level 24.

The corrected slice level is supplied to the comparator 23, which binarizes the EQ signal as described above. Discriminator 28
Is the PLL for the reproduced binary data from the comparator 23.
This is a circuit for outputting in synchronization with the reproduction clock from the generation circuit 27. Reproduced data is generated from this discriminator 28 and taken out from the output terminal 29.

The detailed configuration of the asymmetry detection circuit 26 will be described with reference to FIG. The reproduced binarized data is supplied from the terminal 31 to the EXOR circuit 33 and the LPF 37, and the reproduced clock (T / 4 clock) is supplied from the terminal 32 to the EXOR circuit 33. In the EXOR circuit 33, the exclusive binary OR of the reproduced binary data and the reproduced clock (T / 4 clock) is performed, and the data subjected to the exclusive OR is supplied to the LPF 34. In the LPFs 34 and 37, the supplied data is integrated, and it is detected whether it is biased to the + side or the − side with respect to the central value (optimal value).

In the gain adjusting circuits 35 and 38, L
Due to the bias detected in PF34 and 37,
The correction amount is set. The correction amount set by the gain adjusting circuit 35 is supplied to the input terminal a of the switch 36, and the correction amount set by the gain adjusting circuit 38 is supplied to the input terminal b of the switch 36. In switch 36, terminal 39
The correction amount, which is switched by the switching signal supplied from the switch 36, is supplied to the switch 36.
Is taken out from the output terminal 40 via. The extracted correction amount is supplied to the adder 25 in FIG.

The switch switching signal supplied from the terminal 39 is, for example, a gate signal generated from the preformatted signal.

Here, in the pull-in area 11 in FIG. 2, the reproduced binary data is output from the output terminal 40 via the LPF 37, the gain adjusting circuit 38, and the switch 36 as a correction amount. In the data area 12, the reproduction binarized data and the reproduction clock are output from the output terminal 40 via the EXOR circuit 33, the LPF 34, the gain adjusting circuit 35, and the switch 36, and the correction amount is output. That is, in the pull-in area 11, the correction amount is output from the input terminal b of the switch 36, and in the data area 12, the input terminal a of the switch 36.
The correction amount is output from.

FIG. 5 is a block diagram showing a different embodiment of the single PLL type asymmetry detection circuit. The reproduction RF signal supplied from the recording medium is supplied to the equalizer 22 via the input terminal 21, and E from the equalizer 22 is supplied.
The Q signal is supplied to the subtractor 41. In the subtractor 23, the correction amount supplied from the asymmetry detection circuit 26 and the EQ signal supplied from the equalizer 22 are calculated. This controls the center level of the EQ signal,
That is, the corrected EQ signal is output to the comparator 23.
Is supplied to.

In the comparator 23, the slice level 2
The corrected EQ signal is binarized with reference to the slice level supplied from No. 4. The binarized data is reproduced from the comparator 23 as reproduced binarized data, and the asymmetry detection circuit 26 and the PLL generation circuit 2 are used.
7 and the discriminator 28. PL as described above
The L generation circuit 27 generates a reproduction clock, and the asymmetry detection circuit 26 detects asymmetry from the reproduction binarized data and the reproduction clock (T / 4 clock) and outputs the correction amount. The discriminator 28, to which the reproduced binarized data and the reproduced clock are supplied, generates reproduced data and takes it out from the output terminal 29.

Next, FIG. 6 shows a dual (double) PLL.
FIG. 3 is a block diagram of an embodiment of a type asymmetry correction circuit. Reference numeral 51 denotes an input terminal, to which a reproduction RF signal reproduced from the recording medium is supplied. The reproduction RF signal supplied from the input terminal 51 is supplied to the equalizer 52, and the equalizer 52
Then, it is supplied to the comparator 53 as an EQ signal.
In the comparator 53, the EQ supplied from the equalizer 52
The signal is binarized with the slice level supplied from the slice level 54 as a reference. Here, the slice level supplied to the comparator 53 is added with the correction amount supplied from the asymmetry detection circuit 56 in the adder 55.

The reproduced binary data is supplied from the comparator 53 to the edge detection circuit 57, the asymmetry detection circuit 56, and the discriminator 60. In the edge detection circuit 57,
A rising edge and a falling edge are detected from the supplied reproduced binary data, the detected rising edge is supplied to the PLL 58, and the falling edge is supplied to the PLL 59. The PLL 58 generates a reproduction clock from the supplied rising edge,
In the LL 59, a reproduction clock (hereinafter, referred to as an inverted reproduction clock) which is the inverted clock reproduced from the supplied falling edge is generated.

The reproduced clock generated in the PLL 58 is generated by the asymmetry detection circuit 56 and the discriminator 60.
The inverted reproduction clock generated in the PLL 59 and supplied to the asymmetry detection circuit 56 and the discriminator 60. The reproduced clock from the PLL 58 is supplied as a set pulse and the inverted reproduced clock from the PLL 59 is supplied as a reset pulse. In the asymmetry detection circuit 56, asymmetry is detected and a correction amount is set, as will be described later. , To the adder 55.

In the adder 55, as described above, the correction amount is added to the reference slice level in the comparator 53. The discriminator 60 is a circuit for outputting the reproduction binary data from the comparator 53 in synchronization with the reproduction clock from the PLL 58 and the inverted reproduction clock from the PLL 59. Reproduced data is generated from the discriminator 60 and is taken out from the output terminal 61.

Here, FIG. 7 is a block diagram showing the detailed structure of the asymmetry detection circuit 56 described above. The reproduced clock is supplied from the input terminal 71, and the inverted reproduced clock is supplied from the input terminal 72. In the phase comparator 73, the supplied reproduction clock is used as a set pulse and the supplied inverted reproduction clock is used as a reset pulse to generate an output signal, which is supplied to the LPF 74. The LPF 74 integrates the supplied output signal and detects the deviation of the supplied output signal from the center value.

A correction amount is set for the detected bias in the gain adjusting circuit 75, and the set correction amount is supplied to the input terminal a of the switch 76. The switch 76 is switched by the switching signal supplied from the terminal 80, and the signal supplied to the input terminal a of the switch 76 and the input terminal b of the switch 76 is output to the output terminal 81 via the output terminal c of the switch 76. Taken from. The extracted correction amount is supplied to the adder 55 in FIG. Here, the correction amount supplied to the input terminal b of the switch 76 is such that the reproduction binary data supplied from the input terminal 77 is L
It is supplied via the PF 78 and the gain adjusting circuit 79.

Here, in the pull-in area 11 in FIG. 2, the reproduction binary data is output from the output terminal 81 via the LPF 78, the gain adjusting circuit 79, and the switch 76 as a correction amount. In the data area 12, the reproduction binarized data and the reproduction clock are output from the output terminal 81 via the phase comparator 73, the LPF 74, the gain adjusting circuit 75, and the switch 76, and the correction amount is output. That is, the pull-in area 1
In 1, the correction amount supplied to the input terminal b of the switch 76 is output, and in the data area 12, the correction amount supplied to the input terminal a of the switch 76 is output.

FIG. 8 shows a dual (double) PL.
It is a block diagram which shows another Example of an L-type asymmetry correction circuit. The reproduction RF signal reproduced from the recording medium is input via the input terminal 51 and supplied to the equalizer 52. The reproduced RF signal supplied is the E signal from the equalizer 52.
The Q signal is supplied to the subtractor 82. In the subtractor 82, the EQ signal supplied from the equalizer 52 is corrected by the correction amount supplied from the asymmetry detection circuit 56.

In the comparator 53, the corrected E
Binarization is performed according to the reference slice level supplied from the slice level 54 of the Q signal. Reproduced binary data is supplied from the comparator 53 to the edge detection circuit 57, the asymmetry detection circuit 56, and the discriminator 60. As described above, the edge detection circuit 57 detects the rising edge and the falling edge, and the PLL
The reproduced clock is generated at 58, and the inverted reproduced clock is generated at the PLL 59.

The asymmetry detection circuit 56 supplied with the reproduction clock, that is, the set pulse and the inverted reproduction clock, that is, the reset pulse, detects asymmetry and supplies the correction amount to the subtractor 82. Discriminator 6
At 0, the reproduction clock, the inverted reproduction clock, and the reproduction binary data are supplied, and the reproduction data is taken out from the output terminal 61.

Although an equalizer is used in the above embodiment, this equalizer is not always required.

[0038]

By using the present invention, the slice level can be moved to the correct cross point of the eye pattern, accurate asymmetry correction can be performed, and the reproduction error rate can be improved.

Further, by improving the reproduction error rate, it is possible to obtain effects such as an improvement in recording density of the digital data recording / reproducing apparatus, an increase in recording time, and an improvement in reliability.

[Brief description of drawings]

FIG. 1 is a schematic diagram of an example of a single PLL type asymmetry detection circuit according to the present invention.

FIG. 2 is a schematic diagram of an embodiment of a signal format according to the present invention.

FIG. 3 is a block diagram of an example of a single PLL type asymmetry detection circuit according to the present invention.

FIG. 4 is a block diagram of an example of an asymmetry detection circuit according to the present invention.

FIG. 5 is a block diagram of an example of a single PLL type asymmetry detection circuit according to the present invention.

FIG. 6 is a block diagram of an embodiment of a dual (double) PLL type asymmetry detection circuit according to the present invention.

FIG. 7 is a block diagram of an example of an asymmetry detection circuit according to the present invention.

FIG. 8 is a block diagram of an embodiment of a dual (double) PLL type asymmetry detection circuit according to the present invention.

FIG. 9 is a schematic diagram illustrating an example of a relationship between an error voltage and a mark shift amount.

FIG. 10 is a schematic diagram illustrating an example of a relationship between an error voltage and a mark shift amount.

FIG. 11 is a schematic diagram illustrating an example of a relationship between cross points of eye patterns.

[Explanation of symbols]

 22 Equalizer 23 Comparator 24 Slice Level 26 Asymmetry Detection Circuit 27 PLL Generation Circuit 28 Discriminator

Claims (4)

[Claims] 1. A pull-in region in which a pulse signal of a predetermined frequency having a duty ratio of 50% is recorded or a pull-in region in which a signal is recorded by a modulation method having no DC component is provided in front of a data region of a predetermined length. A digital signal reproducing apparatus for reproducing a recording medium, comprising: comparator means for comparing reproduced data reproduced from the recording medium with a slice level to obtain reproduced binary data; and reproducing the reproduced data in the pull-in area. The asymmetry is detected by integrating the binarized data, and the first asymmetry correcting means for performing asymmetry correction based on the detected asymmetry, and the reproduction from the comparator means in the data area. A PLL for generating a reproduction clock synchronized with the binarized data; A means for synchronizing the reproduced binary data with a reproduction clock, an asymmetry is detected from the reproduced clock and the reproduced reproduction binary data, and based on the detected asymmetry. And a second asymmetry correcting means for performing asymmetry correction. 2. The digital signal reproducing apparatus according to claim 1, wherein a cycle of the reproduction clock is T in the pull-in area.
Then, the digital signal reproducing apparatus is characterized in that it comprises means for bringing the slice level close to the optimum slice level within a range not exceeding ± T / 2 from the optimum mark length. 3. The digital signal reproducing apparatus according to claim 1 or 2, wherein the slice level is corrected by the first asymmetry correcting means and the second asymmetry correcting means. A digital signal comprising: a slice level correcting means for comparing the slice level generated by the slice level correcting means with the reproduced data to obtain the reproduced binary data. Playback device. 4. The digital signal reproducing apparatus according to claim 1 or 2, wherein instead of the correction made to the slice level,
It is characterized by comprising reproduction data correction means for performing the correction on the reproduction data, and comparator means for comparing the corrected reproduction data with the slice level to obtain the reproduction binary data. Digital signal reproducing device.