JPH07271671A - Cache device - Google Patents

Abstract

PURPOSE:To making the capacity (area) of a cache and an error check circuit smaller than that of a cache system with ECC. CONSTITUTION:The check circuit 7 makes an error check on an address array output 106 and on read data 107 read out with a cache index address 103 at a request 105, and outputs a check result 108. A hit decision circuit 6 decides a cache hit by using a cache comparison address 104 as the output of an address register 2, the address array output 106, and the check result 108. A write control circuit 5 use a request 105 and the check result 108 and outputs an address hold signal 110 and invalid data 111 so as to make the data of a word specified with a cache index address 103 ineffective when the check result 108 indicates an error at the time of a store request.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache device, and more particularly to a cache device for performing fault handling.

[0002]

2. Description of the Related Art Fault processing in a conventional cache device has an ECC and performs error correction by hardware control and continues the processing, or performs error detection by a parity check method and then temporarily suspends the processor.
The diagnostic processor is started, error processing is performed, then restarted, and the operation that caused the error is restarted (hereinafter referred to as retry processing).

In the conventional fault processing in a parity check type cache device, a test is carried out by a diagnostic processor, an intermittent fault or a fixed fault is investigated, and in the case of a fixed fault, the cache is separated.

[0004]

In order to have ECC in the fault processing in the conventional cache device, it is necessary to have information bits necessary for error correction in the cache and also have an error correction circuit.

Therefore, there is a problem that the capacity (area) of the cache and the amount of hardware for error checking increase as compared with the parity check method.

In the case of the parity check method, since the diagnostic processor is activated and error processing is performed, the processor must be temporarily stopped, and there is a problem that the processing performance of the processor is significantly reduced due to the error processing.

When an error occurs, the processor is temporarily stopped, the diagnostic processor is activated, retry processing is performed, and it is determined whether the failure is an intermittent failure or a fixed failure. Therefore, the processing capability of the processor decreases.

Further, there is a problem that the performance is deteriorated when the intermittent failure similar to the fixed failure cannot be repaired and the cache is separated.

[0009]

A cache device according to the present invention comprises a request register for storing a memory request, an address register for storing a memory address, an address array indexed by the output of the address register, and the address register. Data array indexed by the output of the address register, and an error in the output of the address array when the content of the request register indicates a store request, and an address array when the content of the request register indicates a read request And a check circuit for checking the output of the data array, and when the output of the check circuit indicates that there is no error, a match is detected between the output of the address array and the output of the address register to detect a cache hit or miss. Detect and check the above If the output of the path indicates an error, all of the hit judgment circuits are regarded as mishits, the output of the request register, the output of the address register, the output of the hit judgment circuit, and the output of the check circuit. Write data and a write control circuit for creating a hold instruction for the address register.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. The cache device shown in FIG. 1 uses a request register 1 for storing a memory request 101, an address register 2 for storing a memory request address 102, and an address having a cache index address 103, which is one output of the address register 2, as a word address. Error check and request 105 of array 3 and data array 4 and address array output 106
And the cache index address 103, and the read result 107 is checked for errors, and the check result 1
Check circuit 7 for outputting 08 and address register 2
Another output of the cache comparison address 104
And address array output 106, check result 108
Hit judgment circuit 6 for judging cache hits using
When using the request 105 and the check result 108 and the check result 108 indicates an error at the time of the store request, the address hold signal 110 and the invalid data are invalidated to invalidate the data of the word specified by the cache index address 103. The write control circuit 5 that outputs 111, the timer 20 that is started when the check result 108 indicates an error, the display register 21 that indicates that the timer 20 is operating, and the display register 21 that the timer 20 operates. The OFF register 23 and the OFF register 23, which are set when the check result 108 indicates an error (continuous error signal 204) and output a cache pseudo OFF signal 206 indicating a cache disconnection state, Similarly, the continuous error signal 204 An error counter 24 that performs a count operation, a timer comparison circuit 22 that outputs a timer match signal 203 that resets the timer 20, the display register 21, and the OFF register 23 when the timer 20 reaches a predetermined value, and the error counter 24 And a counter comparison circuit 25 that issues a cache fixed failure report 207 when a predetermined value is reached.

Next, the operation of this embodiment will be described.

When the memory request 101 and the memory request address 102 are sent, they are stored in the request register 1 and the address register 2, respectively, and the address array 3 and the data array 4 are indexed by the cache index address 103.

The check circuit 7 outputs the address array output 1
When the request 105 is a store request, only the parity check of the address array output 106 is performed, and in the case of a read request, the address array output 106 and the read data 107 and the request 105 are input. Reading data 10
7 parity check is performed.

The result of the above check operation is reported to the hit determination circuit 6 and the write control circuit 5 as a check result 108.

The hit decision circuit 6 inputs the cache comparison address 104, the address array output 106 and the check result 108 and makes a hit decision. Check result 108
Indicates no error, and the cache comparison address 10
When 4 and the address array output 106 match, a cache signal is reported by the hit signal 109, and when the check result 108 indicates that there is an error, the cache signal is unconditionally reported by the hit signal 109.
By performing such control, when an error occurs in the cache, the memory request is in the form of cache bypass, and the processing can be continued without stopping the processor.

The write control circuit 5 requests the request 105.
If the request 105 is a store request, the address hold signal 11 is input.
When 0, the address register 2 is held, the invalid data 111 is transmitted, and the word in the cache having the error is inhibited. Otherwise, if the next read request hits when the error is an intermittent failure, the read data becomes invalid because the data update by the store request that caused the error has not been performed. Further, at the time of a read request, the address array and the data array are updated with new data as in the case of a normal cache hit, so that no contradiction occurs due to the next request.

As described above, in the parity check type cache device, error processing can be performed by hardware without stopping the processor, and it is possible to prevent a decrease in the processing capability of the processor due to a cache error.

When the check result 108 indicates that there is an error, the timer 20 starts operating and the display register 21 indicating that the timer 20 is operating is set.

If the check result 108 indicates that there is an error again while the display register 21 indicates that the timer 20 is operating, the OFF register 23 is set by the continuous error signal 204 and the error counter 24 is set.
To count up.

When the OFF register 23 is set, the cache pseudo OFF signal 206 temporarily disconnects the cache.

The timer comparison circuit 22 receives the timer output 202 and detects a match while comparing it with a predetermined value. When the timer output 202 and the default value match, a timer reset instruction 203 is output to instruct to stop the operation of the timer 20, reset the display register 21, and reset the OFF register 23.

When the OFF register 23 is reset, the cache is incorporated again and the normal operation is resumed.

Further, the counter comparison circuit 25 receives the error counter output 205, compares it with a predetermined value, and detects a match. When the error counter output 205 matches the default value, the fixed failure report 207 completely disconnects the cache.

As described above, when the cache has an intermittent failure, the OFF register 23 is not set (the check result 108 does not report that there is an error again while the timer 20 is operating), which reduces the processing performance of the processor. In most cases, error handling is performed.

When the cache is an intermittent failure similar to a fixed failure, the OFF register 23 disconnects the cache several times, but recovers until the fixed failure report 207 is established (until the error counter 24 matches a predetermined value). By doing so, it is possible to operate in the assembled state, so that it is possible to prevent a decrease in processing capability as compared with the case of completely separating.

[0027]

As described above, according to the present invention,
Since error processing can be performed without having an ECC in the cache, the capacity (area) of the cache and the error check circuit can be made smaller than in the cache system with ECC.

Further, since the error processing is performed by hardware, the time required for the error processing can be shortened as compared with the conventional case and the processing performance of the processor is hardly affected.

Further, according to the present invention, when a cache error occurs, it is possible to distinguish between a fixed failure and an intermittent failure by hardware, and in particular, the cache is opened at a certain time interval before the fixed failure is reported. Since the cache status is tested while disconnecting or incorporating, it is possible to teach an intermittent failure similar to a fixed failure and reduce unnecessary cache disconnection.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

[Explanation of symbols]

 1 request register 2 address register 3 address array 4 data array 5 write control circuit 6 hit determination circuit 7 check circuit 101 memory request 102 memory request address 103 cache index address 104 cache comparison address 105 request 106 address array output 107 read data 108 check Result 109 Hit signal 110 Address hold signal 111 Invalid data 201 Display register output 202 Timer output 203 Timer reset instruction 204 Continuous error signal 205 Error counter output 206 Cache pseudo OFF signal 207 Fixed fault report

Claims (2)

[Claims] 1. A request register for storing a memory request, an address register for storing a memory address, an address array indexed by the output of the address register, a data array indexed by the output of the address register, If the content of the request register indicates a store request, an error in the output of the address array,
When the content of the request register indicates a read request, a check circuit for checking the output error of the address array and the data array, and when the output of the check circuit indicates no error, the address array A hit determination circuit that detects the cache hit and the miss by performing a match detection between the output and the output of the address register, and when the output of the check circuit indicates that there is an error, a hit determination circuit, and the output of the request register and the A cache device comprising: a write control circuit that creates write data of the address array and a hold instruction of the address register by output of the address register, output of the hit determination circuit, and output of the check circuit. . 2. A timer activated by an output from the check circuit, a display register for indicating that the timer is operating, and an operation of the timer when the value of the timer reaches a predetermined value. A timer comparison circuit for instructing stop and reset and reset of the display register, an error counter that performs a count operation by the output of the display register and the check circuit, and fixing of the cache when the error counter reaches a predetermined value. 2. The cache device according to claim 1, further comprising a timer comparison circuit that reports a failure, and an OFF register that temporarily disconnects the cache.