JPH05210597A - Patrol circuit for storage device - Google Patents

Abstract

PURPOSE:To easily decide a fixed error and a software error by the patrolling operation of the storage device and to decrease the frequency of error interruption to a maintenance diagnostic device. CONSTITUTION:The patrolling operation is performed with a patrol address generated by a patrol counter 40 while updated in order in each patrol cycle; if an uncorrectable error is detected, its correction data are rewritten in the patrol address and the patrol address is inhibited by an AND gate 80 from being updated at the same time. In the following patrol cycle, patrolling is performed for the same patrol address and in the further following patrol cycle, the patrol address is updated. In response to the detection of the uncorrectable error, the syndrome of the error is held in a register 50 and a comparing circuit 60 compares its contents with the syndrome of a correctable error in the following cycle. When they match each other, the fixed error is decided and its report 21 is made for the 1st time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a patrol circuit of a memory device, and more particularly to an error reporting system for controlling a patrol address and detecting a maintenance diagnostic device when a correctable 1-bit error is detected.

[0002]

2. Description of the Related Art In recent years, the degree of integration of memory LSIs has dramatically increased, and along with this, memory cells for storing information have been miniaturized. The miniaturization of memory cells has made it impossible to ignore soft errors in which the stored contents are temporarily destroyed by α rays. Since this soft error is not a fixed failure of the memory cell, the stored contents can be restored by writing the information again.

As one of measures against this soft error, when an error in which information can be read and corrected by one address is detected, rewriting of data after error correction is repeated at all addresses to accumulate soft errors. There is a memory patrol method to prevent this. This memory patrol is controlled by the hardware included in the storage device and operates by interrupting the normal write / read access at regular intervals, which causes a decrease in memory access performance.

Further, when the memory patrol method is not adopted, when the storage device reports a correctable error to the maintenance diagnosis device at the time of read access, the maintenance diagnosis device collects error address information and performs a read operation to the address. There is also a method of preventing the accumulation of soft errors by performing an operation of writing back the error-corrected data sent from the storage device to the storage device.

In the conventional patrol method for preventing the accumulation of soft errors, the patrol address is updated every patrol cycle regardless of whether or not there is a correctable error in the patrol operation, so that the error is a fixed error or a soft error. It is necessary to wait for the patrol address to complete a cycle to determine whether or not it is complete.

In this case, the error address of the detected correctable error and the syndrome information are all stored in the maintenance diagnostic device, and when the storage device makes a new error interrupt, it is determined whether or not it matches the stored information. There is a drawback in that the processing load due to the interruption of the maintenance diagnostic device increases for making the determination. Also, the determination of fixed error becomes slower.

[0007]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a patrol circuit for a storage device, which can reduce the load on the maintenance diagnosis device and can quickly determine a fixed error.

[0008]

A patrol circuit of a memory device according to the present invention comprises means for controlling the activation and cycle of a patrol cycle for patrol of a memory, means for generating a patrol address while sequentially updating it, and means for generating the patrol address from the memory. Means for detecting and correcting a correctable error in the read data,
When the correctable error is detected by the patrol operation by the patrol address, the correction data at that time is rewritten to the patrol address and a means for suppressing the update of the patrol address at the same time, and an update is suppressed in the subsequent patrol cycle. Means for performing patrol again for the patrol address thus generated and for updating the patrol address in a subsequent patrol cycle.

[0009]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram of a patrol system according to an embodiment of the present invention, FIG. 2 is a block diagram showing a configuration example of the patrol circuit of FIG. 1, and FIG. 3 is a time chart of patrol operation.

The embodiment shown in FIG. 1 comprises a patrol circuit 1, an address circuit 2, a timing circuit 3, a memory array 4 and a data circuit 5.

The patrol circuit 1 is a circuit for controlling the patrol cycle, generating the patrol address, and activating the patrol cycle. The address circuit 2 is a circuit that selects an address for normal memory access and a patrol address and supplies the selected address to the memory array 4.

The timing circuit 3 is a circuit for generating a tamming signal for performing a write / read operation to the memory array 4. The data circuit 5 is a circuit which has an error correction circuit and generates a timing signal for performing a write / read operation to the memory array 4. The data circuit 5 is a circuit which has an error correction circuit and performs write data input to the memory array 4 and read data error check / correction.

FIG. 2 is an example of a detailed block diagram of the patrol circuit 1. The patrol address hold register 1 is shown in FIG.
0, error interrupt register 20, patrol cycle circuit 3
0, patrol address counter 40, syndrome register 50, comparison circuit 60, and gate circuits 70 and 80. The operation of these circuits will be described with reference to the time chart of FIG.

FIG. 3A is a time chart of a case in which no error is detected in the patrol operation. The patrol address is i, i + 1,
It is sequentially updated to i + 2.

The patrol cycle circuit 30 outputs a patrol start signal 31 and a patrol cycle signal 101 at intervals of the patrol cycle T. The patrol address counter 40 performs the operation of updating the patrol address 100 by the patrol start signal 31 because the correctable error 501 is not set in the patrol address hold register 10.

The address circuit 2 outputs a patrol cycle signal.
Patrol address 100 is set to 101 by memory array 4
Supply to. The timing circuit 3 also supplies the read timing to the memory array 4.

FIG. 3B shows a time chart of a case where a fixed error is detected in the patrol operation. When the data circuit 5 detects a correctable error at the patrol address i, the correctable error signal 501 and the syndrome 502 are sent to the patrol circuit 1.

The correctable error signal 501 is set in the patrol address hold register 10, and the gate circuit 80 is closed by the address hold signal 11, so that the patrol address 100 is not updated in the next patrol cycle and the address i continues. The syndrome 502 is set in the syndrome register 50.

In parallel with these operations, the data circuit 5 corrects the error data and sends it as the write data 500 to the memory array 4, and rewrites to the address i by the write timing signal from the timing circuit 3. However, since the address i is a fixed error, the error cannot be erased by this rewriting operation.

When the next patrol cycle operates in this state, the read data 400 from the address i is again checked by the data circuit 5 to detect the second correctable error.

As a result, in the patrol circuit 1, the first-time syndrome held in the syndrome register 50 and the two-circuit syndrome 502 are compared by the comparison circuit 60, and the syndrome coincidence signal 61 is output.

The gate circuit 70 receives the address hold signal 1
The fixed error interrupt register 20 determines that the same correctable error is detected at the same address by the first, the syndrome coincidence signal 61 and the second correctable error signal 501.
Is set, and a fixed error interrupt signal 21 is used to interrupt the maintenance diagnostic device. After that, the address hold register 10 and the syndrome register 50 are reset. Therefore, in the next patrol cycle, the patrol address counter 40 sets the patrol address 100 to i + 1.
The address is updated.

FIG. 3C is a time chart of a case where an intermittent error (soft error) is detected in the patrol operation. The operation for the first correctable error at the patrol address i is the same as in the fixed error case described above.

No error is detected in the second patrol operation at the patrol address i. This is due to a soft error, and the data on the memory array 4 was correctly recovered by the first rewriting operation. Therefore, in the patrol circuit 1, the fixed error interrupt register 20 is not set and the error interrupt signal 21 is not interrupted.

That is, in the case of a soft error (intermittent error), the recovery in the storage device has been successful, so no report is made to the maintenance diagnostic device. The next patrol cycle is i +
The address is updated to address 1.

[0027]

As described above, according to the present invention, when a correctable error is detected in the patrol operation, the update of the patrol address is stopped and the same address is accessed during the next patrol operation to store the stored data. It is possible to easily determine whether the error is a fixed error or a soft error (intermittent error) by checking whether the error has been recovered.

Further, by interrupting the maintenance diagnosis apparatus only when the result of this determination is a fixed error, it is possible to reduce the number of interruptions and reduce the load of the failure diagnosis operation of the maintenance diagnosis apparatus.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a specific example of the patrol circuit of FIG.

FIG. 3A is an operation time chart in the case of no error, FIG. 3B is an operation time chart in the case of fixed error,
(C) is an operation time chart in the case of a soft error (intermittent error).

[Explanation of symbols]

 1 Patrol Circuit 2 Address Circuit 3 Timing Circuit 4 Memory Array 5 Data Circuit 10 Patrol Address Hold Register 20 Error Interrupt Register 30 Patrol Period Circuit 40 Address Counter 50 Syndrome Register 60 Comparison Circuit

Claims (2)

[Claims] 1. A means for controlling activation and a cycle of a patrol cycle for performing patrol of a memory, a means for generating a patrol address while sequentially updating the patrol address, and detecting and correcting a correctable error of read data from the memory. Means, when the correctable error is detected by the patrol operation by the patrol address, means for suppressing the update of the patrol address at the same time as rewriting the correction data at that time to the patrol address, and in the subsequent patrol cycle, A patrol circuit of a storage device, comprising means for performing patrol again for the patrol address whose update is suppressed, and controlling so as to update the patrol address in a subsequent patrol cycle. 2. Means for retaining the syndrome of the correctable error in response to detection of the correctable error, and means for comparing the contents of this syndrome with the contents of the correctable error syndrome in the subsequent patrol cycle. 2. The patrol circuit for a storage device according to claim 1, further comprising means for making a fixed error report by considering that a fixed error has occurred when a match is detected by comparison.