JPH0724861Y2 - Color burst PLL circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention relates to a color burst PLL circuit that outputs a continuous wave signal synchronized with a color burst signal of a composite color video signal.

[Prior art] Conventionally, in a high quality television receiver called EDTV (Extended Definition Television) or IDTV (Improved Definition Television), a color burst signal of a composite color video signal received by a color burst PLL circuit is received. A continuous wave signal having a frequency of N times in synchronization with is formed as an operation reference clock signal, and based on the clock signal, a Y /
Processing such as C separation (luminance / color separation) is performed.

And a color burst PLL that forms the continuous wave signal
The circuit is normally formed by a dedicated integrated circuit, for example, a digital processing circuit using a DPLL LSI of model number MB87041, in order to perform accurate signal formation with stable operation.

Next, the color burst PL of the digital processing circuit configuration
The L circuit will be described with reference to FIG. 1 showing an embodiment of the present invention.

In FIG. 1, (1) is an input terminal for a composite color video signal, (2) is an A / D converter connected to the input terminal (1),
(3) is L of the model number MB87041 connected to the converter (2)
A phase comparator composed of SI, (4) is a D / A converter connected to the phase comparator (3), (5) is a voltage controlled oscillator (hereinafter referred to as VCO) connected to the converter (4), (6) is an output terminal of the continuous wave signal, and (7) is a frequency divider for dividing the continuous wave signal of the output terminal (6) into 1 / N and feeding it back to the phase comparator (3).

(8) is converter (2), (4), phase comparator (3), VCO
(5), continuous wave output section formed by frequency divider (7), (9)
Is a sync separator connected to the input terminal (1), and (10) is a sampling pulse generator connected to the sync separator (9),
The sampling pulse described later is output to the phase comparator (3).

Then, the received composite color video signal is input terminal (1)
Is input to the converter (2) and the sync separation unit (9), and the composite color video signal digitally converted by the converter (2) is input to the phase comparator (3) and separated and extracted from the composite color video signal. The synchronizing signal pulse is input to the generator (10).

By the way, the conventional color burst PLL circuit generator (1
0) is an inverter (1
1) and two falling trigger type monostable multivibrators (hereinafter, monostable multivibrator is referred to as monomulti) (12) and (13) are connected in series by a gate pulse generation circuit (14), The pulse of the synchronization signal is inverted by the inverter (11), and a mono-multi (pulse leading edge) of the pulse edge of the falling edge of the output signal of the inverter (11), that is, the leading edge of the leading edge of the synchronizing signal (pulse leading edge). 12) is triggered.

In Fig. 4, (R1) and (C1) are resistors and capacitors for the time constant of the monomulti (12), (R2) and (C2) are resistors and capacitors for the time constant of the monomulti (13), (Vcc) is a positive voltage power supply terminal.

In the mono-multis (12) and (13), (A) is a falling trigger terminal, (B) is a rising trigger terminal, (Q),
() Is an output terminal.

Then, each time the mono-multi (12) is triggered, it operates with the time constant of the resistor (R1) and the capacitor (C1), and each horizontal scanning period (hereinafter referred to as "horizontal scanning period") with reference to the rising pulse edge of the horizontal synchronizing signal. In order to extract the color burst signal of the horizontal scanning period is referred to as H), a signal for time adjustment having a pulse width shorter than 1 / 2H is output to the monomulti (13).

Furthermore, the mono-multi (13) is triggered at each falling edge of the output signal of the mono-multi (12), and the mono-multi (13) outputs the extracted pulse as a gate pulse for extracting the color burst signal to the phase comparator (3). Is output.

Then, the phase comparator (3) takes in the output signal of the converter (2) in the color burst period and takes out the color burst signal of the received composite color video signal based on the sampling pulse of the generator (10).

Furthermore, the phase comparator (3) compares the phase of the extracted color burst signal (hereinafter referred to as the received color burst signal) with the output signal of the frequency divider (7), and uses the phase of the received color burst signal as a reference. , The phase difference between the received color burst signal and the output signal of the frequency divider (7) is detected, and the digital signal of the phase difference is output.

Further, the digital signal of the phase difference of the phase comparator (3) is converted into an analog signal by the converter (4), and the converter (4) outputs the VCO to the VCO.
The voltage signal ΔV proportional to the phase difference is output to (5).

The VCO (5) controls the oscillation frequency by the voltage signal ΔV, and outputs an output signal controlled so that the voltage signal ΔV becomes zero, that is, a continuous wave signal as an operation reference clock signal at the output terminal (6 ) Is output.

At this time, change the frequency of the continuous wave signal to the color burst frequency.
The output signal of the VCO (5) is fed back to the frequency divider (7) as well, in order to obtain N · fsc that is N times fsc (3.58 MHz in the NTSC system).

The frequency divider (7) digitally converts the input signal to N
The frequency is divided and the N divided signal of the output signal of the VCO (5) is output to the phase comparator (3).

Therefore, the continuous wave signal at the output terminal (6) is PLL controlled to a signal of frequency N · fsc synchronized with the received color burst signal.

[Problems to be solved by the device]

By the way, in the case of the conventional color burst PLL circuit, the monomulti (1) of the generation circuit (14) forming the generation section (10) is used.
Since the time constants of 2) and (13) are set to less than 1 / 2H, the generator is also generated in the vertical sync pulse period of the vertical blanking period and the equivalent pulse periods before and after it, as described below. (10) outputs sampling pulse.

That is, the composite color video signal of the input terminal (1) is NTSC
In the case of the signal of the system, when the vertical blanking period Tv of FIG. 5 (a) is reached, the sync separation unit (9) is also used in the equivalent pulse period Ta, vertical synchronization pulse period Tb, and equivalent pulse period Tc of each 3H in order from the start end. ) Separates and extracts each pulse as a pulse of the synchronization signal, and the pulses at the interval of 1 / 2H shown in FIG. 7B are input to the monomulti (12).

Then, each time the input pulse falls, the monomulti (1
2) is triggered and monomulti (12) to monomulti (1
The pulse shown in Fig. 5 (c) is output to 3), and the sampling pulse is continuously output from the monomulti (13) to the phase comparator (3) at intervals of 1 / 2H as shown in Fig. 3 (d). Will be output.

At this time, the phase comparator (3)
The output signal of the converter (2) is extracted as a color burst signal, but since the color burst signal is not superimposed in the periods Ta, Tb, Tc, the phase comparator (3) extracts noise and malfunctions.

Therefore, the PLL control of the output section (5) is disturbed by the noise, frequency fluctuation (frequency jitter) occurs in the continuous wave signal at the output terminal (6), and the continuous wave signal operates as a reference. However, there is a problem that the operation of the video processing circuit is disturbed and various adverse effects are exerted on the reproduction processing.

An object of the present invention is to provide a color burst PLL circuit having a digital processing circuit configuration which prevents noise from being extracted during a vertical blanking period.

[Means for Solving the Problems]

In order to achieve the above purpose, the color burst PL of the present invention
The L circuit includes a sampling pulse generator that outputs sampling pulses at the timing of the color burst signal of the video signal with reference to the pulse leading edge of the sync signal separated and extracted from the composite color video signal, and the sampling pulse. A burst signal from the video signal, and a continuous wave output unit that outputs a continuous wave signal having a frequency N times the burst signal by PLL control of the extracted burst signal. A monostable multivibrator unit that outputs the sampling pulse by the trigger of the pulse leading edge to the generation unit, an equivalent pulse period of a vertical blanking period shorter than the horizontal scanning period of the video signal, and a pulse of a vertical synchronization pulse period. A retriggerable monostable marker set to a time constant longer than the interval and triggered by the leading edge of the pulse. And a trigger inhibit signal during an equivalent pulse period of a vertical blanking period and a vertical synchronization pulse period in which the output of the monostable multivibrator is logically processed and the pulse leading edge continues at a shorter interval than the horizontal scanning period. And a trigger prohibition unit that prohibits the trigger of the monostable multivibrator unit by the signal.

[Action]

In the color burst PLL circuit of the present invention configured as described above, the trigger prohibition signal of the trigger prohibition unit causes
Triggering of the monostable multivibrator by the pulse leading edge of the sync signal is prohibited during the equivalent pulse period and vertical sync pulse period of the vertical blanking period where the color burst signal is not superimposed.

Therefore, the stable operation based on the digital processing circuit configuration allows the sampling pulse generation section to output the continuous wave output section to the continuous wave output section only during the period excluding the equivalent pulse period and the vertical synchronization pulse period, that is, the period in which the color burst signal is superimposed. The sampling pulse is output accurately at the timing of the burst signal, and the PLL control of the continuous wave output section is performed accurately while preventing disturbance due to noise.

〔Example〕

One embodiment will be described with reference to FIGS. 1 to 3.

The configuration of FIG. 1 is different from the conventional one in that the generation unit (1
0) is formed by the gate pulse generating circuit (15) shown in FIG.

In FIG. 2, (16) and (17) are two mono-multis forming the monostable multivibrator part (18), and (19) is two re-triggerable mono-multis (20) and (21). , A flip-flop (22), an inverter (23), and two NAND gates (24) and (25).

In addition, each mono-multi (16), (17), (20), (21)
Have trigger terminals (A), (B), output terminals (Q), () and a falling reset terminal (R),
And resistors for time constant (R3), (R4), (R5), (R6)
Also, capacitors (C3), (C4), (C5), (C6) are externally attached.

The flip-flop (22) has a set terminal (S) for rising trigger, a reset terminal (R) and an output terminal (Q).
And an RS flip-flop.

Then, based on the composite color video signal of the input terminal (1), when a pulse of the sync signal is input from the sync separator (9) to the generator (10), the leading edge of the output pulse of the sync separator (9) (16) at the rising edge of (pulse leading edge)
Is triggered.

Further, the mono-multi (17) is triggered by the trailing edge of the signal of the output terminal (Q) of the mono-multi (16) unless the prohibition section (19) holds the trigger-inhibition.

At this time, the time constants of the monomultis (16) and (17) are set to be almost the same as the time constants of the monomultis (12) and (13) of FIG. , The multi-multi (17) is triggered with a color burst period delayed from the trigger of the multi-multi (16), and the multi-multi (17) outputs the same sampling pulse as the mono-multi (13) in Fig. 4 (). To the phase comparator (3).

Further, the pulse of the sync signal of the sync separator (9) is connected to the trigger terminal (B) of the mono-multi (20) and the NAND gate (24),
It is input to (25), and the monomulti (20) is triggered by the rising edge of the pulse leading edge of the synchronizing signal.

Furthermore, the signal from the output terminal () of the mono-multi (20) is input to the trigger terminal (B) of the mono-multi (21), and the signal from the output terminal () of the mono-multi (20) rises to the mono-multi (21). Is triggered.

In the case of the NTSC method, paying attention to the fact that the pulse interval of the sync signal changes from 1H to 1 / 2H only during the equivalent pulse period and the vertical sync pulse period, and the mono-multi (20) and (21) can be re-triggered. The period of time constant τ of the monomulti (20) is shorter than the horizontal scanning period and is longer than the equivalent pulse period of the vertical blanking period and the pulse width of the vertical synchronizing pulse period, that is, 1 / 2H. <Τ <1H and the time constant period τ ′ of the monomulti (20) is 1H−τ <τ ′ <1H
Is set to.

Therefore, in each period excluding the equivalent pulse period and the vertical synchronization pulse period, that is, in the period in which the pulse interval of the synchronization signal of the synchronization separation unit (9) is 1H, monomulti ( 20) is triggered and is delayed by a period τ from the trigger of monomulti (20).
1) is triggered.

And the signal of the output terminal (Q) of the mono-multi (21) is
Directly input to the NAND gate (24) and the inverter (23)
It is inverted by and input to the NAND gate (25).

At this time, 1H <τ + τ ′ <2H, and only the output signal of the NAND gate (24) falls to the low level and the output signal of the NAND gate (24) is held at the high level for each pulse of the synchronizing signal.

Then, the output signals of the NAND gates (24) and (25) are input to the set terminal (S) and the reset terminal (R) of the flip-flop (22), and the flip-flop is caused by the fall of the output signal of the NAND gate (24). (22) is kept in the set state, and the flip-flop (22) outputs the output terminal (Q).
Signal is held high.

Furthermore, the signal of the output terminal (Q) of the flip-flop (22) is input to the reset terminal (R) of the monomulti (17), but since the level of the signal is held at the high level, the monomulti (16) The monomulti (17) operates according to the signal from the output terminal (Q).

Next, when the composite color video signal of the input terminal (1) enters the vertical blanking period Tv of FIG. 3 (a) and the pulse interval of the sync signal of the sync separator (9) changes to 1 / 2H, Before the time constant period τ ′ of the monomulti (21) has elapsed from the trigger of the multi (20), that is, in the high level period of the signal of the output terminal (Q) of the monomulti (21), the sync separation unit (9)
The next pulse of the sync signal of is the NAND gate (24), (2
Entered in 5).

Therefore, the output signal of the NAND gate (25) falls to the low level at each pulse of the synchronization signal, and the flip-flop (2
2) flips to reset state and flip-flop (22)
The signal at the output terminal (Q) becomes low level and a trigger inhibit signal is generated.

Then, the mono-multi (17) is held in the reset state by the low level trigger inhibit signal of the signal of the output terminal (Q) of the flip-flop (22), and the signal of the output terminal (Q) of the mono-multi (16) is held. The trigger of the mono-multi (17) based on this is prohibited, and the signal of the output terminal () of the mono-multi (17) is held at the high level.

That is, in the equivalent pulse period Ta, the vertical synchronization pulse period Tb, and the equivalent pulse period Tc of the vertical blanking period Tv, the monomulti (2
0), (21) output terminal () signal, inverter (2
The output signal of 3) becomes as shown in FIGS. 3B, 3C and 3D, respectively, and the output signals of the NAND gates 24 and 25 and the output terminal (Q) of the flip-flop (22) are shown. ) Signals become as shown in (e), (f) and (g) of the same figure respectively, and as a result, the output terminal () of the mono-multi (17)
Signal is held at a high level as shown in FIG. 7 (h), and the sampling pulse is no longer output from the generator (10).

When the equivalent pulse period Tc ends, the pulse interval of the synchronization signal becomes 1H again, the trigger inhibit signal turns off, the reset of the monomulti (17) is released, and the monomulti (16)
The signal at the output terminal (Q) of the triggers the monomulti (17) again.

Therefore, in the equivalent pulse period Ta, Tc and the vertical synchronizing pulse period Tb in which the color burst signal is not superimposed, the output of the sampling pulse of the generator (10) is stopped, and the period Ta, Tb,
The malfunction of the phase comparator (3) due to the sampling of Tc noise is prevented.

In the above-mentioned embodiment, the case of the composite color video signal of the NTSC system has been described, but the present invention can be applied to the case of the composite color video signal other than the NTSC system.

Further, the monostable multivibrator section (18) and the trigger prohibiting section (19) may have different configurations from those of the embodiment.

Further, it is needless to say that the present invention can be applied not only to a device such as a high image quality television receiver that digitally performs video processing, but also to a television receiver that analogically performs video processing, for example.

[Effect of device]

Since the present invention is configured as described above, it has the following effects.

Based on the setting of the time constant of the retriggerable monostable multivibrator, the trigger prohibition unit logically processes the output of the monostable multivibrator, and the equivalent pulse period of the vertical blanking period where the color burst signal is not superimposed, the vertical A trigger inhibit signal is formed during the sync pulse period. This inhibit signal inhibits the trigger of the monostable multivibrator part due to the pulse leading edge of the sync signal, and the period other than the equivalent pulse period and the vertical sync pulse period, that is, the color burst. The sampling pulse is accurately output at the timing of the color burst signal from the sampling pulse generator to the continuous wave output section only during the period in which the signals are superimposed. Prevents disturbance due to noise during PLL control, minimizes frequency fluctuations of continuous wave signals, To prevent operation disturbance of the video processing circuit of the stage is capable of performing good reproduction process.

[Brief description of drawings]

1 to 3 show an embodiment of a color burst PLL circuit of the present invention, FIG. 1 is an overall block diagram, FIG. 2 is a detailed block diagram of a sampling pulse generator, and FIG. 3 (a). ~
(H) is a timing chart for explaining the operation, FIG. 4 is a block diagram of the sampling pulse generating section of the conventional color burst PLL circuit, and FIGS. 5 (a) to 5 (d) are timings for explaining the operation of FIG. It is a chart. (8) …… Continuous wave output section, (10) …… Sampling pulse generation section, (18) …… Monostable multivibrator section, (19)…
… Trigger prohibition section.

Claims (1)

[Scope of utility model registration request] 1. A sampling pulse generator for outputting a sampling pulse at the timing of a color burst signal of the video signal with reference to a pulse leading edge of a sync signal separated and extracted from a composite color video signal, and a sampling pulse by the sampling pulse. A continuous wave output unit for extracting the burst signal from the video signal and outputting a continuous wave signal having a frequency N times that of the burst signal by PLL control of the extracted burst signal; A monostable multivibrator unit that outputs the sampling pulse by the trigger of the pulse leading edge to the generation unit, an equivalent pulse period of a vertical blanking period shorter than the horizontal scanning period of the video signal, and a pulse of a vertical synchronization pulse period. A retriggerable unitary safety triggered by the leading edge of the pulse set to a time constant longer than the interval A multivibrator, wherein the output of the monostable multivibrator is subjected to logic processing, and the pulse leading edge is continuous at a shorter interval than the horizontal scanning period; A color burst PLL circuit comprising: a trigger prohibition signal that generates a trigger prohibition signal and prohibits the trigger of the monostable multivibrator section by the signal.