JPH07221767A - Cell processing unit for duplicate atm exchange - Google Patents

Abstract

PURPOSE:To keep cell synchronization at system changeover and to prevent a cell from a standby system from being received by implementing cell synchronization at a receiver side with respect to a cell processing unit of a duplicate ATM exchange. CONSTITUTION:Synchronization cell transmission sections 6a, 6b provided in duplicate subscriber processing sections 2a, 2b send signaling cells (b), (c) to a concerned system and send synchronization cells (b'), (c') resulting from converting a header of a signaling cell to other system simultaneously. Cell abort processing sections 7a, 7b of the duplicate signaling cell processing sections 4a, 4b identify a header to abort the synchronization cells (b'), (c') and to provide an output of only the signaling cell of the concerned system. Then number of cells passing through both the systems is selected the same to synchronize cells appearing at output ports of each signaling cell processing section thereby preventing missing and duplicate cells at system changeover.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cell processing device for a duplexed ATM switch.

[0002]

2. Description of the Related Art A conventional technique will be described below with reference to FIG. FIG. 5 is a diagram showing a circuit configuration of a conventional example, and shows a configuration of a switch (duplex ATM switch) by a duplex asynchronous transmission mode communication system.

In FIG. 5, 1 is an individual unit having a single structure, 2a and 2b are subscriber processing units having a double structure, and 3a and 3a.
b is a switch having a duplex configuration, and 4a and 4b are signaling cell processing units having a duplex configuration. 5 is a terminal device.

The signals (a) to (c) described in the circuit of FIG.
ATM cell (asynchronous transmission mode communication cell (box),
Hereinafter referred to as a cell). Note that the cell here refers to a unit data consisting of a certain fixed length, for example, 54 octets, and the cells (a) to (c) consist of signaling cells such as line control commands and transmission data. It is made from user cells.

In the individual unit 1 having a single structure, the interface between the user and the line is used, and the data transmitted from the user is assembled into a cell structure to form a duplicated cell having a low transmission rate.
(a) is created and output to the subscriber processing units 2a and 2b.

In the subscriber processing units 2a and 2b of both systems, the cell (a) and the cells from other subscribers (not shown) are respectively concentrated, and a unique signaling cell (b) or (c) is set. In addition, cells (a) + (b) or (a) + (c) with high transmission speed are created and output to the own system switches 3a and 3b, respectively.

In the switches 3a and 3b, a route is determined by the cell exchange process, and a duplicated cell having a high transmission rate is created by recombining each route, and the cell is signaled by its own system of the route. The data is output to the cell processing units 4a and 4b.

The signaling cell processing units 4a and 4b respectively receive the cells, separate the concentrated cells and recognize the destinations, and send to the terminal device 5 the duplicated cells (a) + ( b) Or send (a) + (c).

As described above, in the duplexed ATM exchange, the subscriber processing section 2a, the switch 3a, and the signaling cell processing section 4a constitute one system, and the subscriber processing section.
2b → switch 3b → signaling cell processing unit 4b constitutes another system, and cells received from both systems are input to the same terminal device 5. In this way, the two systems are connected in parallel by a device having the same function (redundant device), and if one system is the operating system (ACT), the other system is the standby system (SBY).
The operating system and the standby system are switched as required.

For each terminal device to which cells from both systems are input, for example, only cells (a) + (b) from the operating system are valid (○).
Cell from the standby system so that it is selected and received as
(a) + (c) are invalid (x) and are controlled so that they are discarded and not received.

[0011]

However, since the signaling cells added by the subscriber processing unit are different and the addition frequency is different between the operating system and the standby system, the output from the signaling cell processing unit which is the terminating device of the duplex system. The cells to be processed are not cell-synchronized, and the cells having the same cell number are output at different timings. Therefore, at the time when the switching between the active system and the standby system is performed, the cell numbers to be input to the terminal device are not consecutive, the same cell is received in duplicate, or the received cell is lost, etc. There is a problem that correct data cannot be received.

Further, the terminal must be able to receive only the cells of the operating system of the duplicated system. As described above, the cells transmitted from the individual unit to the terminal device need to receive only the cells from the operating system after passing through the duplex system, and have to pass the duplex system with the same number of cells.

According to the present invention, cell synchronization is maintained at the time of system switching and cells from the standby system are not received by synchronizing the cells on the receiving side of a duplexed ATM switch having an operating system and a standby system. The purpose is to do.

[0014]

FIG. 1 is a diagram showing a circuit configuration of an embodiment of the present invention, and FIG. 2 is a diagram showing a circuit configuration of another embodiment of the present invention. FIG. 3 is a diagram showing an embodiment in which the present invention is applied to a cell demultiplexing unit.

To achieve the above object, in the first invention, as shown in FIG. 1, the subscriber processing units 2a, 2b for multiplexing the cells from the individual unit 1 and adding the signaling cells for transmission.
And switches 3a, 3 for connecting the transmitted cells by route
b and a signaling cell processing unit that processes the received cell
In the duplex ATM mode switch in which the exchange system consisting of 4a and 4b is duplicated, and one is the operating system and the other is the standby system to perform data transmission using cells, each of the duplicated subscriber processing units 2a and 2b , The signaling cell (b), (c) is sent to its own system, and at the same time, a synchronization cell that operates a specific bit in the tag area in the signaling cell to another system
(b '), (c') is provided with a synchronous cell transmission unit 6a, 6b, and each of the duplicated signaling cell processing units 4a, 4b, by identifying the specific bit, to join the own system Synchronous cell received by another processing unit from another system and inserted
(c ') and (b') are discarded, and cell discard processing units 7a and 7b that output only the signaling cells from the own system are provided, and the number of cells passing through both systems is made the same, and each signaling cell process is performed. The cells appearing at the output ports of the units 4a and 4b are synchronized to prevent cell drop and duplication during system switching.

In the second aspect of the invention, as shown in FIG. 3, the cell discard processing unit 31 is provided in the signaling cell processing units 4a and 4b in the subsequent stage of the FIFO memory 12 for buffering and storing the received cells on a first-in first-out basis. In order to control the tag comparator 31a for discarding the synchronous cell on the output side of the FIFO memory 12 and designating the tag in the header of the synchronous cell from the outside of the cell discard processing unit 31, A fixed setting unit 32a that outputs a hardware setting value and a program setting unit 32b that outputs a program setting value are provided.

In the third aspect of the invention, as shown in FIG. 2, all the cells received from the individual unit 1 when used as a standby system are transmitted to the synchronous cell transmission units 6a and 6b of the subscriber processing units 2a and 2b. A header conversion function is added to operate the second specific bit so that it can be identified that it is via the standby system, and the cell discard processing units 7a and 7b on the receiving side identify it and receive cells from the standby system. Try to discard all.

In the fourth invention, as shown in FIG.
An input cell identification unit 33 having the same configuration as the cell discard processing unit 31 is provided in the preceding stage of the O memory 12, and a tag setting value for discarding the synchronous cell is designated by a fixed setting unit 34a of hardware setting. 34c or program setting section of program setting
34b and 34d, so that priority control of cells passing through the FIFO memory 12 is possible.

[0019]

In the configuration of the first invention shown in FIG. 1, in each of the synchronous cell transmission units 6a and 6b provided in the duplicated subscriber processing units 2a and 2b for processing transmission cells, the signaling cell is transmitted to the operating system. At the same time as sending, a synchronous cell in which a specific bit in the tag area in the signaling cell is operated is sent to the standby system, and a cell discard processing provided in the dual signaling cell processing unit 4a, 4b for processing the received cell Department
In 7a and 7b, a specific bit in the tag area in the header of the signaling cell of another system is identified, the synchronous cell is discarded, and only the signaling cell from the operating system is received.

In this way, by inserting the signaling cell of its own system as a synchronization cell into the other system, the number of cells passing through the active system and the standby system becomes the same, and cell synchronization of both systems can be achieved. On the receiving side, this synchronization cell is unnecessary and is discarded. As a result, the synchronization of the duplexer can be automatically maintained, and cell drop and duplication at the time of system switching can be prevented.

Further, in the configuration of the second invention shown in FIG. 3, a FIFO for performing first-in first-out buffering storage
A cell discard processing unit 31 having the same configuration as the cell discard processing units 7a and 7b is provided at the subsequent stage of the memory 12 so that the synchronous cells are discarded at the output side of the FIFO memory 12, and Tag comparator 31a that specifies the tag in the header
Is controlled from outside the cell discard processing unit 31.

Therefore, the set value from the fixed setting unit 32a or the program setting unit 32b is externally supplied to the tag comparator 31a.
By adding to, it becomes possible to arbitrarily specify the tag area. Further, in the configuration of the third invention shown in FIG.
An input cell identification unit 33 having the same configuration as the cell discard processing unit 31 is provided in the preceding stage of the IFO memory 12, and a fixed setting unit is provided to specify a tag setting value for identifying a cell to be discarded by the input cell identification unit. 34a, 34c or program setting section
By performing steps 34b and 34d, priority control of cells passing through the FIFO memory 12 is enabled.

[0023]

EXAMPLES Examples of the present invention will be described below with reference to FIGS. FIG. 1 is a diagram showing a circuit configuration of an embodiment of the present invention, in which a main configuration in the present invention is described. 2 is a diagram showing a circuit configuration of another embodiment of the present invention.

FIG. 3 shows an example in which the present invention is applied to a cell demultiplexing unit, and shows a part of the peripheral configuration of FIGS. 1 and 2. Hereinafter, first, FIGS. 1 and 2 will be described. In FIG. 1, 1 is an individual unit of a single structure, and 2
a and 2b are subscriber processing units having a duplex configuration. It should be noted that each of the subscriber processing units 2a and 2b has a synchronous cell transmission unit of the present invention.
Each of 6a and 6b is provided, and each of the synchronized cell transmission units 6a and 6b outputs a signaling cell to its own system and outputs a synchronized cell operated by the signaling cell to another system, and the number of passing cells of both systems. To make them the same and synchronize.

Reference numerals 3a and 3b are switches having a redundant configuration, and
a and 4b are signaling cell processing units having a duplex configuration.
Then, each of the signaling cell processing units 4a, 4b is provided with one of the cell discard processing units 7a, 7b of the present invention, and each of the cell discard processing units 7a, 7b synchronizes with the received signaling cell. Only the signaling cells of the cells are processed to be valid (○), and the synchronous cells inserted from other systems on the transmitting side are invalidated (×) and discarded.

Similar to FIG. 5, in FIG. 1, one system is formed by, for example, a subscriber processing unit 2a (synchronous cell transmitting unit 6a) → switch 3a → signaling cell processing unit 4a (cell discard processing unit 7a). For example, the subscriber processing unit 2b → switch 3b → signaling cell processing unit 4b forms the other system, and if one system is an operating system, the other system becomes a standby system. Hereinafter, it is assumed that the upper side is an operating system and the lower side is a standby system.

The signal (a) is a user cell from the individual unit, and the same signal is input to both systems. Signals (b) and (c) are working-system signaling cells, standby-system signaling cells, and signals (b ') and (c') are synchronization cells, respectively.

In the present invention, it is necessary to perform system switching in a state in which both the operating system and the standby system are always synchronized so that there is no cell drop and cell duplication during system switching. The duplexer is synchronized by using the configuration shown.

In the individual unit 1, the interface between the user and the line is taken, and the transmission data from the user is assembled into a cell to form a duplicated user cell (a) having a low transmission rate, and the user cell (a) is duplicated. Output to the subscriber processing units 2a and 2b.

In order to synchronize both the operating system and the standby system,
The synchronous cell transmission unit 6a provided in the subscriber processing unit 2a transmits the signaling cell (b) for controlling the own system to the own system, and at the same time, to the subscriber processing unit 2b of the other system, which is the standby system, as described above. The synchronous cell (b ') is transmitted at the transmission timing of the signaling cell.

This synchronization cell (b ') is identified by using the ATM header of the signaling cell (b) to be transmitted to the own system as the synchronization cell (b').
Header, that is, a certain bit in the header (1 bit in the tag area indicating the destination) is assigned to the first dedicated bit for identification, and the first dedicated bit is operated to perform signaling. Be able to identify the difference between cell (b) and sync cell (b ').

On the other hand, the subscriber processing unit 2b of the standby system generates a signaling cell (c) as a standby system and sends the signaling cell (c) to its own system, and at the same time, a synchronization cell in which the header of the signaling cell (c) is also changed. Subscriber processing unit for operation system converted to (c ')
Send to 2a.

Then, in the subscriber processing units 2a and 2b of both systems,
The synchronous cell (b ') or (c') received from the other system is added to the original transmission cell (consisting of a signaling cell and a user cell) of the own system and transmitted. As a result, the total number of cells transmitted in both systems becomes equal, and cell synchronization can be achieved on the receiving side.

The synchronization cell (b ′) added in this way,
Since (c ') is unnecessary in the terminal device 5 which is the final cell transmission destination, the cell discard processing units 7a and 7b provided on the output side of the signaling cell processing units 4a and 4b perform processing to discard. Details of the cell discard processing units 7a and 7b will be described later.

As described above, only the valid cells are output from the signaling cell processing units 4a and 4b of the active system and the standby system to the terminal device 5, and the terminal device 5 receives only the cells from the active system. It is controlled separately.

By the above operation, it is possible to secure the synchronization between the active system and the standby system, and prevent cell drop and cell duplication at the time of system switching. Next, by using the signaling cell processing units 4a, 4b and the cell discard processing units 7a, 7b of the present invention, the terminal device 5 always receives only the cells from the active system and does not receive the cells from the standby system. To do. The configuration of this embodiment will be described with reference to FIG.

In FIG. 2, the user cell (a) transmitted from the unifying unit 1 is output to the operating system and the standby system. Synchronous cell transmission unit 6b provided in the subscriber processing unit 2b of the standby system
Then, the ATM of the user cell (a) received from the individual unit 1
One bit different from the above-mentioned first dedicated bit in the header (1 bit in the tag area indicating the destination) is assigned to the second dedicated bit, and whether the cell of the operating system is displayed by displaying the second dedicated bit. It is processed so that it can be determined whether the cell is a standby cell.

Then, in the standby system, the second dedicated bit transmits the user cell (a ') indicating that it is the standby system to the signaling cell processing unit 4b via the switch 3b. In the standby subscriber processing unit 2b, the same processing is performed on the synchronization cell (b ') received from the active system and the own signaling cell (c), and the second dedicated bit is the standby system. The sync cell (b ") and the signaling cell (c") that have been changed to the display indicating that are transmitted.

Then, the subscriber processing unit 2a of the operating system does not perform the above conversion processing, but receives the user cell received from the subscriber side.
(a), the signaling cell (b) from its own system, and the synchronization cell (c ') from another system are transmitted as they are.

As a result of the above, the user cell (a) and the signaling cell (b) of the own system and the synchronous cell (c ') from the other system are sent from the operating system to the switch 3a, and the standby system The user cell (a ′) and signaling cell (c ″) of the own system and the synchronization cell (b ″) from the other system are sent to the switch 3b.

In the terminal device 5, the user cell from the operating system
(a) and signaling cell (b) only and sync cell
It is necessary to discard (c ') and not receive the user cell (a'), signaling cell (c "), and synchronization cell (b") from the standby system.

Therefore, according to the present invention, the user cell (a ') and the signaling cell transmitted from the individual unit 1 via the standby system are used.
(c ") and the synchronization cell (b") are set to the signaling cell processing unit 4b.
The cell discard processing unit 7b provided therein recognizes that the cell should be discarded using the second dedicated bit. The configuration of cell discard will be described below.

In the cell discard processing unit 7b provided in the signaling cell processing unit 4b, the values of the first dedicated bit and the second dedicated bit in the header portion of the received cell are compared with the values set in advance from the outside. Then, if they match, the synchronous cell (c ') to be discarded and the cells (a'), (c ") and (b") from the standby system are recognized, and the cells are discarded.

The synchronization bit (c ') is the cell discard processing unit.
It is the same as in Fig. 1 that it is discarded at 7a. As a result of the above,
In the terminal device 5, only the user cell (a) and the signaling cell (b) from the active system are received, and the synchronous cell (b ') and all cells (a'), (b "), (c from the standby system are received. ") Is not received and is discarded.

Next, the cell discard function provided in the signaling cell processing units 4a and 4b will be described with reference to FIG. In the circuit of FIG. 3, the input cell identification unit 33, the FIFO memory 12, and the cell discard processing unit 31 have a cell demultiplexing function.
Are connected in this order and built in as an LSI.

Here, the FIFO memory 12 temporarily holds a predetermined amount of received cells by the first-in first-out method and outputs it to the terminal device 5, and the input cell identification unit 33 and the cell discard processing unit 31 are shown in FIG. The cell discard processing units 7a and 7b shown in FIG. 2 have the same configuration and function.

Then, the cell discard processing section 31 includes a tag comparator 31a for checking a predetermined bit of the tag area in the received cell by comparing it with a set value, and a fixed setting section 32a and a program setting section 32b which will be described later. An OR gate 31b for selecting one of the two setting inputs of

The fixed setting unit 32a and the program setting unit 32b externally set a voltage level (bit value) for identifying the first dedicated bit and the second dedicated bit in the tag area of the cell. It was made possible,
The fixed setting unit 32a sets the voltage level by hardware, and the program setting unit 32b sets the voltage level by software.

In the tag comparator 31a, the FIFO memory
The cell output from 12 and the voltage level corresponding to the first dedicated bit and the second dedicated bit in the cell from the OR gate 31b are confirmed to match, and if the levels of both signals match, the cell is discarded. That is, no output cell is sent from the tag comparator 31a. If they do not match, the input cell is directly output from the tag comparator 31a as an output cell.

In addition, the cell discard processing unit 31 is replaced with a FIFO memory.
The reason for providing the 12 output side (reading side) is that the number of cells buffered and stored in the FIFO memory 12 is the same for both systems in order to achieve cell synchronization at the end of the duplex system. This is because the synchronous cell must be regarded as the number of passing cells.

Further, 31 is a cell discard processing section provided on the output side of the FIFO memory 12, 33 is an input cell identification section provided on the input side of the FIFO memory 12, and these two circuits 3
1,33 have the same configuration and the same function.

The cell discard processing section 31 of FIG. 3 is further provided with a circuit capable of externally controlling the cell discard function. That is, an AND gate 31c and a matching determination unit 31e are provided, and the AND gate 31c controls whether or not the set value from the OR gate 31b is added to the tag comparator 31a.

In the matching determination unit 31e, the OR gate 31
The output controlled by the instruction signal indicating whether or not the matching specified through d is taken is given to the AND gate 31c as an instruction to determine whether to enable the output of the OR gate 31b.

Then, in the cell discard processing section 31, fixed setting sections 32a, 32c for fixedly setting the bits by hardware so that the instruction bit for the presence or absence of the matching operation and the matching bit value can be set from the outside, and Program setting part 32b, 32 that allows variable setting by software
d is provided. As a result, cells to be discarded can be arbitrarily changed during system operation, and system operation flexibility is improved.

Similarly, the input cell identification unit 33 includes a tag comparator 33a having the same function as the cell discard processing unit 31 and an OR gate.
33b, 33d, AND gate 33c, and matching determination unit 33
e, fixed setting sections 34a, 34c and program setting section 34b,
34d and

In the input cell discriminating section 33 provided on the front side of the FIFO memory 12, the instruction from the matching determining section 33e is added to the AND gate 33c, and the set value from the OR gate 33b is set in the tag comparator 33a. Whether or not to operate the cell identification function of the input cell identification unit 33 can be arbitrarily selected by controlling whether or not to perform.

As described above, if the specific value of the header bit of the received cell is set in advance as a bit indicating the priority, the cell demultiplexing unit having the above configuration is used to set this value from the outside. By comparing with the set value
Only the important cells pass through the FIFO memory 12, non-important cells do not pass through the FIFO memory 12, and priority control of the cells passing through the cell discard processing unit 31 is performed, so that the traffic amount passing through the FIFO memory 12 is increased. It is possible to prevent the excessive.

Next, another embodiment of the present invention will be described with reference to FIG. FIG. 4 shows the cell processing apparatus of the present invention having the input cell identification unit 33, the FIFO memory 12 and the cell discard processing unit 31 shown in FIG. 3, separating the multiplexed cells from the high speed highway and sending them to the low speed highway. An embodiment used as a demultiplexing configuration will be shown.

In FIG. 4, reference numerals 21 to 2n denote demultiplexing units each including a first demultiplexing unit to an nth demultiplexing unit.
The separating section 21 to the n-th separating section 2n have the configuration shown in FIG. As shown in FIG. 4, the switch 3a (shown in FIG. 1)
The high-speed cells transmitted from the high-speed highway to the first separation unit 21 to the n-th separation unit 2n are added, and a predetermined bit indicating the destination set in the tag area of each cell is added to each of the first separation units. The input cell identification units 33 of the first separating unit 21 to the n-th separating unit 2n compare with a set value from the outside (not shown) to recognize whether or not to flow as a low speed cell to its own low speed highway.

That is, by setting the set value applied to the first separating unit 21 to the n-th separating unit 2n to a predetermined value, it becomes possible to separate the high-speed highway into a plurality of low-speed highways for transmission.

[0061]

As is apparent from the above description, according to the present invention, (1) cell drop and cell duplication at the time of system switching can be prevented with a simple hardware configuration, so that the cost is improved and the reliability is improved. be able to. (2) By making the cell discard processing unit simple and versatile, the discard processing itself can be widely used for discarding synchronous cells and discarding received cells from the standby system. (3) By providing the matching configuration of the cell discard processing unit also on the input side of the FIFO memory, it becomes possible to fetch only the necessary cells, and the cell demultiplexing function can be easily realized. Play.

[Brief description of drawings]

FIG. 1 is a diagram showing a circuit configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing a circuit configuration of another embodiment of the present invention.

FIG. 3 is a diagram showing an embodiment in which the present invention is applied to a cell demultiplexing unit.

FIG. 4 is a diagram showing a configuration of conversion from a high-speed highway to a low-speed highway.

FIG. 5 is a diagram showing a circuit configuration of a conventional example.

[Explanation of symbols]

 1 Individual unit 2a, 2b Subscriber processing unit 3a, 3b Switch 4a, 4b Signaling cell processing unit 5 Terminal device 6a, 6b Synchronous cell transmission unit 7a, 7b, 31 Cell discard processing unit 33 Input cell identification unit 12 FIFO memory 31a , 33a Tag comparator 32a, 32c, 34a, 34c Fixed setting section 32b, 32d, 34b, 34d Program setting section

Claims (4)

[Claims] 1. A subscriber processing unit (2a, 2b) for multiplexing cells from an individual unit (1) and adding a signaling cell for transmission.
And a switch (3a, which connects the transmitted cells by route)
The switching system consisting of 3b) and the signaling cell processing unit (4a, 4b) that processes the received cell is duplicated, and one is an operating system and the other is a standby system, which is a duplexed ATM that performs data transmission using cells. In the mode switch, the signaling cells (b) and (c) are sent to the own system to each of the duplicated subscriber processing units (2a, 2b), and at the same time a specific bit in the tag area in the signaling cell is sent to another system. Operated synchronous cell (b '), (c') to send the synchronous cell transmitter (6
a, 6b), and the synchronization cell received and inserted by the subscriber processing unit of the own system from another system by identifying the specific bit in each of the duplicated signaling cell processing units (4a, 4b) (c '), (b') are discarded, and cell discard processing units (7a, 7b) that output only the signaling cells from the own system are provided, and the number of cells passing through both systems is made the same, and A cell processing device for a duplicated ATM switch, characterized in that cells appearing at the output ports of the cell processing units (4a, 4b) are synchronized to prevent cell drop and duplication at the time of system switching. 2. The signaling cell processing unit (4a, 4b) is provided with the cell discard processing unit (31) at a stage subsequent to a FIFO memory (12) for performing first-in first-out buffering storage of a reception cell, and the FIFO is provided. The output of the memory (12) discards the synchronous cell, and the tag comparator (31a) for designating the tag in the header of the synchronous cell is controlled by the cell discard processing unit (3
The duplexer according to claim 1, characterized in that a fixed setting section (32a) for outputting a hardware setting value and a program setting section (32b) for outputting a program setting value are provided so as to be performed from the outside of 1). Cell processing equipment for ATM exchanges. 3. An individual unit when used as a standby system in the synchronous cell transmission unit (6a, 6b) of the subscriber processing unit (2a, 2b).
By operating the second specific bit of all cells received from (1), a header conversion function that makes it possible to identify that it is via the standby system is added, and the cell discard processing unit (7a, 7b) on the receiving side 2. The cell processing device of the duplex ATM switch according to claim 1, wherein the cell is identified by the above and all the cells received from the standby system are discarded. 4. An input cell identification unit having the same configuration as that of the cell discard processing unit (31) in a stage preceding the FIFO memory (12).
(33) is provided, and the tag setting value for discarding the synchronous cell is designated from the fixed setting section (34a, 34c) of hardware setting or the program setting section (34b, 34d) of program setting, 2. A cell processing apparatus for a duplex ATM switch according to claim 1, wherein priority control of cells passing through said FIFO memory (12) is enabled.