JPH07219720A - Semiconductor memory device and its control method - Google Patents

Abstract

PURPOSE:To provide a semiconductor memory device whose data processing efficiency is satisfactory and which can be compatible with a hard disk device. CONSTITUTION:The semiconductor memory device where a data storage device 5 is constituted by a non-volatile memory such as flash-type EEPROM and data is accessed from a host computer in a prescribed block unit by logical block address designation is provided with a first table 41 converting a logical block address from the host computer into a real block address on the real memory space of the data storage part 5 and a second table 42 managing the state of data in the real block address in accordance with the real block address.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device such as a semiconductor disk compatible with a hard magnetic disk in a conventional computer system and a control method thereof.

[0002]

2. Description of the Related Art In various computer systems, disk-shaped storage media such as magnetic disks and optical disks have been conventionally used to store and process a large amount of data. However, the drive device for driving this disk-shaped storage medium is large in size, requires a highly precise mechanism, and lacks reliability.

As an alternative to this, for example, a DRAM
Solid-state storage devices having a semiconductor memory such as an SRAM and SRAM have been studied. However, they have the drawback that they are expensive, and that they always require electric power to retain the stored data, which results in high running costs.

In order to solve this drawback, JP-A-2-29
Flash EEPR as described in 2798
An OM system has been proposed.

[0005]

However, in the proposed system, the method of writing new data while erasing the previous data in the data area of the storage unit is adopted, so that the writing of data is completed. It takes time to do so, and the processing efficiency is not good.

Further, since the data area is provided with an alternative area for storing defect data and a defect map area for managing the defect data, the usable storage area is substantially limited. In addition, since the flash EEPROM is used for the data storage unit, the number of times of writing is limited and the service life of the external storage device is limited.

The object of the present invention is to eliminate the drawbacks of the prior art, to improve the efficiency of data processing, and since it is not necessary to be aware of write restrictions, a semiconductor memory that can be handled in the same manner as a conventional hard disk. An object is to provide an apparatus and a control method thereof.

[0008]

In order to achieve the above object, the first invention is a data storage comprising a non-volatile memory which is electrically writable and electrically erasable in a predetermined unit. Unit, a control unit for controlling the data storage unit, and an input / output unit for inputting / outputting data to / from a connected host computer. In a semiconductor memory device in which is executed, a first table for converting a logical block address designated at the time of access from the higher-level computer into a real block address in a real memory space of the data storage unit, and the first table corresponding to the real block address And a second table for managing the state of the data in the real block address.

In order to achieve the above-mentioned object, a second invention is a data storage section comprising a non-volatile memory which is electrically writable and can be electrically erased in a predetermined unit, and the data storage. Control means for controlling the parts,
An input / output unit for inputting / outputting data to / from a connected host computer; and a first table for converting a logical block address designated by the host computer at the time of access to a real block address in a real memory space of the data storage unit. And a second table that manages the state of data in the real block address corresponding to the real block address, and a semiconductor memory that executes data access by specifying a logical block address from a high-order computer in fixed block units. In the control method of the apparatus, during the data read processing by the host computer, the logical block address is converted into a real block address by the first table, the data read from the converted real block is transferred to the host computer, and the host computer is During the data writing process from the By searching for an empty block in which data can be written from the block, writing the data to the empty block, and writing the real block address of the block in which the data is written to the first table, the real block address does not correspond to the logical block address. And a process of erasing data independently of the series of data writing processes described above.

In order to achieve the above object, a third aspect of the present invention is a data storage unit comprising a non-volatile memory which is electrically writable and electrically erasable in a predetermined unit, and the data storage. Control means for controlling the parts,
In a semiconductor memory device configured by a host computer connected thereto and an input / output unit for inputting / outputting data, the data access is executed from the host computer in a fixed block unit by designating a logical block address. A pointer register that stores a writable real block address at the time of writing data, and a register operation unit that sets a write destination real block address at the time of writing data to the pointer register. Is.

In order to achieve the above object, a fourth aspect of the present invention is a data storage unit comprising a non-volatile memory which is electrically writable and electrically erasable in a predetermined unit, and the data storage. Control means for controlling the parts,
In a semiconductor memory device configured by a connected high-order computer and input / output means for inputting / outputting data, in which data access is executed by logical block address designation from the high-order computer in a fixed block unit, when accessing from the high-order computer A first table for converting a designated logical block address into a real block address in the real memory space of the data storage unit; and a first table for managing the state of data in the real block address in correspondence with the real block address. In the semiconductor memory device including the table of No. 2, a first non-volatile memory in which the data storage unit can be erased in erase block units including at least one access block, and the number of writable times is greater than that of the first non-volatile memory. Large, access block or bytes below access block It is composed of a second non-volatile memory that is writable or erasable by a unit, stores the data area managed by the operating system in the first non-volatile memory, and stores the file management area such as FAT and directory in the second non-volatile memory. It is characterized by being stored in a memory.

In order to achieve the above object, a fifth aspect of the present invention is a data storage section comprising a non-volatile memory which is electrically writable and electrically erasable in a predetermined unit, and the data storage. Control means for controlling the parts,
In a semiconductor memory device configured by a connected high-order computer and input / output means for inputting / outputting data, in which data access is executed by logical block address designation from the high-order computer in a fixed block unit, when accessing from the high-order computer A first table for converting a designated logical block address into a real block address in the real memory space of the data storage unit; and a first table for managing the state of data in the real block address in correspondence with the real block address. In the semiconductor memory device including the table No. 2 and the third table storing the number of times of writing to the logical block, the data storage unit can erase in units of erase blocks including at least one access block.
And a second non-volatile memory having a writable count larger than that of the first non-volatile memory and capable of writing or erasing in an access block or in byte units less than or equal to the access block. Of the logical block addresses stored in the table are stored in the second non-volatile memory from the block having the largest number of writings, and the remaining blocks that cannot be stored in the second non-volatile memory are stored in the first non-volatile memory. It is characterized by that.

[0013]

The operation of the present invention will be described with reference to the above-mentioned aspect. By providing the first table and the second table,
The erased area can be searched and the data can be written immediately, so that it is possible to write the data faster than previously proposed and it is possible to improve the efficiency. By setting the real block address of the data write destination,
It is also possible to write data more quickly.

Further, the data storage unit is composed of two non-volatile memories having different writable times, and a sector having a high writing frequency is stored in the non-volatile memory having a large writable number. It has an advantage that a file device having a large capacity and a long device life can be realized even if a memory element having a limited number of times of rewriting is used.

Further, by making it possible to arbitrarily set the real block address of the data write destination set in the pointer register, it is possible to avoid concentration of writing to a specific real block address and prolong the life of the device. It has the advantage of being possible.

[0016]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a diagram for explaining the first embodiment.

The semiconductor disk 1 is a microcomputer 2 for controlling read / write to the flash memory and overall control.
An I / F controller 3 that realizes an interface protocol with a host computer, a work memory 4 for work, a data storage unit 5 including a plurality of flash memories (flash memory arrays), and a memory controller that executes an interface with the data storage unit 5. 6, a buffer memory 7 for temporarily storing access data with the host computer, an address bus 111 for connecting the above-mentioned units, a data bus 112,
The control signal bus 113 is mainly configured.

The microcomputer 2, the I / F controller 3, the work memory 4, the memory controller 6, and the buffer memory 7 include an address bus 111, a data bus 112,
They are connected by the control signal bus 113. Data storage unit 5
The memory controller 6 is connected to the memory controller 6 via an address bus 121, a data bus 122, and a control signal bus 123. An address bus 101, a data bus 102, and a control signal bus 103 are connected to a host computer (not shown).

Here, the address buses 101 and 111 and 121, the data buses 102 and 112 and 122, and the control signal buses 103, 113 and 123 do not necessarily correspond. Although not shown in the figure, electric power for operating the semiconductor disk 1 is supplied from the host computer to each of the components of the semiconductor disk 1.

The work memory 4 has a first table 41 for converting a logical block address designated by the host computer at the time of access into a real block address which is an actual address in the memory space in the flash memory group of the data storage unit 5. , And a second table 42 for managing the data area of the flash memory corresponding to the real block address.

The I / F controller 3 has a command register 31 for designating a process to be executed, an address register 32 for setting a logical address for data access, and a data write / write function for realizing access to a host computer. A data register 33 for reading data and a status register 34 for notifying the execution result of the processing to the host computer are provided. The host computer and the semiconductor disk execute input / output of information via these register groups.

The structure of the first table 41 and the second table 42 will be described. Like the hard disk, the semiconductor disk 1 is accessed in a certain fixed block unit, and an arbitrary data area is designated as a logical block address by the host computer. At this time, the byte unit of one block is arbitrary, but 2 ⁿ bytes are desirable. Here, a case where one block is composed of 512 bytes will be described.

The structure of the first table 41 will be described with reference to FIG. In the first table 41, as described above, the logical block address designated by the host computer for data access is the actual address in the memory space of the data storage unit 5 composed of a plurality of flash memories. It is for converting to a block address. In the figure, it is assumed that the logical block address space is mapped to the logical block addresses 0001h to FFFFh. Similarly, it is assumed that the real block address space is also mapped to the real block addresses 0001h to FFFFh. Here, for example, when the logical block address 0030h is designated as the data read destination from the host computer, the real block address 008 corresponding to the logical block address 0030h is specified by the first table 41.
8h is referred to. This is because the address 0030h of the first table 41 is read and the data stored at this address is the data indicating the real block address 0088h corresponding to the logical block address 0030h. Therefore, the corresponding data A is the real block address. 008
It is read from 8h. Thus, the first table 41
Shows the correspondence between the logical block address and the real block address which is the actual physical address, and both addresses are made to correspond one-to-one by the first table 41.

By thus passing through the first table 41, it is not necessary that the address values of the logical block address and the real block address always match.
It is possible to effectively use the memory space of the data storage unit 5.

Further, since the data of the first table 41 is generated at the time of writing to the semiconductor disk 1 and the addresses are associated with each other, a logical block address in which no data is written is, for example, the logical block address FFFFh. , The value of the predetermined area of the first table 41 becomes 0000h, indicating that there is no corresponding data in the real block address space. For reading to such a logical block address, ALL0 may be transferred to the host computer as read data.

In the example of FIG. 2, the size of the logical block address space and the size of the real block address space are the same, but the size of the logical block address space and the size of the real block address space are exactly the same. Need not be, and there is no problem if the real block address space is larger.

The second table 42 is for storing flag information for managing the state of data in the real block address in the real block address space. In FIG. 3, an “effective block” flag 01h indicating that the data in this real block address is valid is stored in an address 0088h, which is an area of the second table 42 corresponding to the real block address 0088h. . Further, when the data in the real block address is invalid like the real block address 0043h, a flag 02h indicating "invalid block" is stored. this is,
Previously, the data in this block was valid, but since it was rewritten and the data corresponding to one logical block address was set to another real block address, the data in this real block has no meaning. Shows. The "invalid block" flag also indicates that the corresponding block in the flash memory needs to be erased.

As for the real block address to which data can be written, a flag 00h indicating that it is an "empty block" like the real block address 0007h is stored. For the real block address where data cannot be written normally, the real block address 012
A flag FFh indicating a “defective block” such as 3h is stored. With these flag information,
It is possible to manage the state of the flash memory that constitutes the real block address space, and it is possible to effectively perform processing such as writing and erasing data in the flash memory. The values of these flags are examples, and may be arbitrarily set as long as they are identified so that the state of the flash memory can be managed.

Since the first table 41 and the second table 42 are information necessary for accessing the flash memory in the data storage unit 5, they are stored in the non-volatile memory. As the memory, an EEPROM or a flash memory may be used, but an FRAM is most suitable because the access speed is higher than that of the EEPROM or the flash memory and data can be rewritten in byte units. Alternatively, DRAM or SRAM may be used as the memory and the table information may be stored in the nonvolatile memory when the power is turned off. Alternatively, a method of backing up DRAM or SRAM with a battery or the like may be used.

Next, an example of a data access method with the host computer in the first embodiment (FIG. 1) will be described.

First, the case of reading data will be described.
The host computer designates a register by the address bus 101, and the data bus 102 and the control signal bus 103 address the command code indicating the read processing of the data to be executed in the command register 31 and the logical block address where the data to be read is stored. Set in register 32.
Therefore, the microcomputer 2 in the semiconductor disk 1 determines the command code in the command register 31, confirms that the data is read, and executes the data read process. After that, the execution result is reported to the host computer via the status register 34.

FIG. 4 shows an example of the read processing of these data. In FIG. 4, first, the address register 3
The logical block address set to 2 is converted by the first table 41 into a corresponding real block address in the memory space of the data storage unit 5 composed of a plurality of flash memories (S1).

Next, the corresponding data in the data storage unit 5 is read from the real block address to the buffer memory 7 (S2), and the data in the buffer memory 7 is transferred to the host computer via the data register 33 (S3). ). When the data is read in this manner and there are a plurality of blocks to be read, these processes are repeated a predetermined number of times to end the read process (S4).

Next, the case of writing data will be described. The host computer specifies the register with the address bus 101,
The data bus 102 and the control signal bus 103 set the command code indicating the write processing to be executed in the command register 31 and the logical block address for writing the data in the address register 32. Therefore, the microcomputer 2 determines the command code in the command register 31, confirms that the data is written, and executes the data writing process. After that, via the status register 34,
Report the execution result to the host computer.

FIG. 5 shows an example of these processes. In FIG. 5, for the logical block address specified in the address register 32, the memory space of the data storage unit 5 is read from the first table 41. Search whether the corresponding real block address above is set (S1)
1). If the actual block address does not exist in the first table 41 (when the logical address is the first write), the process proceeds to S14.

If it is determined in S12 that the real block address exists, the "invalid block" flag is set in the area of the second table corresponding to the real block address. Next, in S14, the data is transferred from the host computer to the buffer memory 7 via the data register 33.

After that, the second table 42 is searched to find the real block address in which the "empty block" flag is set in the data storage unit 5 (S15), and the area indicated by the real block address is stored in the buffer memory. Data is written (S16), and it is checked whether the data writing has been normally executed (S17).

If an error occurs during writing and normal writing cannot be performed, a flag of "defective block" is set in the area of the second table 42 corresponding to the actual block address in S18, and the actual block address will be changed in the future. Prevent access to block addresses. Then, again, the second table 42 is searched for a real block address that is an "empty block", and data writing is re-executed.

When the data is normally written,
The "valid block" flag is set in the area of the second table 42 corresponding to the real block address written in S19. Then, by setting the value of the real block address in the area of the first table 41 corresponding to the designated logical block address, the correspondence between the logical block address and the real block address is performed. When the data writing is executed in such a procedure and there are a plurality of blocks to be written, these processes are repeatedly executed a predetermined number of times to end the writing process (S21).

As described above, reading and writing of data with respect to the flash memory is performed. Then, in the case of a flash memory, a separate erasing process is necessary. In a flash memory, erasing is performed in a certain unit (usually 2 ⁿ bytes, which is usually larger than the writable unit). When this erase unit is larger than the write block (for example, when the erase size is 4 Kbytes and the write size is 512 bytes), an example of the data erase procedure of the flash memory is shown in FIG.

When executing the erasing process, first, in S31, the second table 42 is searched for the area of the "invalid block" flag, and the "valid block" is included in the erase block unit including the "invalid block" flag. It is searched for an area having a flag (S32). If the "valid block" flag does not exist in the determination of S33, the contents of the erase block are erased (S34).

If the "valid block" flag is present in the determination in S33, the data in the real block address having the "valid block" flag in S35 is stored in the work memory 7.
Evacuate to. Since there may be a plurality of real block addresses, a sufficient work memory size is required. Then, in S36, the contents of the corresponding erase block are erased. After that, the data saved in the work memory 7 is written to the original corresponding real block address, and the data which is the "valid block" flag is returned to the original state (S3).
7). After execution of this erase operation, an "empty block" is set in the area of the second table 42 corresponding to the real block address that was the "invalid block" flag that is the target of the erase process.
A flag is set (S38). The erasing process is executed in such a procedure.

In the case of this erasing process, the data saved in the work memory 7 may be written in another real block address instead of being returned to the original real block address. An example of this processing is shown in FIG.

In the figure, the processes of S41 to S45 have the same contents as S31 to S35 of FIG. In S46, the real table address that is the "empty block" flag is searched from the second table 42 other than the erase operation target block, and the data saved in the work memory 7 is written in the area of the real block address (S47). ). Then, the real block address for which the data has been saved is retrieved from the first table 41, and that value is changed to the real block address value for which the saved data has been written (S48).

Then, the "valid block" flag is set in the area of the second table 42 corresponding to the written real block address (S49), and the data which is the "valid block" flag is stored. Next, an erase operation is performed in erase block units (S50), and in S51, an "empty block" flag is set in the area of the second table 42 corresponding to all real block addresses in the erase block range. The erasing process is executed in such a procedure.

In the erasing processing method in FIG. 7, the data which is the “valid block” is moved to another “empty block” as compared with FIG. 6, so that the processing efficiency is improved and the erasing processing is executed at high speed. There is an effect that it is possible.

Next, the data erasing procedure of the flash memory when the erase unit is equal to the write block unit (for example, the erase size is 512 bytes and the write size is 512 bytes) will be described with reference to FIG.

In this case, since it is not necessary to care about the states of other blocks, first, to execute the erasing process, S
The second table 42 is searched with 61, and “invalid block” is searched.
Search for flag areas. Then, in S62, the contents of the real block address corresponding to the "invalid block" flag are erased. Then, in S63, the "empty block" flag is set in the area of the second table 42 corresponding to the erased real block address. The erasing process is executed in such a procedure.

When the erase unit is smaller than the write block unit (for example, the erase size is 512 bytes and the write size is 1024 bytes), the same processing procedure as that when the erase unit is equal to the write block unit may be used ( (See FIG. 8), erasing processing may be performed on each of a plurality of erase blocks corresponding to the write size.

The erasing process as shown in FIGS. 6 to 8 may be executed in response to the writing of data. However, in order to execute the writing process of the data quickly, it is separated from the writing process of the data. It is better to execute it while waiting for a command where processing for access from the computer does not occur.

Further, if the erasing process can be executed in parallel with the writing and reading of data, the erasing process can be executed as a work behind the normal access process, so that the erasing process inside the device is the writing and reading process. It does not affect time.

Next, a second embodiment of the present invention will be described with reference to FIG. The present embodiment is an example in which the pointer register 9 and the register operating unit 8 for controlling the pointer register 9 are provided inside the memory controller 6 that controls access to the flash memory. It shall be realized by either hardware or software.

The pointer register 9 always points to a writable real address in the flash memory in order to store the data transferred from the host computer when a data write command is issued from the host computer. The register operating unit 8 is a pointer register 9 for writing the next data every time data writing is executed.
Perform an update operation for.

In the above description, the case where the pointer register 9 and the register operating unit 8 are provided inside the memory controller 6 for controlling access to the flash memory has been described. However, the pointer register 9 is set in the work memory 4. It is conceivable that the register operating unit 8 is realized by software in the microcomputer 2, and the present invention is not limited to the above embodiment.

FIG. 16 is a diagram showing a block configuration example of a flash memory. The flash memory is divided into some erase blocks as erase units, and each erase block is divided into some access blocks as read / write units. In the flash memory, reading and writing can be executed in units of access blocks, but in erasing processing, erasing must be performed in units of erase blocks, or the entire chip must be erased at once. Further, an access block once written cannot be newly written unless the block is erased. In this example, the flash memory is divided into 10 erase blocks, and each erase block is further divided into 8 access blocks.

FIG. 10 shows a data write processing procedure for the semiconductor disk device of this embodiment. The semiconductor disk device transfers the received data from the host computer to the buffer memory in S71, and then writes the received data stored in the buffer memory to the real block address indicated by the pointer register in block units in S72. S7
It is determined in 3 whether or not this writing process is completed normally, and if the process is not completed normally, it is determined in S74 that the block to be written is a defective block and the block information is stored in the second block. The data corresponding to the designated block in the table is rewritten to the code indicating the defective area. As a result, this block is subsequently regarded as a defective area and excluded from access targets. After this operation, the pointer register is updated (S75), and the process returns to S72 to execute the write process to another block. Incidentally, S7
The updating process of the pointer register in 5 will be described later. On the other hand, if it is determined in S73 that the writing process to the block has been completed normally, the actual block address in the flash memory array in which the data writing was executed and the logical block address designated to be written by the host computer are linked in S76. Therefore, the actual block address value is written in the area corresponding to the logical block address specified in the first table.

Next, in S77, the second table information corresponding to the written block is updated from the erased "empty block" to a code indicating "valid block", and S7
In step 8, the second table information corresponding to the block address in which the data before rewriting is stored is updated from "valid block" to a code indicating "invalid block" (erase request). Next, in S79, the pointer register is updated, and the write processing for one block, which is the minimum unit of access, is completed.

By repeating the above processing for the number of write blocks designated by the host computer, the data write processing is completed (S80). The data invalid block area set in the writing process is extracted by referring to the second table during the erasing process, and becomes a writable empty block by executing the erasing.

In the processing procedure shown in FIG. 10, the pointer register update processing is executed during a series of processing.
It is also possible to process in parallel with the flow. It is also possible to prepare a plurality of pointer registers and set not only the data write destination address at that time but also the next data write destination address.

FIG. 11 shows a detailed flow of the pointer register updating process. First, in S81, the pointer register is incremented to move the pointer by one block address. In S82, it is determined whether the pointer value is within the range of the real memory space to which the flash memory array is mapped by this movement. If the pointer value is out of the range, the pointer value is set to the start address of the real memory space in S83. , It is assumed that the pointer cyclically points to the real memory space.

Next, in step S84, the state of the block indicated by the pointer register is read from the second table, and in step S85, it is determined whether the block is an erased data writable area. If the area is other than the data writable area, this operation is repeatedly executed to set the empty block address next to the previously specified block address in the pointer register. The pointer register updating process of S81 to S85 is executed by the register operating unit 8 by software or hardware.

As described above, the pointer register 9 indicating the data write destination is used by the register operating unit 8 in the data storage unit 5.
By operating so that writing is executed evenly to the entire area, access is concentrated on a specific area (area where disk management information such as FAT and directory is stored) of the flash memory array that is the data storage unit 5. Since it is possible to write data uniformly to the entire real memory space,
The life of the semiconductor disk device can be extended.

FIG. 12 shows a processing procedure for reading data. Since the pointer register is used only for writing data, the operation for the pointer register is not executed in the data reading process. In the read processing in S91, the real block address corresponding to the logical block address designated by the host computer is read from the first table, and S
At 92, the data block is read from the flash memory array of this real block address to the buffer memory and transferred to the host computer (S93). By repeating this process for the number of blocks designated by the host computer, the data reading process is completed (S94).

Next, the timing of the data erasing processing method in the semiconductor disk of this embodiment will be described. The specific contents of the erasing process are the same as in the case of the first embodiment. First, the erasing processing procedure at the time of reading data from the semiconductor disk will be described with reference to FIG. In S101, the logical block address sent from the host computer is converted into the real block address of the data storage unit in the first table of the work memory.

Next, in steps S102 and 103, it is determined whether or not there is an erase block to be erased in a chip that does not execute access, other than the chip in which the real block to be read in the read process is stored. If there is an erase block, the erase process is activated for that block (S104). If it does not exist, the erasing process is not performed and the data in the real block address is transferred to the host computer in S105.

Then, in S106, it is determined whether or not the erase process has been executed for each read process, and if the erase process has been activated in S104, the erase process is verified in S107, and the read process is terminated. If it has not been executed, the read process is terminated as it is.

In this way, the erasing process is started before reading the data from the real block address, the erasing process is performed in parallel with the data reading, and it is verified whether the erasing process is normally completed after the data reading is completed. Therefore, it is possible to execute the erasing process as the back work of the data reading process.

Next, the procedure of the erase verification process in S107 of FIG. 13 will be described with reference to FIG. It waits for the end of the erasing process executed in S111. After the erasing process, S1
In step 12, it is checked whether the processing has ended normally.
In 3, the erased real block information of the second table is set to “empty block” (erased). Next, if the processing ends abnormally, that is, if the real block is not completely erased, the real block information in the second table is set to "defective block" in S114, and access to this real block is prohibited thereafter.

Next, the erasing processing procedure when writing data to the semiconductor disk will be described with reference to FIG. First, in S131, it is checked in the first table of the work memory whether the logical block address accessed by the host computer has been previously accessed, that is, whether it is the logical block address for the first write processing or the second or more write processing. To do. Specifically, it is checked whether or not the real block address value exists in the first table. If the real block address value exists, the data in the real block address accessed last time becomes invalid and the real block can be erased. Therefore, in S132, the real block information of the second table is set to “invalid block”.

Next, in S133, the data sent from the host computer is first transferred to the buffer memory.
Next, in S134, the real block which is requested to be erased is investigated, and in S135, it is checked whether or not there is a real block to be erased among the chips which are not accessed. If there is a real block to be erased, erase processing is performed in S136. If not present, no erasing process is needed.

Then, in S137, the data in the buffer memory is transferred to the real block address indicated by the pointer register. Then, in S138, it is checked whether or not the writing of the actual block has been completed normally. If a write error occurs here, error processing is performed in S139 and writing is retried. The contents of this error processing correspond to S74 and S75 in FIG.

When the writing is completed normally, the information of the real block written in S140 is set as the "valid block" in the second table. Next, in S141, the value in the pointer register is incremented, and in S142, it is checked in the second table whether or not the information of the next real block is "empty block".

Information of the next real block is "empty block"
If so, the value of the pointer register is updated to that position in S143. If the block is an "empty block", that block cannot be accessed, so the procedure returns to the pointer increment of S141, and the pointer register is not updated until an erased real block is found. Next, in S144, it is determined whether or not the erase process is executed for each write process, and if it is executed, the erase process is verified in S145, and then the write process is ended. If it has not been executed,
The writing process is finished as it is.

Next, another method of erasing data will be described with reference to FIGS. 16 and 17.

In the example shown in FIG. 16, the access blocks are invalid access blocks 1 to 6 in the erase block 1.
It is assumed that valid access blocks 1 and 2 exist. In the erase block 2, all empty access blocks 1 to 8
Has become.

Here, the empty access block means that the block is in a state immediately after the erase processing, there is no data in the block, and the block can be written. An effective access block is a state in which data has been written once to an empty access block.
It indicates that the data in the block can be read. An invalid access block is a block that can be erased because data exists in that block, but rewriting is executed for that logical address and the actual data is written in another block. Shows.

A preprocessing procedure for erasing the flash memory in such a state will be described with reference to FIG.
This erase preparation process is performed while waiting for a command that is not accessed from the host computer, or is executed in conjunction with the erase process. First, in step S161, a second table that corresponds to the access blocks (1 to 8) in the erase block on a one-to-one basis and manages information such as valid / invalid for the real address is searched.

Next, in S162, how many invalid access blocks are included in the total number of 8 access blocks in the erase block 1 is counted. If the number of invalid access blocks exceeds x% of the total number of erase blocks, the block moving process is performed in the next S163.

If it does not exceed the threshold, the process of moving the block is not performed and the process proceeds to S166. The ratio x for the block movement processing determination can be set arbitrarily. For example, the value of x is 70
In this example, if 70% of the total number of blocks 8 in the erase block 1, that is, the number of invalid access blocks is 6 or more, in this example, the blocks are relocated. In this example, the invalid access block is 6, which corresponds to the block transfer. When set to 80%, the transfer is 7 or more, which is not the case in this example. That is, by making the value of x variable, it is possible to change the criteria for block movement processing determination.

If the invalid access block exceeds x% in S162, the valid access block in the erase block 1 is transferred to another erase block 2 which is another erase block unit in S163. The access block to be transferred must be an empty access block.
The pointer register indicates a real block address to which data is written, and since the pointer points to an empty access block, the effective access block in the erase block 1 may be moved to the block pointed to by the pointer.

After transferring the valid access blocks 1 and 2 to the empty access blocks 1 and 2 of the erase block 2, S
At 164, empty access block 1 of erase block 2
Register the real block address of 2 in the first table.

Then, in S165, the data in the erase block 1 where there is a valid access block becomes meaningless, so the information of the second table corresponding to that block is changed from "valid block" to "invalid". block"
Change to. Further, the information in the second table corresponding to the access blocks 1 and 2 in the erase block 2 that has been transferred is changed from the "empty block" to the "valid block". As a result of this processing, the data itself exists in all the access blocks in the erase block 1, but the read / write state becomes invalid, and the erase block 1 can execute batch erase.

After the processing is completed for the erase block 1, it is determined in S166 whether or not the processing is performed for all the erase blocks. If there is an erase block that has not been processed, the next erase block is selected in S167, and the search is performed again in S161. The process is executed for all erase blocks, and the erase preparation process is ended.

After that, in the erase processing operation, all the access blocks in the erase block unit are "invalid blocks".
It is sufficient to erase all the erase blocks.

In the present embodiment, the case where the block moving process is performed when the number of invalid access blocks (erasable blocks) exceeds x% (threshold value) of the total number of erase blocks in units of erase blocks has been described. However, there is a case where the block moving process is performed when all access blocks of the data storage unit 5 are used as a unit and x% (threshold value) of invalid access blocks with respect to the sum of all access blocks exceeds.

The structure of the semiconductor disk of the third embodiment of the present invention is shown in FIG.

In this embodiment, there is a logical block address (for example, DOS FAT or directory area) that is always accessed every time a file is read / written in a specific system, and these are naturally rewritten many times. In view of this, the FRAM 51 is configured to access this area faster than the flash memory and has a much longer life depending on the number of times of rewriting. This makes it possible to speed up data access and, at the same time, prolong the life of the semiconductor disk due to the limitation of the number of times of rewriting of the flash memory.

The data storage unit 5 comprises an FRAM 51 and a flash memory 52. The third table 43 in the work memory 4 stores the number of rewrites of the logical address block accessed by the host computer.

FIG. 19 shows a configuration example of the second table 42. Y% in the real block address space of the data storage unit 5
As the FRAM area, and the information in the second table indicates the presence / absence of data in the real block address.

Next, FIG. 20 shows the configuration of the third table 43. The number of rewrites of each logical block address is stored in correspondence with the logical block address accessed by the host computer. In this example, the address 0001 has not been accessed yet, and the address 0030 has already been written 1024 times.

Next, a specific writing process in this embodiment will be described. FIG. 21 shows a processing procedure at the time of writing. First, in S171, the data sent from the host computer is transferred to the buffer memory 7. Then S172
In step 1, it is checked whether the logical block address accessed by the host computer exists in the first table 41.

If it exists, the data is rewritten. Therefore, the previously written data is the FRAM area 5.
In S173, it is checked which of the memory area 1 and the flash memory area 52 exists. If the data exists in the FRAM area 51, the data in the buffer memory 7 is written to the FRAM real block address in S178 (erasing is not necessary). If it exists in the flash memory area 52, the writing process to the real block address indicated by the pointer register 9 is performed.

Next, when the logical block address accessed by the host computer does not exist in the first table 41, the logical block address is accessed for the first time, so that there is an empty area in the FRAM area 52 in S174. Find out if Specifically, in the second table 42 having the configuration as shown in FIG. 19, the FRAM area is searched for a real block having information of “no data”.
When all the FRAM areas 51 are in use, the flash memory is accessed in S175. If an empty block exists in the FRAM area 51, the data in the buffer memory 7 is written to the real block address in S176. Next, in S177, the written block information of the FRAM is set to "data exists" in the second table 42.

Next, in S179, after one of the above-described writings is completed, the number of times of rewriting of the area corresponding to the logical block address accessed by the host computer in the third table 43 as shown in FIG. 20 is incremented. Here, a logical block address that is rewritten many times means that it is accessed many times. Therefore, the logical block address, which is rewritten many times, is more FR than the flash memory area 52.
It is better to place it in the AM area 51. This is because the life of the memory chip due to the number of times of rewriting is much longer in the FRAM than in the flash memory, and the access speed is higher.

Therefore, in S180 and S181, the logical block address with the largest number of rewrites in the flash memory area and the logical block address with the smallest number of rewrites in the FRAM area are searched for each writing process, and the logical block address in the FRAM area is searched in S182. If the number of rewrites of the logical block address of the maximum number of rewrites of the flash memory area is larger than that of the logical block address of the minimum number of rewrites, the data in the actual blocks are exchanged in S183. When the replacement is further performed, the contents of the first table 41 are updated. If the replacement is not necessary, the writing process ends without doing anything.

By executing such processing, the logical block address that is frequently rewritten is stored in the FRAM area, which makes it possible to extend the device life of the semiconductor disk and increase the average access speed. Can be

In the above embodiment, the number of times of rewriting is managed by the third table. However, in most systems, the management area of the disk (F of DOS).
Since the frequency of rewriting to the area corresponding to the AT area etc.) is high, the memory is configured so that the area corresponding to the management area of the disk is mapped to the FRAM area without using the third table. It is possible to obtain the same effect as that of the embodiment.

[0098]

As described above, according to the present invention, by providing the first table and the second table, the erased portion can be searched and the data can be immediately written. Data can be written more quickly than the above, and efficiency can be improved. Furthermore, by providing a pointer register and setting the actual block address of the data write destination in advance, data can be written more quickly. It is also possible.

Further, the data storage unit is composed of two non-volatile memories having different writable times, and the sector having a high writing frequency is stored in the non-volatile memory having a large writable number. It has an advantage that a file device having a large capacity and a long device life can be realized even if a memory element having a limited number of times of rewriting is used.

Further, by arranging the real block address of the data write destination set in the pointer register to be arbitrarily settable, the concentration of writing to a specific real block address can be avoided and the device life can be extended. It has the advantage of being possible.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a semiconductor disk according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a first table.

FIG. 3 is a configuration diagram of a second table.

FIG. 4 is a flowchart showing a data reading process.

FIG. 5 is a flowchart showing a data writing process.

FIG. 6 is a flowchart showing a data erasing process.

FIG. 7 is a flowchart showing a data erasing process.

FIG. 8 is a flowchart showing a data erasing process.

FIG. 9 is a block diagram showing a configuration of a semiconductor disk according to a second embodiment of the present invention.

FIG. 10 is a flowchart showing a data writing process.

FIG. 11 is a flowchart showing a pointer register update process.

FIG. 12 is a flowchart showing a data reading process.

FIG. 13 is a flowchart showing a data reading process.

FIG. 14 is a flowchart showing a verification process for erasing data.

FIG. 15 is a flowchart showing a data writing process.

FIG. 16 is a diagram showing a block configuration of a flash memory.

FIG. 17 is a flowchart showing an erase preparation process.

FIG. 18 is a block diagram showing a configuration of a semiconductor disk according to a third embodiment of the present invention.

FIG. 19 is a configuration diagram of a second table.

FIG. 20 is a configuration diagram of a third table.

FIG. 21 is a flowchart showing a data writing process.

[Explanation of symbols]

 1 semiconductor disk 2 microcomputer 3 I / F controller 4 work memory 5 data storage unit 6 memory controller 7 buffer memory 8 register operating unit 9 pointer register 41 first table 42 second table 43 third table 51 FRAM 52 flash memory 101,111 Address bus 102,112 Data bus 103,113 Control signal bus

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hiroyuki Mushiaki 1-88, Tora-Tora, Ibaraki City, Osaka Prefecture Hitachi Maxell Co., Ltd. (72) Inventor Masayuki Nagano 1-88-Tora, Ibaraki City, Osaka Maxel Co., Ltd.

Claims (18)

[Claims] 1. A data storage unit comprising an electrically writable non-volatile memory, a control unit for controlling the data storage unit, and an input / output unit for inputting / outputting data to / from a host computer connected thereto. In a semiconductor memory device in which data access is executed from a higher-level computer by specifying a logical block address in a fixed block unit, the logical block address designated at the time of access from the higher-level computer is stored in the real memory space of the data storage unit. Of the real block address, and a second table for managing the state of data in the real block address corresponding to the real block address. 2. The pointer register according to claim 1, which stores a writable real block address when writing data to the data storage unit, and a write destination real block address when writing data to the pointer register. A semiconductor memory device, comprising: a register operating unit for setting the. 3. The semiconductor memory device according to claim 1, further comprising a third table that stores the number of times of writing to the logical block. 4. The semiconductor memory device according to claim 1, wherein the address space indicated by the real block address is larger than the address space indicated by the logical block address. 5. The code according to claim 1, wherein the contents of the second table are states of corresponding real blocks, and stores codes representing at least three states of a free block, a data stored block, and an erasable block. A semiconductor memory device characterized in that 6. The semiconductor memory device according to claim 1, wherein the data storage unit is composed of a nonvolatile memory capable of erasing in erase block units including at least one access block. 7. The nonvolatile memory according to claim 6, wherein the nonvolatile memory forming the data storage unit is a flash type EEPRO.
A semiconductor memory device characterized by being M. 8. The rewritable number according to claim 3, wherein at least one of the first table, the second table, and the third table has a larger number of rewritable times than the nonvolatile memory of the data storage unit. A semiconductor memory device characterized by being stored in a non-volatile memory that can be written or erased in byte units. 9. The semiconductor memory device according to claim 8, wherein the non-volatile memory storing the table is an FRAM. 10. The first non-volatile memory according to claim 1, wherein the data storage section is capable of erasing in erase block units including at least one access block, and the number of rewritable times is greater than that of the first non-volatile memory. Large,
The access block or a second non-volatile memory that can be written or erased in byte units below the access block is used as the first data area managed by the operating system.
And a file management area such as a FAT or a directory is stored in the second non-volatile memory. 11. The first non-volatile memory according to claim 3, wherein the data storage section is capable of erasing in erase block units including at least one access block, and the number of rewritable times is greater than that of the first non-volatile memory. Large,
An access block or a second non-volatile memory that is writable or erasable in byte units below the access block, and is written from the block having a large number of writes to the logical block address stored in the third table to the second block. A semiconductor memory device, comprising: storing in a non-volatile memory the remaining blocks that cannot be stored in the second non-volatile memory in a first non-volatile memory. 12. The EEP according to claim 10, wherein the first nonvolatile memory is a flash type EEP.
A semiconductor memory device comprising a ROM and a second non-volatile memory being an FRAM. 13. A data storage unit, which comprises an electrically writable and electrically erasable non-volatile memory in a predetermined unit, and a control means for controlling the data storage unit are connected. Input / output means for inputting / outputting data to / from a host computer; a first table for converting a logical block address designated by the host computer at the time of access into a real block address in a real memory space of the data storage unit; Control of a semiconductor memory device configured to include a second table that manages the state of data in the real block address corresponding to the block address and execute data access by specifying a logical block address from a host computer in a fixed block unit In the method, during the data read processing by the host computer, the logical table is read by the first table. It has a step of converting the lock address into a real block address, and a step of transferring the data read from the converted real block to a host computer, and when writing data from the host computer, writes data from the second table. A step of searching for a possible free block, a step of writing data to the free block, and a step of writing the real block address of the block in which the data is written to the first table are used to determine the correspondence between the real block address and the logical block address. A method of controlling a semiconductor memory device, comprising: a step of erasing and a step of erasing data independently of the series of data writing processing. 14. A data storage unit comprising a non-volatile memory that is electrically writable and electrically erasable in a predetermined unit, and a control means for controlling the data storage unit are connected. Input / output means for inputting / outputting data to / from a host computer; a first table for converting a logical block address designated by the host computer at the time of access into a real block address in a real memory space of the data storage unit; Control of a semiconductor memory device including a second table that manages a state of data in a real block address corresponding to a block address, and a pointer register that stores a writable real block address in the data storage unit In the method, during a data write process from the host computer, a specific real block address in the data storage unit is Control method of a semiconductor memory device characterized by comprising the step of sequentially changing the actual block address in each data writing write the less is set for the pointer register so as not to concentrate. 15. A data storage unit is composed of a non-volatile memory that is electrically writable and electrically erasable in a predetermined unit, and data is specified by a logical block address from a host computer in fixed block units. In a method of controlling a semiconductor memory device to be accessed, the data storage unit is composed of a plurality of memories, data access processing for a memory in which desired data is stored for data access from the host computer,
A method for controlling a semiconductor memory device, characterized in that erasing processing of an erasing target block for another memory can be performed at the same time. 16. A data storage unit is composed of a non-volatile memory that is electrically writable and electrically erasable in a predetermined unit, and data is specified by a logical block address from a host computer in fixed block units. In a method of controlling a semiconductor memory device to be accessed, an erase block unit of the data storage unit is larger than a readable and writable access block unit,
If there are a plurality of access blocks in the erase block size and the number of invalid access blocks exceeds a predetermined threshold value in the erase block size, the valid block existing in the erase block is valid. A method of controlling a semiconductor memory device, comprising: erasing an erase block after moving an access block to another block. 17. The method of controlling a semiconductor memory device according to claim 16, wherein the threshold value can be changed according to the total number of empty blocks in the data storage unit. 18. A first non-volatile memory which is electrically writable and can be erased in erase block units including at least one access block, and the number of rewritable times is greater than that of the first non-volatile memory. , A data storage unit consisting of an access block or a second non-volatile memory that can be written or erased in byte units below the access block, control means for controlling the data storage unit, and a host computer and data to be connected. An input / output unit for inputting and outputting the data, a first table for converting a logical block address designated at the time of access from the host computer into a real block address in the real memory space of the data storage unit, and the real block address Correspondingly, a second table that manages the state of the data within that real block address, and A method of controlling a semiconductor memory device comprising a third table for storing the number of times of writing in logical address units, wherein a block having a large number of times of rewriting with respect to a logical block address stored in the third table is stored in the second nonvolatile memory. A non-volatile memory and a remaining block that cannot be stored in the second non-volatile memory is stored in the first non-volatile memory.