JPH0721771B2 - Emulation chip - Google Patents

Description

Description: INDUSTRIAL APPLICABILITY The present invention has the same architecture, memory size, I /
Regarding debug emulation chips of 1-chip microcomputer family with different numbers of O,
In particular, the present invention relates to a mode switching method to a target microcomputer.

2. Description of the Related Art An emulator for a microcomputer usually has two operation modes, a user mode and a supervisor mode. User mode is the program of the microcomputer to be emulated.
This mode is executed with the function equivalent to the target microcomputer, while the supervisor mode is
Display the status of internal register of emulation,
This is a mode for executing programs associated with emulation work, such as changing the user program, operating various mode registers, and displaying trace results during user mode.

By the way, the one-chip microcomputer developed in recent years has the same architecture with the same memory size, the number of I / O, and peripherals in order to promote development efficiency, compatibility, and product price reduction. Increasing adoption of core architectures that form families by differentiating hardware.

Emulation for such a core architecture family is usually performed by an emulation microcomputer equipped with the largest hardware in the family (hereinafter referred to as emulation chip), and is effective corresponding to the microcomputer to be emulated. Switch memory areas, I / O, peripheral hardware, etc.

That is, in the conventional emulation chip, a plurality of mode switching registers are provided, and the microcomputer to be emulated is determined through the selection circuit according to the value written in the mode switching register.
The mode on the hardware is switched by enabling or disabling the additional circuit for each target microcomputer.

FIG. 2 is a diagram schematically showing the configuration of an emulation chip having n mode switching setting signal holding registers mapped to a certain address.

When setting this emulation chip to the mode of the microcomputer to be emulated, the following operation is performed. First, the mode setting signal 3 is set to "1" via the address bus, and the write signal 4
Is set to active “0”. The NAND circuit 10 is the inverter 5
“0” is output to the output line 11 based on the inverted write signal 6 and the mode setting signal 3. In this state, desired mode data is input to the switching setting signal holding registers 1 (1) to 1 (n) via the data bus and the defining signal lines 2-1 to 2-n.

The address-mapped n mode switching setting signal holding registers 1 (1) to 1 (n) are used when the write signal 4 changes from "0" to "1", that is, the output line 11 of the NAND circuit 10. The data on the mode switching setting signal defining signal lines 2-1 to 2-n is latched at the rising edge of the rear end at the edge, and the latch data is output to the mode setting latch signals 12-1 to 12-n.

That is, the mode switching setting signal holding register 1 (1)
The signal lines for regulation 2-1 to 2-n for regulating 1 to (n) are
When active "1", mode setting latch signal 12- of mode switching setting signal holding register 1 (1) to 1 (n)
1 to 12-n becomes "1", and the signal lines for regulation 2-1 to 2-n
Is non-active "0", mode setting latch signal 12- of mode switching signal holding register 1 (1) to 1 (n)
1-12-n is "0".

These mode setting latch signals 12-1 to 12-n are input to the decoder 17, and the mode setting signals are output to the decoder outputs 18-1 to 18-m. This mode setting decoder output 18-
According to 1 to 18-m, the emulation chip inhibits a memory area, I / O, peripheral hardware and the like which are not mounted in the microcomputer to be emulated.

Problems to be Solved by the Invention As described above, the mode switching setting signal holding register in the conventional emulation chip is a regulation signal for instructing the mode setting and environment setting according to the emulation target via the data bus. This is performed by the mode setting signal and the write signal by the line and the address bus.

Therefore, in the conventional emulation chip, the contents of the mode switching setting signal holding register may be rewritten when the program of the target microcomputer runs away in the operation in the user mode. In this case, the target mode of the emulation chip changes, and it becomes impossible to continue effective emulation for the specific microcomputer.

Further, since the operation itself of the emulation chip is determined when the value is set in the mode switching setting signal holding register, once the target mode is set, the operation mode does not change until it is reset. Therefore, even in the supervisor mode in particular, it operates in the preset target microcomputer mode, and the functions such as the read / write attribute of the memory, the access mode, and the memory size cannot be used. That is, there is a drawback in that the function of the emulation chip unique to debugging cannot be effectively used.

The present invention solves the above-mentioned drawbacks of the prior art, and as an emulation chip, a new emulation chip having a more effective user mode and supervisor mode.
Its purpose is to provide chips.

Means for Solving the Problems That is, according to the present invention, a user mode in which the same operating environment as that of the microcomputer to be emulated is set to execute a program for the microcomputer, and an operating environment provided by itself Is set to be operable and a program for itself is executed in at least two kinds of operation modes. In the user mode, execution of an operation environment setting operation is prohibited, and the supervisor In mode, it is an emulation chip that is configured to activate all operating environments that it has, and it is the logical product of the mode setting signal and the inverted write signal and the user mode or supervisor mode. Whether the output signal is the emulation chip mode output signal shown A mode switching circuit having a mode setting signal holding register triggered by constant logical product and using a logical product of the latch signal of the mode setting signal holding register and an inverted signal of the emulation chip mode output as the mode setting latch signal There is provided an emulation chip having:

The emulation chip according to the present invention prohibits the switching of the debug target mode in the user mode for executing the program of the microcomputer to be emulated, while it is within the family in the supervisor mode for executing the program for the emulation. The debugging target microcomputer mode switching circuit is configured to be the emulation chip mode which is the maximum mode of the above.

This is, for example, as a mode switching method of a target microcomputer, an AND of a mode setting signal and an inverted write signal, and an emulation indicating that the mode is a user mode or a supervisor mode.
The NAND of the chip mode output signal line is used as the trigger for the mode switching setting signal holding register, and as the mode setting latch signal, the latch signal of the mode setting signal holding register and the inverted signal of the emulation chip mode output. It is realized by using the logical product of and.

Such an emulation chip according to the present invention is
It can be particularly advantageously used for debugging a one-chip microcomputer family that has the same architecture but differs only in memory size, I / O count, peripheral hardware, and the like.

EXAMPLES The present invention will be described in more detail below with reference to the drawings. However, what is disclosed below is only one example of the present invention and does not limit the technical scope of the present invention. .

FIG. 1 is a diagram schematically showing the configuration of an embodiment of the present invention.

In the emulation chip having the circuit shown in FIG. 1, the following operation is performed when setting the mode of the microcomputer to be emulated.

First, when the mode setting signal 3 is set to “1” and the write signal 4 is set to active “0” via the address bus, AN
The mode setting signal 3 and the inverted write signal 6 are input to the D circuit 7, and "1" is output to the output line 8. Further, the emulation chip mode output signal line 9 becomes "1" in the supervisor mode in which the emulation chip accepts a privileged interrupt request (hereinafter referred to as a supervisor interrupt) from the supervisor, so that the user who is executing the emulation is It is a signal line that becomes “0” in the mode.

Then, the output line 8 of the AND circuit 7 and the emulation
The chip mode output signal line 9 is input to the NAND circuit 10. Emulation chip mode output signal line 9 is "1" (supervisor mode) and NAND circuit output line
When 11 becomes "0", the write signal 4 changes from "0" to "1". Therefore, at the trailing edge of the rising edge of the output line 11 of the NAND circuit 10, the mode switching setting signal holding register defining signal lines 2-1 to 2-n connected to the data bus.
The mode data corresponding to a desired mode is latched in the address-mapped n pieces of mode switching setting signal holding registers 1 (1) to 1 (n), and the mode setting latch signals 12-1 to 12-n are latched. Is output.

Mode switching setting signal holding register 1 (1) to 1
At (n), the mode setting latch signals 12-1 to 12-n become active "1", and the active "1" mode setting latch signal is held until the mode is set again in the supervisor mode. Therefore, AND circuits 15-1 to 15- that receive the active "1" mode setting latch signal as one input
Mode setting decoder inputs 16-1 to 16-n which are n outputs
Is transferred to the user mode by the emulation chip mode inversion output signal line 14 that is inverted by the inverter 13 that is input to the other input, and the emulation chip
It becomes active "1" when the mode inversion output signal becomes "1".

The signal lines 2-1 to 2-1 for defining the registers 1 (a) to 1 (n)
When 2-n is inactive "0", register 1
(1) to 1 (n) mode setting latch signals 12-1 to 12-
Since n is always "0", the corresponding mode setting decoder inputs 16-1 to 16-n are always "0".

The decoder 17 has mode setting decoder inputs 16-1 to 16-n.
A mode setting decode signal is output to the decoder outputs 18-1 to 18-m according to the signal from the. Thus, according to the mode setting decoder outputs 18-1 to 18-m, the emulation chip inhibits the memory area, I / O, peripheral hardware, etc. which the microcomputer to be emulated does not have.

The emulation chip whose mode is set as described above operates as follows in each mode.

In the supervisor mode, the emulation chip mode output signal line 9 is "1". Therefore, according to the mode setting signal 3, the register defining signal lines 2-1 to 2-n and the write signal 4, the output of the mode switching setting signal holding registers 1 (1) to 1 (n) is changed, that is, the mode setting latch. It is possible to change the signals 12-1 to 12-n. However, the emulation chip mode inversion output signal line 14 is "0", and the mode setting decoder input 16-1
.About.16-n are also always "0", so that all the mode setting decoder outputs 18-1 to 18-m are also "0". This sets the emulation chip's mode with the largest memory size, I / O count, and peripheral hardware for the family.

On the other hand, in the user mode, the emulation chip mode output signal line 9 is "0". Therefore, even if the mode setting signal 3 and the write signal 4 change the AND circuit output line 8 due to program runaway of the target microcomputer, the NAND circuit output line 11 is always "1".
That is, the mode setting latch signals 12-1 to 12-n cannot be changed, that is, the outputs of the registers 1 (1) to 1 (n) cannot be changed. At this time, the emulation chip mode inversion output signal line 14 is "1", and the mode setting latch signals 12-1 to 12- set in the supervisor mode are set.
The state of n is output to the mode setting decoder inputs 16-1 to 16-n to set the mode of the target emulation chip.

Thus, at the time of shifting to the user mode, the state corresponding to the target emulation chip is set, and this is not changed while in the user mode. on the other hand,
All memory sizes, I / O counts, and peripheral hardware are enabled when you enter supervisor mode.

As described in detail above, according to the present invention, the emulation
By adding an emulation target microcomputer mode switching circuit to the chip and using an emulation chip mode output signal line that indicates whether the mode is the supervisor mode or the user mode, , The settings of the emulation target microcomputer are not changed, while the supervisor mode switches to the mode of the emulation chip that has the largest memory size, I / O count, and peripheral hardware in the family. , You can fully use the functions useful for debugging.

[Brief description of drawings]

FIG. 1 is a diagram schematically showing a configuration of a 1-chip microcomputer family debug emulation chip according to the present invention, and FIG. 2 is a conventional 1-chip microcomputer family debug emulation chip. It is a figure which shows the structure of. [Main reference numbers] 1 (1) to 1 (n) ... Mode switching setting signal holding register, 2-1 to 2-n ... Mode switching setting signal holding register defining signal line, 3 ... Mode Setting signal, 4 ... Write signal, 5, 13 ... Inverter, 6 ... Inverted write signal, 7 ... AND circuit, 8 ... AND circuit output line, 9 ... Emulation chip mode output signal line, 10 ...... NAND circuit, 11 …… NAND circuit output line, 12-1 to 12-n …… Mode setting latch signal, 14 …… Emulation chip mode inversion output signal line, 15-1 to 15-n …… AND Circuit, 16-1 to 16-n ... Mode setting decoder input, 17 ... Decoder, 18-1 to 18-m ... Mode setting decoder output

Claims (1)

[Claims] 1. A user mode in which a microcomputer for emulation is set to the same operating environment and a program for the microcomputer is executed, and an operating environment provided by itself is set to be operable so that its own At least two kinds of operation modes including a supervisor mode for executing a program for, and prohibiting execution of an operation environment setting operation in the user mode,
In the supervisor mode, the emulation chip is configured to activate all operating environments of the device, and in the user mode or the supervisor mode, the AND of the mode setting signal and the inverted write signal is used. A mode setting signal holding register triggered by a NAND operation with an emulation chip mode output signal indicating that there is a latch signal of the mode setting signal holding register;
An emulation chip having a mode switching circuit that uses a logical product of an emulation chip mode output and an inverted signal as a mode setting latch signal.