JPH0719191B2 - Memory device - Google Patents

Description

The present invention relates to a large capacity memory device connected to a so-called microcomputer.

The so-called micro computer is configured as follows. In Fig. 1, (1) is the central processing unit (CP
The data bus line (2), the control bus line (3) and the address bus line (4) are derived from the CPU (1). Each line (2)-
(4) is a read-only memory (ROM) (5) in which a program for the operation of the CPU (1) is written and a random access memory (RAM) for storing data, etc.
It is connected to (6). Furthermore, each of these lines (2)
(4) is connected to the input / output circuit (7). Note that (10) is
It is an oscillator that creates the timing of the operation of the CPU (1).

In this device, data from the outside is read into the CPU (1) through the input / output circuit (7), and further RAM
It is written in (6). Then, data processing is performed according to the program in the ROM (5), and the resulting data is taken out through the input / output circuit (7).

However, in such a device, the storage capacity of the RAM (6) is limited, so that it is impossible to handle a large amount of data and, for example, processing such as compiler, editing, and sorting cannot be performed.

Therefore, a large-capacity memory device is provided externally to input / output a predetermined amount of data to substantially increase the storage capacity of the RAM (6).

As such a memory device, there is, for example, a device called a floppy disk.

As shown in FIG. 2, the floppy disk is a magnetic disk having a diameter of 8 inches, for example, and 77 concentric tracks (0
~ 76) and each truck has 26 sectors (1-2
It is divided into 6), and each sector can store 128 bytes of data.

And each line (2) from the input / output circuit (7) of FIG.
The signals (4) to (4) are supplied to the flow pie disk controller (FDC) (8), and the Fro pie disk (9) is driven by this FDC (8) to input / output data.

That is, a signal from the CPU (1) indicating whether to use the floppy disk (9) is supplied to the FDC (8) through the address bus line (4). A signal designating the track and sector numbers of the floppy disk (9) is supplied to the FDC (8) through the data bus line (2). Further, a write or read control signal is supplied to the FDC (8) through the control bus line (3). Then, the floppy disk (9) is rotated, the position of the magnetic head is moved, and writing and reading of the sector of the designated number is performed on the data bus line (2).
Is done through. Whether the signal of the data bus line (2) is a track number or a sector number,
An identification signal indicating whether the data is input or output is supplied to the FDC (8) through the address bus line (4).

In this way, the data of the floppy disk (9) is input / output.

However, in the case of such a floppy disk (9), a large amount of time is required to reach a designated sector, so-called access time, for mechanical driving, and input / output cannot be performed efficiently.

By the way, the price of a memory device such as a random access memory has dropped significantly compared to the initial stage of development, and the provision of a large number of memory devices has become a problem in terms of price.

Therefore, for example, it was considered to increase the capacity of the RAM (6) itself, but such a large capacity is not necessary for normal use, and increasing the capacity of the RAM (6) is a matter of address setting. It was necessary to change the design of software such as programs or hardware, and there were many problems in using the general-purpose CPU (1) already in practical use.

In view of the above points, the present invention provides a memory device that can be handled in the same manner as a floppy disk and has a short access time.

That is, the present invention has a read only memory and a random access memory, divides the read only memory and the random access memory into a plurality of sectors, and synthesizes the sector number supplied through the data bus and the output of the built-in counter. The address of the read-only memory and the random access memory is set as the address, and reading and writing are performed in sector units.

An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 3, (20) is a dynamic random access memory. This memory (20) has a storage capacity of about 190 Kbytes, which is equal to the storage capacity of one data area of a floppy disk, and is formed by arranging three 64-Kbyte memory units in parallel.

Further, (21) is a read-only memory, and this memory (21) corresponds to an area in which a program necessary for operating a computer such as an operation system of a floppy disk is written, and this memory is, for example, of 64 Kbytes. It is formed by a mask ROM.

ROM (5), RAM from the address bus line (4)
(6) Or a signal indicating which one of the external memory devices is used is supplied to the address decoder (19) to form a signal corresponding to each used memory device. These signals are ROM (5) and RAM respectively
(6) and the external memory device described later. The example shown in the figure is a case where two external memory devices are provided, one of which is a floppy disk (9),
The other is the memory device according to the present invention.

And the data bus line (2) from the input / output circuit (7)
Are connected to the data buffer circuit (11), the track number register (12) and the sector number register (13). Further, a signal for identifying whether the signal of the data bus line (2) from the address bus line (4) is the track number, the sector number or the input / output data is supplied to the decoder (14). To be done. A signal from the decoder (19) is supplied to the control terminal of the decoder (14). Then, the decoded signal is the buffer circuit (1
1), supplied to the drive terminals of the registers (12), (13). A control signal for writing or reading from the control bus line (3) is supplied to the control terminals of the buffer circuit (11), the registers (12) and (13).

Further, a write or read control signal is supplied to the drive and refresh circuit (15) of the memory (20). Also, the data bus line (2) from the decoder (14)
The signal when the signal is data to be input / output is supplied to the drive and refresh circuit (15). Also, for example, the upper 2 of the numerical value indicating the track number from the register (12).
The bit signal is supplied to the drive and refresh circuit (15). Further, the clock signal from the oscillator (10) is supplied to the drive and refresh circuit (15). Then, the signal from the drive and refresh circuit (15) is transferred to the memory (2
0) is supplied to the refresh control and chip select terminals, and the output signal of the drive and refresh circuit (15) is supplied to the 128-ary counter (16). Therefore, the counter (16) is driven in association with the write and read control signals and outputs a continuous count value.

In addition, the write or read control signal is sent to the memory (2
It is supplied to the drive circuit (17) of (1) and further to the register (1
The signal of 2 bits having the highest track number from 2) is supplied to the drive circuit (17). Then, the signal from the drive circuit (17) is supplied to the chip select terminal of the memory (21).

Further, the count value of the counter (16), the numerical value of the track number register (12) and the sector number register (13) described above.
And the numerical value of are supplied to the synthesis circuit (18). Further, the signal from the drive and refresh circuit (15) is supplied to the control terminal of the synthesis circuit (18).

The numerical value formed by the synthesis circuit (18) is supplied to the address terminal of the memory (20). Further, the numerical values of the counter (16) and the registers (12) and (13) are supplied to the address terminal of the memory (21). Further, the data buffer circuit (11) is connected to the data terminals of the memories (20) and (21).

Then, in the memories (20) and (21), signals are supplied to the chip select terminals, so that the
One of the two memory sections or the memory (21) is selected,
By writing an address to the address terminal, writing and reading of the designated address are performed.

In this circuit, first, during normal operation, in order to write data in the random access memory (20), the track number and sector number to be written first are supplied through the data bus line (2). It At this time, the track number and sector number identification signals from the decoder (14) are sent to the register (1
2), (13) and these registers (12), (1
The track number and sector number are stored in 3). Further, the upper 2 bits of the register (12) are supplied to the driving and refreshing circuit (15) and the driving circuit (17), and in this case, the signals from the driving and refreshing circuit (15) cause three of the memory (20). One of the memory units is selected.

The data to be written next is supplied through the data bus line (2). At this time, the data input / output identification signal from the decoder (14) is supplied to the buffer circuit (11) and also to the drive and refresh circuit (15), and the timing of data supply from this circuit (15). The counter (16) is driven by a signal related to. And the count value of this counter (16) and the register (12),
The track number and the sector number stored in (13) are supplied to the synthesis circuit (18), and the address number of the memory (20) is formed.

Here, the formation of the address number is performed, for example, by setting the track numbers other than the upper two bits as the upper bits of the address number, the sector numbers as the middle bits, and the count value of the counter (16) as the lower bits.

Then, the data is stored in the address designated by the formed address number, and thereafter, data of 128 bytes is stored in 128 consecutive addresses.

In order to read the random access memory (20), the track number and the sector number for the first read are supplied through the data bus line (2), and these numbers are stored in the registers (12), (13). ), And one of the memory units in the memory (20) is selected. Then, when the data input / output identification signal is supplied from the decoder (14) to the drive and refresh circuit (15), the counter (16) is driven, and the numerical values of the registers (12) and (13) and the counter (16). The data of 128 addresses designated by the count value of 1 is sequentially read.

The read data is supplied to the data bus line (2) through the buffer circuit (11).

Further, at the start of operation in this circuit, first, a predetermined track number and a sector number are supplied through the data bus line (2), and these numbers are registered in the register (1
It is stored in 2) and (13). Then, in this case, the signal of the upper two bits of the register (12) is discriminated by the drive circuit (17) and is set to a numerical value for selecting the read only memory (21). Further, a data input / output identification signal is supplied from the decoder (14) to the drive and refresh circuit (15), the counter (16) is driven, and the numerical values of the registers (12) and (13) and the counter (16) are calculated. 128 specified by the number and
The data of the individual addresses are sequentially read.

In this way, writing and reading of data and further reading of the program are performed. According to the present invention, the track number and the sector number are supplied to the sector through the data bus line (2). The 128 addresses included are written or read, which is equivalent to the writing and reading of the floppy disk described above.

Further, the read-only memory (21) can store a program corresponding to the operation system of the floppy disc, etc., and can be treated exactly like the floppy disc.

Therefore, it is possible to write and read data by using the writing and reading programs of the floppy disk (9) built in the CPU (1) and the ROM (5) as they are. In this case, since the memory (20) is composed of the memory element, there is no delay in mechanical access and the input / output can be performed very efficiently.

That is, according to the present invention, it is possible to provide a high-speed and large-capacity memory in a microcomputer having a relatively small-capacity built-in RAM and a program for driving a floppy disk without internally changing the design. You can

Therefore, processing such as compiler, editing, and sorting can be performed at extremely high speed.

When the scale of the program of the above-mentioned system or the like is small, the capacity of the read only memory (21) may be reduced and the capacity of the random access memory (20) may be increased accordingly.

[Brief description of drawings]

1 and 2 are diagrams for explaining a conventional apparatus, and FIG. 3 is a configuration diagram of an example of the present invention. (1) CPU, (2) data bus line, (3) control bus line, (4) address bus line,
(5) is ROM, (6) is RAM, (7) is input / output circuit, (1
1) is a data buffer circuit, (12) is a track number register, (13) is a sector number register, (14) is a decoder, (15) is a drive and refresh circuit, (16) is a counter, (17) is a drive circuit, (18) is a synthesis circuit, (20) is a random access memory, and (21) is a read-only memory.

Claims (1)

[Claims] 1. A read-only memory, which is a memory device connected as an external device to at least a computer having a program for writing and reading data in a magnetic disk, the read-only memory being divided into a plurality of sectors. A random access memory; a data line for transmitting a sector number and a track number for writing and reading the magnetic disk from the computer; a storage unit for storing the transmitted sector number and track number; A built-in counter that is driven in association with write and read control signals from the computer and outputs a continuous count value; an address signal that forms an address signal based on the output from the storage means and the count value of the built-in counter Forming means, The access memory has a storage capacity that is at least equal to the storage capacity of the data area of one magnetic disk, and writes and reads the read-only memory and the random access memory in sector units according to the formed address signal. A memory device characterized by being connected to the computer so as to have the function of an independent magnetic disk in combination with the magnetic disk connected to a disk controller provided in the computer.