JPH07182523A - Image processing and coding/decoding processing device - Google Patents

Abstract

PURPOSE:To provide the image processing and coding/decoding processing device for arranging a memory for image processing and a memory for coding/ decoding processing on the same address space and further efficiently inputting/ outputting image data while reducing the number of input/output ports by multiplexing a read image data input port and an image data output port with a memory access port. CONSTITUTION:A memory 12 is defined as the shared memory of an image processor 10 and a coding/decoding processing device 11, the request of access from both the processors to the shared memory 12 or to an image data input/ output device 17 is discriminated by a memory access I/F and an image data input/output I/F 1, the division of a basic frequency and a time slot for accessing the shared memory 12 and the image data input/output device 17 is allocated and when the data are completely inputted/outputted corresponding to the access request, a response and answer data are outputted through a signal line 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing / encoding / decoding processing apparatus, and more particularly, to an image processing / encoding apparatus in a device such as a facsimile apparatus or a filing apparatus equipped with image reading means and image output means. The present invention relates to a means for efficiently using a memory for a decoding process.

[0002]

2. Description of the Related Art In a facsimile apparatus, an original read through a photoelectric conversion element is binarized into a black and white signal at the time of transmission, and then compression encoded according to an encoding system recommended by the International Telegraph and Telephone Consultative Committee (CCITT). , Is transmitting. At the time of reception, the transmitted code is inversely decoded and converted into a bit map image, and then the document is reproduced by the recording device. Similar processing is generally performed in the filing apparatus.

In a facsimile apparatus or a filing apparatus which operates in such a procedure, an image is generally read from the time when the original is read through the photoelectric conversion element to the time when the original is binarized or while the code is received and the original is reproduced. Processing is performed. For example, in the reading stage, a γ correction process for improving the reproducibility of a document and an error diffusion process for expressing a multi-valued halftone image in a quasi beautiful manner in binary are performed. Smoothing processing is performed to make jaggedness less noticeable.

In order to realize these image processes, a line memory for several main scanning lines is required, and a dedicated memory must be provided. Further, in the case of facsimile communication using the MR and MMR codes recommended by CCITT, at least one main scanning line memory is required. The filing device also needs the same memory as long as it has the same function.

Conventionally, a memory for encoding / decoding processing is used as a temporary input / output memory for image processing, but retains data that must be stored for image processing. Different from the image processing memory,
It was common to locate in another address space.

When the image processing memory and the encoding / decoding processing memory are arranged in different address spaces in this way, a port for inputting / outputting data individually is required to access each memory. It was uneconomical because there were two circuits that had almost the same function. In addition, the configuration is disadvantageous when considering efficient use of memory.

Regarding the efficient use of the memory, Japanese Patent Laid-Open No. 4-366159 has been proposed, for example. In this conventional technique, a memory used by a CPU for controlling the entire facsimile apparatus and an image processing memory used by an image processing means are arranged in the same address space, and an access request from the CPU is made based on the judgment of the memory access control means. It proposes a method in which the priority order of the access request from the image processing means is determined and the memory is switched and used.

[0008]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
In the related art such as No. 159, the image processing and the encoding / decoding processing are executed by using the ROM or RAM connected to the system bus, and the access request from the CPU and the access request from the image processing means are , I had to wait until the other party's processing was completed, and I could not avoid performance degradation. When higher-speed processing is required, an expensive CPU and a high-speed but expensive memory are required in order to increase the throughput of the system bus, and the economical efficiency is lost.

Further, the relationship between the memory space required by the image processing means and the memory space required by the encoding / decoding processing means is not described, and the configuration is unknown, and the CPU
Alternatively, a device for specially designating an address from the image processing means is required. Therefore, there is a limit in cost reduction by reducing the number of ports.

An object of the present invention is to use an image processing memory and an encoding / decoding processing memory in common in a facsimile apparatus, a filing apparatus, etc., and to execute an image processing and an encoding / decoding processing at high speed. A processing and encoding / decoding processing device is provided.

Another object of the present invention is to perform image processing and coding / decoding by which the memory which the image processing means and the coding / decoding processing means have to access can be accessed from the same port to reduce the number of input / output ports. An object of the present invention is to provide a chemical processing device.

Another object of the present invention is to connect the memory, which the image processing means and the encoding / decoding processing means have to access, to a bus accessed through the same port,
Another object of the present invention is to provide an image processing / encoding / decoding processing device that can use the bus in common with other input / output devices.

[0013]

In order to achieve the above object, the present invention includes a signal processing which includes an image processing means and an encoding / decoding processing means, and which encodes a document or an image after the image is read and image-processed. A memory used for image processing and a memory used for encoding / decoding processing in an image processing / encoding / decoding processing apparatus that performs signal processing of decoding an image data code and then performing image processing to output image data. Proposes an image processing and coding / decoding processing device which is a shared external memory arranged in the same memory address space.

In order to achieve the above-mentioned object, the present invention further includes image processing means and encoding / decoding processing means, and performs signal processing and image data code for encoding after reading a document or image and performing image processing. In an image processing and coding / decoding processing apparatus that performs image processing after decoding and signal processing for outputting image data, a memory used for image processing and a memory used for coding / decoding processing are the same memory. A memory access processing unit, which is a shared external memory arranged in an address space, determines access to the shared external memory from the image processing unit and the encoding / decoding processing unit, and allocates the shared external memory to image processing or encoding / decoding processing. An image processing and coding / decoding processing apparatus including the above is proposed.

The present invention further includes image processing means and encoding / decoding processing means to achieve the above object,
An image processing and an encoding / decoding processing apparatus that perform signal processing of reading a document or image and performing image processing and then encoding, and image processing of decoding image data code and then image processing and outputting image data The memory used for and the memory used for encoding / decoding processing are shared external memories arranged in the same memory address space,
The shared external memory is provided with a memory access processing unit that determines access from the image processing unit and the encoding / decoding processing unit to divide the shared external memory into image processing or encoding / decoding processing. The present invention proposes an image processing and coding / decoding processing device having a bus connection between them.

When the memory access processing means, the image processing means, and the encoding / decoding processing means are integrated in a single-chip LSI, the shared external memory is accessed through a common input / output port formed inside the LSI.

In order to achieve the above object, the present invention includes an image processing means and an encoding / decoding processing means, and performs image processing on a document or image read by a reading device connected to a common bus and then encodes the image. In the image processing and the encoding / decoding processing apparatus, which performs the signal processing for converting and the signal processing of decoding the image data code and then outputting the image data to the recording device connected to the common bus, The memory used and the memory used for the encoding / decoding processing are shared external memories connected to a common bus and arranged in the same memory address space, and the image processing means and the code for the shared external memory or the reading device or the recording device are provided. The shared external memory, the reading device, or the recording device is subjected to image processing or encoding / decoding by determining the access from the encoding / decoding processing means. It is to propose an image processing and encoding and decoding apparatus having a memory access and image data input processing means distributes the processing or image reading or output.

When the memory access processing means, the image processing means and the encoding / decoding processing means are integrated in a single chip LSI, the common bus is accessed through a common input / output port formed inside the LSI.

When the A / D converter is connected to the common bus, the memory access and image data input / output processing means can include means for controlling the output ready signal of the A / D converter.

Further, the memory access and image data input / output processing means can also include a data set timing control means of the recording device, and when the display has a port for inputting display data, this input port In the case of having a port for inputting data to the storage device connected to the common bus, the data set timing control means for the input port to the storage device can be included.

[0021]

According to the present invention, means for discriminating between the memory access request from the image processing means and the memory access request from the encoding / decoding processing means, and uniformly controlling so as to secure an appropriate memory area for each. Since the image processing unit and the encoding / decoding processing unit do not need to generate a memory address, the circuit and the processing procedure can be simplified because the image processing device and the port are provided.

Further, since a bus coupling method is adopted in which the image processing means and the encoding / decoding processing means access the independent memory from the system bus commonly accessed through the unified port, other data can be input to the unified port. By setting a control signal for controlling the input / output state of data including the output device, another data input / output device can be coupled to the bus. For example, if the input / output port is provided with a control circuit for controlling the output ready of the A / D converter and a signal line, the data input pin of the A / D converter and the data input / output pin of the memory can be used in multiple. Saves hardware for data input and output,
The cost can be reduced.

Further, a memory and peripheral devices commonly accessed by the image processing means and the encoding / decoding processing means are connected to a bus independent of the system bus, and the encoding / decoding for image processing is also performed. Each process can be time-divided with a time slot having a sufficient margin for the process. Also,
By recognizing the processing means that has made an access request to the memory and peripheral devices and assigning each slot appropriately, it is possible to execute access processing according to the urgency of processing without degrading processing performance. Is.

Specifically, when considering the operation of reading and coding an image, for example, an input original is read by a photoelectric conversion element such as a CCD, converted into digital multi-valued image data by an A / D converter, and the image is converted. Input data to the image processing means. The input multi-valued image is image-processed and then encoded.
The number of external input / output pins can be reduced by multiplexing the multi-valued image data input port to the image processing means and the port for accessing the memory used by the image processing means and the encoding processing means. Further, if a bus is used in common with the image data output means for image recording, the number of input / output pins can be further reduced and the cost can be reduced.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of an image processing and coding / decoding processing apparatus according to the present invention will be described below with reference to FIGS.

FIG. 1 is a block diagram showing a basic configuration of an embodiment of an image processing and coding / decoding processing apparatus according to the present invention. Here, the image data input / output device 17 comprehensively represents an image reading device for inputting image data and a recording device for outputting image data. As described above, conventionally, the memory accessed by the image processing means 10 and the memory accessed by the encoding / decoding processing means 11 are arranged in different address spaces. That is, the input of data from the image reading device and the output of data to the recording device are performed through separate input / output ports. On the other hand, in the present embodiment, the memory access I as the memory access processing means.
/ F (interface) and image data input / output I / F 1 as image data input / output processing means, and the memory 12 is shared by the image processing means and the encoding / decoding processing means.
Further, the input / output ports for the memory 12 and the image data input / output device 17 are shared.

The signal line group 2 comprises a data signal line 3, an address signal line 4 and an input / output control signal line 5, and a signal line group 6
Comprises a data bus 7, an access request / response signal line 8 and an input request / response signal line 9.

Here, a series of flow for taking in image data, performing image processing and encoding processing will be described. Image processing means 1
0 captures image data from the image data input device, that is, the image reading device 17, via the image data input / output I / F 1. The image processing means 10 performs high image quality processing in order to improve the image quality of the captured image. In order to execute this image processing, the image data up to several lines before is referred to, or the error component data between the slice level and the actual density level during the binarization process up to several lines ago is referred to. Or At that time, it is necessary to refer to the image data and the error component data accumulated in the memory 12 up to several lines before, and the memory 12 is accessed several times. This type of image processing is general as a high-quality image processing and is a known technique to a person skilled in the art related to a facsimile machine, and therefore detailed description thereof will be omitted.

Depending on the execution method of the high image quality processing, the memory 1
Number of accesses to memory 2 and memory 1 from other processing means
Since the number of accesses to 2 changes, the number of memory access request signals for the memory access I / F and the image data input / output I / F 1 differs. Further, since the image processing means 10 and the memory access process are asynchronous processes, a response signal to the access request is also required. Here, the total number of signals on the input request / response signal line 9 for transmitting the input / output request signal and the response signal is assumed to be m. The data is processed by the image processing means 10 through the data bus 7.
Is input and output to. The width of this data bus is generally 8,
Although it is 16 bits, since it is not particularly limited, n bits are used here.

In the encoding processing of the encoding / decoding processing means 11, it is not necessary to access the memory 12 in the case of the one-dimensional MH encoding processing method, but in the MR and MMR two-dimensional encoding processing method, the immediately preceding Since it is necessary to refer to the image data of the main scanning line, the image data stored in the memory 12 is accessed. Similarly to the access at the time of the image processing, the access at the time of the encoding processing makes the access request and the response thereto via the access request / response signal line 8. Here, the total number of signals is assumed to be p. At the time of encoding, 2 of read request and its response
You can access the book.

The memory access I / F and the image data input / output I / F 1 are transmitted from the encoding / decoding processing means 11 via the access request / response signal line 8 and the data bus 7.
It receives an access request, returns a response and request data, and returns a response and request data from the image processing means 10 via the input request / response signal line 9 and the data bus 7. As will be described later in detail with reference to FIGS.
/ F and the image data input / output I / F 1 takes timing to access the memory 12, inputs / outputs an input / output control signal and a control signal through the signal line 5, inputs / outputs an address signal through the address signal line 4, and outputs the data. Data is input and output through the signal line 3. The input / output control signal using the signal line 5 and the address signal using the signal line 4 are determined based on the number of functional processes required to be input / output to / from the memory 12 and the total memory amount. Each k
Book and i book. Data input / output does not have to be limited to the parallel input / output bit system, so that the number of data is set to h. The memory access I / F and the image data input / output I / F 1 manage the input / output of image data, shift from image processing for high image quality to encoding, and show the encoded signal from the output line 14. Not output to MPU, etc.

Next, the decoding process will be briefly described. The procedure of the decoding process proceeds from the reading to the reverse of the procedure of the encoding process. As shown in FIG. 1, the code to be decoded is input from the signal line 15 to the coding / decoding processing means 11, and if the processing is the reverse of the coding, that is, in the case of MR and MMR two-dimensional decoding, the image of the immediately preceding line is displayed. Since the data must be decoded while referring to it, the memory access request is output to the access request / response signal line 8, and the response to this request is also received through the signal line 8 and the necessary image data is sent through the image bus 7. It receives and decodes while referring to the image data.

If smoothing or reduction / enlargement processing of the restored image is required, image processing is further performed by the image processing means 10 with reference to the memory 12 in which necessary image data is accumulated, and an image data output device, that is, image recording. Image data is output from the signal line 5 to a display unit such as a device or a CRT.

As shown in FIG. 1, when the image data input / output device 17 is connected to the signal line 2 in addition to the memory 12, a selection signal for accessing the image data input / output device 17 is also supplied by the input / output control signal line 5. Can be output. When the image data input / output device 17 is selected, the image data for the image data input / output device 17 is placed on the data signal line 3 so that the input / output to / from the memory 12 is prohibited. This function can be easily realized by using a 3-state input / output device. Memory access I /
If the F and the image data input / output I / F 1 are configured and connected as shown, the memory 12 and the image data input / output device 1
It is not necessary to distinguish 7 from each other, and they can be uniformly accessed from the memory access I / F and the image data input / output I / F 1.

Next, the structure of the memory access I / F and the image data input / output I / F1 and the memory access timing, which are the main points of the present invention, will be described.

Memory access and image data input / output I
The access timing for the memory 12 of / F1 and the data input / output timing for the image data input / output device 17 are generally asynchronous processes. Therefore, the memory access I / F is used to determine at which timing and where to access.
Also, a function of managing the image data input / output I / F1 and responding to the request source when the input / output processing of the data requested to be accessed is completed is required.

FIG. 2 is a block diagram showing an example of the configuration of the memory access and image data input / output I / F 1 in the embodiment of FIG. The access request determination / response timing generation means 24 determines which processing means has issued the access request, and notifies the time slot division / allocation means 23 of the result. If it is a data write request to the memory 12, the data to be written is latched in the data input / output buffer 20, and the write signal is generated by the input / output control signal generating means 22 at the timing of the assigned time slot to generate the address. An appropriate address is output from the generation means 21 and the data is written in the memory 12 through the data signal line 3. Then, the completion of writing is notified to the access request source through the signal lines 8 and 9.

On the other hand, when the request is for reading data from the memory 12, the read signal is generated from the input / output control signal generating means 22 at the timing of the assigned time slot and the appropriate address is generated from the address generating means 21. Output and output the data through the data signal line 3 to the memory 1
The data is read from No. 2, and the data is temporarily latched in the data input / output buffer 20. Then, the completion of reading is notified to the access request source through the signal lines 8 and 9, and the access source extracts the necessary data through the data bus 7.

FIG. 3 is a diagram showing an example of memory access timing divided by time slots in the embodiment of FIG. Time slot division and allocation means 23
3 determines whether the process at that time is a read encoding process or a process for decoding and outputting restored image data according to a state preset by a system control MPU or the like not shown in FIG. Set the base frequency and the number of time slots above the required minimum. The base frequency and the number of time slots above the required minimum may be set appropriately as needed, and are not particularly limited, and therefore are shown by cutting the dotted line in FIG. Data input / output processing for an access request output from each processing means is allocated to each appropriately set time slot. For example, in the period divided by the base frequency as shown in the figure, data read (read), data write (write), and data write are allotted to the first time slot. The section 22 controls the read / write signal of the input / output control signal line 5. In synchronization with this, the address generating means 21 generates an appropriate address. In this manner, it is possible to realize a device capable of appropriately accessing an appropriate area in the memory 12 and responding to the image processing unit 10 or the encoding / decoding processing unit 11 that is the access request source.

FIG. 4 is a block diagram showing the configuration of an embodiment of a facsimile system incorporating the image processing / encoding / decoding processing apparatus of FIG. The image processing / encoding / decoding processing apparatus 52 according to the present embodiment uses the memory access I
/ F and image data input / output I / F1, image processing means 10, encoding / decoding processing means 11, and MPUI / F53 for inputting / outputting commands and data of the microprocessor unit MPU54 for controlling the system. , And is connected to the shared memory 12.

The memory access I / F and the image data input / output I / F 1 are a memory access I / F 41, an image data input I / F 51 for inputting image data from the document reading device 50, and an image data input to the recording device 60. And an image data output I / F 59 for outputting. That is, the image data input / output I / F part of the present embodiment is the I / F of the image processing means 10, the reading device 50, and the recording device 60.
Has become.

The facsimile system is connected to the image processing / encoding / decoding processing device 52, the document reading device 50, the recording device 60, the system bus 58, and the system memory 5 for storing the system program.
5, an I / O device 56 such as an operation panel, and a communication means 57 connected to a public line to perform facsimile communication.

FIG. 5 shows the implementation of a facsimile system in which the image data input / output I / F portion is multiplexed in the embodiment of FIG. 4 in order to make the image processing and encoding / decoding processing device 52 compact and further reduce the cost. It is a block diagram which shows the structure of an example.

In this embodiment, an enable control signal for the memory 12, a selection control signal for permitting the input of image data from the reading device 50, and a recording device for the input / output control signal line 5 which is a component of the signal line 2. The data signal line 3 for the memory access I / F and the image data input / output I / F1 has a bus structure by providing a function of outputting a selection control signal for outputting image data.

With this bus configuration, the input / output ports of the image data input / output I / Fs 51 and 59 are deleted from the image processing / encoding / decoding processing device 52 in the embodiment of FIG. And encoding / decoding processing device 5
2 is transformed into the image processing and encoding / decoding processing device 70, and a compact and low-cost facsimile system with a small number of input / output ports can be realized.

A large effect of downsizing and cost reduction is when the reading device 50 and the recording device 60 handle parallel input / output data of several bits, and the input width is the same as the input / output parallel data size of the memory 12. If output, the greatest effect can be obtained.

FIG. 6 is a diagram showing an example of access timing to the memory and the image data input / output device divided by time slots in the embodiment of FIG. 5, divided by time slots. Time slots in the first part of the repetition base frequency are used for memory access, and the latter two time slots are assigned to input / output of data to / from the reading device 50 and the recording device 60.

In the case of the present embodiment, since the memory access and the access to the reading device 50 and the recording device 60 can be performed in the same way, even if they are multiplexed and the same port is used,
The load on the circuit hardly increases.

FIG. 7 is a block diagram showing the configuration of the embodiment of the facsimile system in which the connection position of the recording apparatus is changed in the embodiment of FIG.

In this embodiment, the recording device 60 connected to the bus 2 in FIG. 5 is disconnected, and the recording device 60 is directly connected to the memory access I / F and the image data input / output I / F1 for image processing. An example in which the encoding / decoding processing device 52 is modified to the device 72 is shown.

In this embodiment, a dedicated image data output port for the recording device is required on the memory access I / F and image data input / output I / F1 side, but data output to the recording device is serial output. In such a case, the selection signal to the recording device 60, which was necessary in the embodiment of FIG. 5, is unnecessary, so that the number of output pins does not increase.

When the image data of the reading device 50 is output in parallel, the device can be made more compact and the cost can be reduced as in the embodiment of FIG.

The image data output timing to the recording device 60 may be a method of allocating time slots as shown in FIG. 6, but since image data can be output independently from the bus 2, it is possible to use a unique method. It is also possible to output at the timing, and the degree of freedom of the recording process becomes greater.

FIG. 8 is a block diagram showing the configuration of an embodiment of the facsimile system in which the connection position of the recording device 60 is changed in the embodiment of FIG.

In this embodiment, the image data from the image processing means 10 is sent to the recording device 6 through the image data output I / F 59.
It outputs to 0.

Similar to the embodiment of FIG. 7, when the image data output to the recording device 60 is serial output, the image processing and coding / decoding are performed so that the image data is directly output from the image processing means 10. It is more convenient to transform the processing device 52 into a device 72 and the number of output pins does not increase.

Generally, the image data output to the recording device 60 used in a facsimile system or the like is often serial output. On the other hand, the reading device 50
The image data output from the device is often a parallel output of several bits. Therefore, basically, the configuration of the embodiment of FIG. 4 is adopted.

On the other hand, the image data output to the recording device 60 is a parallel output of several bits, and the reading device 5
If the image data output from 0 is serial, the recording device 60 should be coupled to the bus 2 and the reading device 50 should be connected to the image data input I / F 1. That is, FIG.
Alternatively, the connection system in which the positions of the reading device 50 and the recording device 60 of FIG. 8 are interchanged may be advantageous.

The output destination of the image data is the recording device 60.
However, it is clear that the present invention can be applied even if the output destination is a memory device such as a display device or a hard disk.

When the image processing and coding / decoding processing apparatus of the embodiments shown in FIGS. 4, 5, 7, and 8 is configured as an LSI logic, the number of pins of the LSI can be reduced to make it compact. Cost reduction is possible.

Further, in the facsimile system and the filing system, not only the image processing and coding / decoding processing device portion is integrated as an LSI logic, but also to another I / O device as shown in the embodiment of FIG. If the I / O control part and the control port for the communication means are integrated together, the number of input / output ports is increased more than it looks, and the size and cost can be further reduced.

[0062]

According to the present invention, the memory accessed by both of the image processing and encoding / decoding processing apparatuses can be set in the same address space without degrading the performance of the image processing and encoding / decoding processing apparatuses. The number of I / O ports can be reduced without the need.

Further, for example, an input port for inputting digitized image data output from the image data reading device to the same input / output bus to which the memories used by the both processing devices are connected, and recording of the image data. A device, display device, or device that stores image data can be connected with the same processing configuration as when accessing the memory, so when inputting and outputting image data in parallel, a pin for inputting and outputting data The number can be reduced.

Furthermore, since the number of input / output ports can be reduced, the cost performance of the image processing / encoding / decoding processing apparatus is improved. In particular, when the logic configuration is an LSI, the number of input / output pins can be reduced, and an LSI with high cost performance can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing a basic configuration of an embodiment of an image processing and coding / decoding processing apparatus according to the present invention.

2 is a block diagram showing an example of a configuration of a memory access I / F and an image data input / output I / F in the embodiment of FIG.

3 is a diagram showing an example of memory access timing divided by time slots in the embodiment of FIG. 1;

FIG. 4 is a block diagram showing the configuration of an embodiment of a facsimile system incorporating the image processing / encoding / decoding processing apparatus of FIG.

5 is an image data input / output I / F in the embodiment of FIG.
It is a block diagram which shows the structure of the Example of the facsimile system which multiplexed the part.

FIG. 6 is a diagram showing an example of access timings of a memory and image data input / output devices divided by time slots in the embodiment of FIG.

7 is a block diagram showing the configuration of another embodiment of the facsimile system in which the connection position of the recording device is changed in the embodiment of FIG.

8 is a block diagram showing the configuration of another embodiment of the facsimile system in which the connection position of the recording device is changed in the embodiment of FIG.

[Explanation of Codes] 1 Memory access I / F and image data input / output I / F
F 2 signal line group 3 data signal line 4 address signal line 5 input / output control signal line 6 signal line group 7 data bus 8 access request / response signal line 9 input request / response signal line 10 image processing device 11 encoding / decoding process Device 12 Memory 13 Image data input signal line 14 Encoded signal output line 15 Decoded signal input line 16 Image data output signal line 17 Image data input / output device 20 Data input / output buffer 21 Address generator 22 Input / output signal generator 23 Time Slot division / allocator 24 Access request determination / response timing generator 50 Reader 51 Image data input I / F 52 Image processing and encoding / decoding processor 53 MPUI / F 54 MPU 55 System memory 56 Other input / output devices 57 communication means 58 system bus 59 image data output I / F 0 storage device 70 image processing and coding decoding apparatus 71 image processing and coding decoding apparatus 72 image processing and coding decoding apparatus

Claims (10)

[Claims] 1. A signal processing unit including an image processing unit and an encoding / decoding processing unit, which reads a document or image and performs image processing and then encoding, and image data after decoding a image data code and outputting image data. In the image processing and coding / decoding processing device that performs the signal processing, the memory used for the image processing and the memory used for the coding / decoding processing are shared external memories arranged in the same memory address space. An image processing and encoding / decoding processing device characterized by the above. 2. A signal processing unit including an image processing unit and an encoding / decoding processing unit, which reads a document or image and performs image processing and then encoding, and image data processing after decoding the image data code. In the image processing and encoding / decoding processing device for performing signal processing, the memory used for image processing and the memory used for encoding / decoding processing are shared external memories arranged in the same memory address space, A memory access processing unit that determines access to the shared external memory from the image processing unit and the encoding / decoding processing unit and allocates the shared external memory to the image processing or the encoding / decoding process. Image processing and encoding / decoding processing device. 3. A signal processing unit including an image processing unit and an encoding / decoding processing unit, which reads a document or image and performs image processing and then encoding, and image data decoding and then image processing to output image data. In the image processing and encoding / decoding processing device for performing signal processing, the memory used for image processing and the memory used for encoding / decoding processing are shared external memories arranged in the same memory address space, The shared external memory includes a memory access processing unit that determines access from the image processing unit and the encoding / decoding processing unit to the shared external memory and allocates the shared external memory to the image processing or the encoding / decoding process. An image processing and coding / decoding processing apparatus characterized in that a bus connection is made between the memory access means and the memory access means. 4. The image processing and coding / decoding processing device according to claim 2, wherein the memory access processing unit, the image processing unit, and the coding / decoding processing unit are integrated in a single-chip LSI. An image processing and encoding / decoding processing device characterized by accessing the shared external memory through a common input / output port formed inside the LSI. 5. A signal processing including image processing means and encoding / decoding processing means, image processing of a document or image read by a reading device connected to a common bus, and decoding after image processing In an image processing and encoding / decoding processing device, which performs image processing after conversion to image data and outputs image data to a recording device connected to the common bus, a memory used for image processing and an encoding / decoding process. The memory used for is a shared external memory connected to the common bus and arranged in the same memory address space, and the image processing means and the encoding / decoding process for the shared external memory or the reading device or the recording device. Access to the shared external memory, the reading device, or the recording device to determine whether the image processing or the code is performed. Image processing and coding decoding apparatus characterized by comprising a memory access and image data input processing means distributes the decoding process or the image read or output. 6. The image processing and coding / decoding processing device according to claim 5, wherein the memory access processing unit, the image processing unit and the coding / decoding processing unit are integrated in a single chip LSI, An image processing and coding / decoding processing apparatus characterized in that the common bus is accessed through a common input / output port formed inside the LSI. 7. The image processing and coding / decoding processing device according to claim 5, wherein an A / D converter is connected to the common bus, and the memory access and image data input / output processing means includes: An image processing / encoding / decoding processing apparatus including means for controlling an output ready signal of an A / D converter. 8. The image processing / encoding / decoding processing apparatus according to claim 5, wherein the memory access and image data input / output processing means includes a data set timing control means of the recording apparatus. Image processing and encoding / decoding processing device for facsimile. 9. The image processing and coding / decoding processing device according to claim 5, 6 or 8, wherein said memory access and image data input / output processing means has a port for inputting display data to a display. A facsimile image processing and encoding / decoding processing apparatus, which further comprises data set timing control means for the input port. 10. The image processing and coding / decoding processing device according to claim 5, 6 or 8 or 9, wherein the memory access and image data input / output processing means is in a storage device connected to the common bus. A facsimile image processing and encoding / decoding processing apparatus having a port for inputting data and including data set timing control means of an input port to the storage device.