JPH07174825A - Equivalent trouble extracting method and apparatus - Google Patents

Abstract

PURPOSE:To lessen the number of processes and time necessary for a logic composing means by defining a trouble, producing the whole number test patterns, carrying out trouble simulations to produce a trouble dictionary, and extracting an equivalent trouble from the trouble dictionary. CONSTITUTION:A circuit description of a functional gate 100 is put in. The whole number test patterns 220 are produced by the whole number test pattern producing means 210. Troubles 160 are produced by a trouble defining means 150. A trouble dictionary 260 is produced by utilizing a trouble simulation means 250. The dictionary 260 is composed as a corresponding table of the input test patterns, the troubles detectable by the test patterns, and external terminals in which the troubles are detected. An equivalent trouble 140 is extracted by putting the dictionary 260 in and utilizing an equivalent trouble extracting means 270. As a result, a trouble extracting method by which a test pattern can be produced at high speed and high precision without utilizing a logic composing means is obtained even in the case a theoretical circuit is not expressed as a basic logic gate network.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic circuit fault simulation method, and more particularly to a logic circuit equivalent fault extraction method and apparatus.

[0002]

2. Description of the Related Art Test designing of logic circuits has become more and more important as the scale of circuits increases. The test design aims to avoid the shipment of defective products by designing a test pattern having excellent manufacturing defect detection capability and testing a circuit using the test pattern. In order to realize this test design, the following three concepts are important.

(1) Logic failure: Various physical defects have been reported as the causes of circuit manufacturing defects, but it is very difficult to handle them as they are in test design. Therefore, in general, a fault is simplified by using a logic fault focusing only on the logical behavior of the circuit. Among the logical faults, the stuck-at fault is generally widely used because of its ease of handling and the wide range of physical defects that can be covered.

Stuck-At-Fault means that the state of the input / output terminals of the logic circuit is "1" or "0".
It is a failure model that is assumed to be fixed (changes) to, and is referred to as a stuck-at-1 failure and a stuck-at-0 failure, respectively.

(2) Test pattern generation: For circuits with deep logic represented by a microprocessor, a function verification test pattern or a random test pattern cannot often provide sufficient manufacturing defect detection capability. Therefore,
With respect to the remaining failures that cannot be detected by these existing test patterns, a method of generating a detectable test pattern to supplement the manufacturing defect detection capability is generally performed.
Although automatic test generation is used as a means to do this automatically, an effective method for large-scale sequential circuits has not been reported.

(3) Test pattern verification: Generally, a test pattern generated for a certain fault also functions as a test pattern for another fault. Reduction of the number of test patterns using this relationship is generally performed.

In order to be able to reduce, it has to be determined which fault in the logic circuit the given test pattern detects. Failure simulation is used as a means for this.

The fault simulation is considered to be the same process as the logic simulation in principle, except that the logic operation of a circuit in which a fault exists is simulated, but there is a big difference in terms of calculation time.
The calculation amount of the logic simulation is O (n ² ) (n is the number of gates), whereas the fault simulation is O (n ² ).
³ ), which has the property that the difference in calculation time increases as the circuit scale increases.

Therefore, as one of the means for reducing the calculation time (simulation time) required for the fault simulation, the equivalent compression of the fault is generally performed.

Assuming that there are two faults, f1 and f2, a test pattern set for detecting the fault f1 and a fault f2.
When the test pattern set for detecting
1 and f2 are said to have an equivalent relationship with each other, and the failure f1 (f
2) is said to be an equivalent fault of the fault f2 (f1).

When there is an equivalent fault among the faults, it is only necessary to simulate one of them as a representative fault, and the remaining equivalent faults are detected by the representative faults. equal. In this way, the simulation time can be easily reduced by targeting a failure consisting of a representative failure instead of all failures (this is called "equivalent compression").

As described above, if the equivalent compression of faults is used, the fault simulation time can be easily reduced. The conventional equivalent fault extraction method is shown in FIG.
As shown in (A) and (B), it was intended for a basic logic gate or a basic logic gate network in which basic logic gates are combined.

FIG. 3A shows an example of the basic logic gates. Each basic gate (50, 51, 52, 53, 5).
4, 55) have equivalent faults classified by a square “□” or a triangle “Δ”. Squares and triangles in the figure represent faults defined in each node (or net). For example, for the inverter gate 50, it is shown that the test patterns for detecting the output 0 fault and the input 1 fault are the same, that is, these faults are equivalent to each other.

Further, FIG. 3B shows an example of a logic gate network, which has an equivalent fault surrounded by a dotted line. The reason for this is as follows.

The faults defined at the inputs and outputs of the basic logic gates (56, 58, 59) are as shown in FIG. 3 (A). Then, the basic logic gate (NOR) 56
Output 0 failure and the first of the basic logic gates (AND) 58
The 0-input fault is in an equivalent relationship via the net 57. More specifically, the test pattern for detecting the output 0 fault of the basic logic gate 56 is (a, b, c) = (0,
0,0) only, and the first input 0 of the basic gate 58
The test pattern for detecting a failure is also the same as this test pattern.

The equivalence relation of the input / output failure of the net differs depending on whether the net is fan-out free or not. If the net is fan-out free, the I / O faults are equivalent faults to each other, and if the net is not fan-out free, they are not equivalent faults to each other. Net 60 of FIG. 3 (B)
Is not fan-out free, the output failure of the basic logic gate (inverter) 59 is not equivalent to the failure of the y terminal.

If the logic circuit provided in this way is a basic logic gate network, the conventional technique is sufficient, but if it is not, the processing shown in FIG. First, the logic circuit must be converted into a basic logic gate network.

This will be described in detail with reference to FIG.
It is assumed that the given logic circuit is a functional gate 70 having a Boolean expression 90 or a truth table 80 as shown in FIG. 4, for example.

In the case of the prior art, the functional gate shown in FIG. 4 cannot be processed as it is, and as shown in FIG. 5, a logic synthesizing means 110 is used for the input functional gate 100 to obtain an equivalent basic logic. It must be converted into the gate network 120. The basic logic gate network of FIG. 3B shows an example in which the functional gate 70 of FIG. 4 is converted by the logic synthesizing means 110.

Although the logic synthesizing means 110 is limited here to means for generating a basic logic gate network from functional gates, generally, a circuit description at a higher design level (system level, architecture level, register transfer level) is input. However, it is a means for outputting a circuit description at a logic gate level (gate level, switch level), and has been widely used in recent years. However, the calculation time (synthesis time) required for the logic synthesizing unit 110 tends to explosively increase as the circuit scale increases.

Next, the fault 160 is defined in the functional gate 100 by using the fault definition means 150. Specifically, the definition of a fault means to assign to the input terminal and the output terminal of the functional gate 100 as a stuck-at-0 fault and a stuck-at-1 fault, as an example is shown in the functional gate 70 of FIG. In the function gate 70 of FIG. 4, for example, a
0 and a1 respectively represent 0 and 1 stuck-at faults of the input a, and x0 and x1 respectively represent 0 and 1 stuck-at faults of the output x.

Finally, the basic logic gate network 12
For 0 and the fault 160, the equivalent fault described with reference to FIGS. 3A and 3B is extracted by the equivalent fault extraction means 130 and output as the equivalent fault 140. An example of the equivalent fault 140 for the functional gate 70 of FIG. 4 is shown in FIG. An example of this equivalent fault will be described later.

[0023]

In the conventional equivalent fault extraction method described above, for a logic circuit which is not a basic logic gate network, a logic synthesizing means can be used to generate a basic logic gate network equivalent to the logic circuit. Therefore, there is a problem that it requires a lot of man-hours and time.

Therefore, an object of the present invention is to solve the above-mentioned problems, and even when the logic circuit is not represented as the basic logic gate network, without using the logic synthesizing means,
An object of the present invention is to provide a fault extraction method capable of generating a test pattern at high speed and with high accuracy.

[0025]

To achieve the above object, the present invention comprises: (a) inputting a circuit description of a logic circuit; and (b) generating a 100% test pattern for the logic circuit. (c) a step of defining a fault for the logic circuit, (d) a step of performing a fault simulation based on the defined faults and the total test pattern, and generating a fault dictionary, and (e) the fault A method of extracting faults having an equivalent relationship from a dictionary, and an equivalent fault extraction method comprising:

The present invention further comprises means for inputting a circuit description of a logic circuit, means for defining a fault in the logic circuit,
Means for generating a 100% test pattern of the logic circuit;
Means for inputting the logic circuit, a 100% test pattern, and faults to generate a fault dictionary by fault simulation;
And an equivalent fault extracting means for extracting the equivalence relation of the faults by referring to the fault dictionary.

[0027]

Embodiments of the present invention will be described below with reference to the drawings.

[0028]

[Embodiment 1] FIG. 1 is a functional block diagram showing an embodiment of an equivalent fault extraction method according to the present invention. As shown in the figure, first, the circuit description of the functional gate 100 is input, the 100% test pattern generating means 210 is used to generate the 100% test pattern 220, and the fault defining means 150 is used to generate the fault 160. In the total test pattern generation means 210, when the number of input terminals of the functional gate is n, 2
^N combinations of patterns are generated.

Next, the 100% test pattern 220 and the faults 160 are input, and the fault simulation means 250 is used to generate a fault dictionary 260. The failure dictionary 260 is
It is configured as a correspondence table of an input test pattern, a fault that can be detected by the test pattern, and an external terminal in which the fault is detected.

Here, a specific example of the fault dictionary 260 will be described with reference to FIG. FIG. 2A is the same as FIG.
The example of the failure dictionary regarding the functional gate 70 shown in FIG. As shown in the figure, in the fault dictionary 300, detected faults corresponding to the test patterns are arranged for each test pattern, and (x | y) of the detected faults indicates the fault detected at the output terminals x and y. ing. For example, the test pattern of test pattern number 8 (a, b, c) = (1, 1, 1)
, The fault that can be detected at the output terminal x is {x1}, that is, the stuck-at-1 fault of the output x, and the fault that can be detected at the output terminal y is {c0, y1}, that is, the stuck-at-0 fault of the input c and the output y. 1 is a stuck-at fault.

As the last step of the process of FIG. 1, the fault dictionary 260 is input and the equivalent fault extraction means 270 is used to extract the equivalent fault 140. FIG. 2B shows an example of an equivalent failure of the 3-input 2-output functional gate 70 of FIG. In the figure, the symbol "{}" represents a set, {} enclosing the entire set represents a set of equivalent faults, and each {} represents a constituent element of the equivalent fault. For example, the equivalent fault {a1, b1, x
0} corresponds to the equivalent failure of the input terminal and the output terminal in the basic logic gates 56 and 58 surrounded by the dashed line in the basic logic gate network of FIG. 3 (B).

Next, with reference to FIGS. 5 and 6, a total test pattern generation means 210 and an equivalent fault extraction means 270.
Will be described.

FIG. 5 shows a total test pattern generation means 210.
The detailed processing flow of is shown. The process flow of FIG. 5 will be described as a specific example using the 3-input 2-output function gate 70 of FIG.

The inputs to the function gate 70 are a, b, and c,
Initialize S to the empty set and variable k to 0 (step 40
0).

The test pattern of the functional gate is (a, b,
As described in c), in the determination of the size of the variable k (step 410), since k (= 0) <2 ³ , the first loop is entered, and S = (0,0,0) ^U A calculation process of S (= empty set) is performed (step 420).

After that, the variable k is incremented (step 430) and the processing in the loop is repeated until the condition of the branch decision 410 is not satisfied (k ≧ 2 ³ ), S = {(0,0,0 ), (0,0,1), ..., (1,1,1)}, and the test pattern shown in the example of the fault dictionary in FIG. 2A is obtained.

FIG. 6 shows a detailed processing flow of the equivalent fault extraction means 270. The processing will be specifically described with reference to the drawings.

In the example of the fault dictionary of FIG. 2A, when the detection test pattern set for the fault is obtained (step 500), S is given by the following equation (1).

[0039]

[Equation 1]

Here, for example, a0: (5x) is the failure a0.
Indicates that the fifth pattern can be detected by the external terminal x.

P = empty set, and then branch decision 510 S
Is not an empty set, the process proceeds to step 520, and the first element a0 of S is moved from S to P (step 520).
Then, S and P are expressed by the following equation (2).

[0042]

[Equation 2]

Next, the element of S is searched for a fault whose detected test pattern set matches that of a0 (step 53).
0). In this case, S and P do not change because there is no such fault. That is, the process returns to the branch determination 510 and S
Is not an empty set, processing 520 is executed.

The element a1 next to S is moved from S to P (step 520).

In the element S, the detected test pattern set is a1
Search for a failure that matches that of (step 530).

In this case, b1 and x0 are found and they are moved from S to {a1} (step 540). As a result, S and P are expressed by the following equation (3).

[0047]

[Equation 3]

The above process is repeated, and the loop ends when S becomes an empty set. At this time, S and P are given by equation (4).

[0049]

[Equation 4]

The equivalent fault 310 of FIG. 2B is obtained for the set P of the above equation (4).

In the present embodiment, the stuck-at fault is used as the fault defined in the functional gate. However, the present invention can be similarly applied to a fault model other than the stuck-at fault, such as a short-circuit fault. Of course. Furthermore, the present invention is not limited to the above-mentioned embodiments, but includes various embodiments according to the principle of the present invention.

[0052]

As described above, the equivalent fault extraction method of the present invention inputs a logic circuit which is not a basic logic gate network without using a logic synthesizing means for converting it into a combination of basic logic gates. A fault in the specified logic circuit, and generate a 100% test pattern,
By executing the fault simulation based on the fault and the test pattern to generate the fault dictionary and extracting the equivalent fault from the fault dictionary, the man-hour and time required for the logic synthesizing means can be significantly reduced.

Further, according to the equivalent fault extracting apparatus of the present invention, the equivalent fault is directly output from the logic circuit without using the logic synthesizing means, and the equivalent compression test pattern holding a constant fault coverage is made highly efficient. It can be automatically generated.

[Brief description of drawings]

FIG. 1 is a functional block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a diagram illustrating an embodiment of the present invention. (A) It is an example of a failure dictionary. (B) This is an example of an equivalent fault.

FIG. 3 is a diagram illustrating a conventional technique. (A) An example of an equivalent fault of the basic logic gate. (B) An example of a basic logic gate network and its equivalent fault.

FIG. 4 is a diagram illustrating a Boolean expression and a truth table for explaining an example of a functional gate.

FIG. 5 is a functional block diagram showing a configuration of a conventional technique.

FIG. 6 is a flowchart showing a detailed processing procedure of the total test pattern generation means according to the present invention.

FIG. 7 is a flow chart showing a detailed processing procedure of an equivalent fault extraction means according to the present invention.

[Explanation of symbols]

 56 NOR gate 57 Net 58 AND gate 59 Inverter 70 Example of functional gate 100 Functional gate 110 Logic synthesizing means 120 Basic logic gate network 130 Equivalent extracting means 140 Equivalent fault 150 Fault defining means 160 Fault 210 100% test pattern generating means 220 100% test pattern 250 Failure Simulation Means 260 Failure Dictionary 270 Equivalent Extraction Means 300 Example of Failure Dictionary 310 Example of Equivalent Failure

Claims (2)

[Claims] 1. A step of inputting a circuit description of a logic circuit, a step of generating a 100% test pattern for the logic circuit, and a step of defining a fault in the logic circuit. From (d) a step of performing a fault simulation based on the defined faults and the exhaustive test pattern to generate a fault dictionary, and (e) a step of extracting faults having an equivalent relationship from the fault dictionary. Equivalent fault extraction method comprising. 2. A means for inputting a circuit description of a logic circuit, a means for defining a fault in the logic circuit, a means for generating a 100% test pattern of the logic circuit, a logic circuit, a 100% test pattern and a fault. An equivalent fault extracting device comprising: means for generating a fault dictionary by inputting a fault simulation; and equivalent fault extracting means for referring to the fault dictionary and extracting an equivalence relation of the faults.