JPH0715293A - Clock disable circuit, clock disable and enable circuit and carrier-signal-frequency tracking device with synchronized clock disable and enable - Google Patents

Abstract

PURPOSE: To provide a clock disable and enable circuit having an input for receiving a clock signal and the other input for receiving a disable/enable signal. CONSTITUTION: In a disable and enable circuit 20, a clock disable/enable output is applied from a circuit synchronizing with a clock signal CLK when a disable/ enable signal D/E is not activated. When the disable/enable signal D/E is activated, the transition of a clock disable/enable signal CLKD/E to a normal state value (a high or low voltage level) is obtained after at least a half-clocking period. When the disable/enable signal D/E is inactivated again, the clock disable/enable signal CLKD/E is automatically synchronized with the clock signal CLK.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to electronic circuits, and more particularly to synchronous clock disable and enable circuits.

[0002]

Background of Related Art Clock circuits used to generate multiple pulses are well known. This pulse is generated very regularly and is often synchronized with the operation of digital circuits attached to the output of the clock circuit. As such, clock pulses are used to control the speed of operation of digital circuits that may be included on the same monolithic circuit as the clock circuits.

In order to ensure optimum performance of the digital circuit receiving the pulses, each pulse must have a constant duration, which duration must not change substantially. For example, a high level voltage pulse must remain high for a minimum duration, but not exceed the maximum duration. Similarly, low level voltage pulses must also remain low for more than the minimum duration and less than the maximum duration, respectively. If the high or low pulse is less than the acceptable duration, then a "glitch" can occur causing the connected digital circuitry to fail.

Often, it is desirable to temporarily stop the stream of clock pulses generated by a clock circuit. By deactivating the clock pulse, some attached digital circuits can be temporarily suspended. For example, the operation of a microprocessor or microcontroller may generally be suspended in such a manner. To provide temporary deactivation of clock pulses, clock disable and enable circuits are typically placed between the clock circuit and the corresponding digital circuit. The clock disable and enable circuit receives a free-running continuous period of clock pulses and also a disable signal that may exceed some clock periods. When the disable signal is activated, the clock disable and enable circuit provides the digital circuit with a steady state output indicating the suspension of the clock pulse. Transient glitches often occur at the output of conventional disable and enable circuits while the clock disable and enable circuits are receiving the disable signal, causing persistent digital circuits to malfunction. A glitch, which is defined here as a clock pulse with a duration less than the targeted pulse duration, causes a connected digital circuit to lose or err in its operating state or data (stored or modulated data). May be. Therefore, many conventional disable and enable circuits typically provide one or more glitches each time the output transitions from the clock state to the disabled or steady state. Similarly, when the disable and enable circuit reactivates the clock pulse,
One or more glitches may appear at the output during the transition from steady state to clock state.

[0005]

SUMMARY OF THE INVENTION The above problems are in large part solved by the synchronous clock disable and enable circuit of the present invention. That is, the disable and enable circuit ensures that no output glitch occurs on the output transition between the free-running clock state and the steady state. The steady state output occurs after the full duration of the high or low pulse of the clock pulse has occurred but before the next pulse. Similarly, when the disable signal is stopped, the disable and enable circuit outputs will
The transition occurs after the complete high or low pulse duration of the clock pulse occurs but before the next pulse.
When disabled, the disable and enable circuit output returns to the clock state, where the clock state is substantially equal to and synchronized with the clock pulses generated by the clock circuit.

By ensuring a glitch-free transition,
The present invention is suitable for applications that require disable and enable circuit outputs that are synchronous to the clock pulses output by the clock circuit. Such applications include, but are not limited to, demodulators and microprocessor-based timing circuits. Microprocessors designed for static operation (that is, microprocessors that can hold state when the internal clock is held in a steady state) make a smooth transition from dynamic operation to static operation and vice versa. Therefore, it can be easily incorporated into the present invention. In addition, microprocessors that require a phase locked loop (PLL) clocking mechanism and outputs will need to provide smooth dynamic to static or static to dynamic transitions. However, the PLL cannot provide such a transition when it stops and restarts in a short period of time. PLL is generally
A long start-up period is required to synchronize to the clock output or lock on. Therefore, it is possible to allow the PLL to move freely and to place the synchronized disable / enable circuit of the present invention between the PLL and the internal clock driver of the microprocessor (or digital circuit). desirable. The PLL can continue to run while the disable / enable circuit disables or enables the internal driver in synchronization with the PLL clock pulse. A considerable amount of power is consumed when the internal clock of the microprocessor runs. It is a very desirable feature of this invention to stop the internal clock and put the processor in a static state when synchronized. Temporary disabling of the processor controls power consumption resulting in lower operating temperatures and in battery operating environments, providing longer battery life during charging.

Briefly, the present invention contemplates a clock disable and enable circuit including a multi-stage latching circuit having inputs and outputs. The latching circuit can receive the disable signal at the input and delay the disable signal at the output until the latching circuit receives a particular series of clock pulses from the clock signal. The clock disable and enable circuit further includes a logic gate coupled to the output of the latching circuit. The logic gate receives the delayed disable signal during the transition of the clock signal and
A steady state output signal can be generated.

The steady state output signal can be a logic level high or a logic level low depending on the configuration of the clock disable circuit. The clock disable and enable circuit is configured to receive the opposite polarity of the clock signal and can generate either a relatively high steady state voltage or a relatively low steady state voltage at its output depending on the polarity configuration selected. For example, if the steady state output from the clock disable and enable circuit is at a relatively low voltage level, then the logic gate is preferably NAND.
Configured as a gate, the transition of the clock signal from a higher voltage level to a lower voltage level produces a low steady state output while the NAND gate receives the delayed disable signal. Conversely, by way of further example, if the steady state output is at a relatively high voltage level, the logic gate is preferably configured as a NOR gate and the NOR gate is at a relatively low voltage level while receiving the delayed disable signal. From a high to a relatively high voltage level produces a high steady state output. In the former example, the steady-state output signal is of opposite polarity to the high voltage pulse duration of one cycle of the clock signal, and begins shortly after this duration has occurred, and the other of the subsequent cycles of the clock signal. Continues until immediately after the high voltage pulse duration of has occurred. Conversely, in the latter example, the steady-state output signal is of opposite polarity to the low voltage pulse duration of one cycle of the clock signal, and begins shortly after this duration occurs and the subsequent cycle of the clock signal. Until another low voltage pulse duration of occurs shortly after.

The present invention further contemplates a carrier signal frequency tracking system with synchronous clock disable and enable. The tracking system includes an oscillator and clock disable and enable circuits. The clock disable and enable circuit has one input coupled to receive the clock signal from the oscillator and another input coupled to receive the disable / enable signal. The clock disable and enable circuit further includes a multi-stage latching circuit having a latching input and a latching output. The latching circuit can receive the disable / enable signal at the latching input and delay the disable / enable signal at the latching output until the latching circuit receives the clock signal. The clock disable and enable circuit includes a logic gate having two logic inputs and one logic output.
One logic input is coupled to receive the delayed disable / enable signal and the other logic input is coupled to receive the clock signal. The logic output is synchronous with the clock signal and produces a logic output signal substantially equal thereto. The logic output signal goes high or low from the clock state (synchronized with the input clock signal) while one input receives the clock signal transition and the other input receives the delayed disable / enable signal. Transition to steady state voltage. The logic output signal then transitions from the steady state to the clock state again, synchronizing to the clock signal when one input stops receiving the clock signal transition and the other input stops receiving the delayed disable / enable signal. And is substantially equal to it.

Further included is a frequency transition detection circuit having two detection inputs and one detection output. The voltage amplitude of the detection output changes due to the difference in frequency between the carrier signal applied to one detection input and the logic output signal applied to the other detection input. Therefore, the oscillator can be voltage controlled and the frequency transition detector is
It is placed in the feedback loop of the voltage controlled oscillator, forming a demodulator or phase locked loop.

[0011]

DETAILED DESCRIPTION OF THE INVENTION Other objects and advantages of the present invention will become apparent through the following detailed description and with reference to the accompanying drawings.

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and will be described in detail herein. However, the drawings and description are not intended to limit the invention to the particular forms disclosed, but the intention is to contemplate that the invention includes all modifications, equivalents, and alternatives. Within the spirit and scope of the invention as defined by.

FIG. 1 illustrates a typical carrier signal frequency tracking system 10 of the present invention. The tracking system 10 has a terminal 1 capable of receiving an input signal.
Including 2. The input signal can be sent or modulated on a carrier signal, where the carrier signal is fixed at the carrier frequency. In order to demodulate the input signal from the carrier signal, it is important that the system 10 follow the carrier frequency in synchronization.

Tracking techniques often make use of phase-locked loops (PLLs) known in the art. Phase lock occurs by using the phase detector 14 to receive the modulated input signal. The feedback information from the phase locked loop is generated by the phase detector 14 so that the phase detector 14 acts as a mixer. The low pass filter 16 substantially transfers the DC voltage to its output. Carrier signal frequency and oscillator 18
The change in DC offset voltage occurs at the output of low pulse filter 16 due to the difference between Oscillator 18
Is a voltage controlled oscillator, and DC from the filter 16
A variable frequency PLL output clock signal (CLK signal) that depends on the offset voltage output is generated. Therefore,
The oscillator 18 transmits the CLK signal to the phase detector 14.
If the frequency of the clock signal matches the carrier frequency at terminal 12, then phase detector 14 produces little or no DC offset. With a minimal amount of offset, the oscillator 18 will not change the frequency output. Therefore, the output of the oscillator 18 or the clock signal is said to be locked in frequency and in phase with the carrier frequency. If there is any change in carrier frequency, there will be an offset and a corresponding change in the clock signal (or CLK signal).

In many cases, the clock signal needs to be temporarily deactivated or the tracking system 10 needs to be temporarily stopped. In such cases, the disable and enable circuit 20 may be incorporated between the oscillator 18 and the internal clock driver 21. Clock driver 21 provides the output levels required to drive the attached digital circuitry or processor. When receiving the disable / enable signal (D / E signal),
Circuit 20 will force the clock signal to either a steady state high voltage or a low voltage depending on the configuration of circuit 20. A particular advantage of circuit 20 described below is that it is possible to disable the clock signal on a clock signal transition and then reactivate the clock signal on a clock signal transition. Disable and enable occur with the clock disable / enable signal (CLKD / E signals) without any glitches. The clock disable / enable signal sent from the circuit 20 to the internal clock driver 21 is therefore synchronous with the input clock signal. The change between clock state and steady state occurs synchronously with the input clock signal so that system 10 remains synchronized with the clock signal even after a suspend operation. Continuous synchronization is required to achieve optimal operation of system 10. PL
L can move freely even when the output of the disable / enable circuit 20 is stopped. However, it should be noted that the PLL does not always have to be used with the disable / enable circuit 20. In such a case circuit 20 may be used to provide the disable and enable outputs to the asynchronous clock.

Referring to FIG. 2, a schematic diagram of one embodiment of the clock disable and enable circuit 20 is shown. The circuit 20 includes a multistage latching circuit 22. Each stage of the latching circuit 22 has an inverter 2 anti-coupled with a transmission gate or a pass gate 24.
6 and 28 (shown in the latching configuration) and another inverter / buffer 30. The latching circuit 22 of FIG. 2 shows three stages of latching. Circuit 22
At least 3 to provide a delay for the disable / enable signal for the glitchless transition of the output of
Steps are needed. The use of three stages ensures that the delayed disable / enable signal (D.D / E signal) toggles at least half a clock cycle after the disable / enable signal (D / E signal) transitions. . By delaying the disable / enable signal by at least a half cycle, the delayed disable / enable signal toggles only after all changes to the disable / enable signal have been released. The delayed disable / enable signal is also synchronized with the falling edge of the input CLK (shown in the embodiment of FIG. 2) or the rising edge of the input CLK (shown in the embodiment of FIG. 3). Sync with.

The clock signal (CLK signal) activates the first and third stages of circuit 22 during a relatively low clock cycle / pulse. Similarly, the clock signal activates the second stage of circuit 22 during a high clock cycle / pulse. The disable / enable signal is transmitted to the output of the circuit 22 via the clock signal by the selective conduction circuit formed by the modulation transmission gate 24. The transmitted disable / enable signal is delayed by at least a half clock cycle and provided as a delayed disable / enable signal (DD / E signal).

Logic gate 32 receives the delayed disable / enable signal and combines it into a clock signal. In the embodiment shown in FIG. 2, the disable / enable signal and the clock signal together are N
ANDed and, after inversion, form the clock disable / enable signal (CLKD / E signal) as shown. When the delay disable / enable signal is not activated, the clock disable / enable signal is synchronized with the clock signal in the clock state.
The clock disable / enable signal assumes a steady state value when the delayed disable / enable signal is active.

An important advantage of the present invention is that not only is it possible to synchronize the clock disable / enable signal to the clock signal, but the disable / enable signal is
It can be delayed until after all transients associated with the signal have passed. In addition, the change in clock disable / enable signal state between steady state and synchronized clock occurs without any glitches, and the resulting clock state is delayed disable / enable activation. When not present, it always remains in sync with the same polarity as the clock signal.

The embodiment shown in FIG. 2 is an example of circuit 20, which is connected so that the delayed disable transitions from a high to a low state coincident with the clock signal, resulting in The resulting clock disable / enable signal will then be deactivated to a low voltage state. Conversely, the clock disable / enable signal will follow the clock signal while the delayed disable / enable signal transitions from the low to high state. The following Table 1 illustrates the operation of the circuit 20 shown in FIG. 2, in which the delayed disable / enable signal represents a similar delayed signal to the disable / enable signal.

[0021]

[Table 1]

With reference to FIG. 3, an alternative embodiment of the disable and enable circuit 20 is shown. In particular, circuit 20 can be configured to have a multi-stage latching circuit similar to that shown in FIG. But,
Instead of logic gate 32 being a NAND gate in FIG. 2, logic gate 32 can be a NOR gate in FIG.
The delayed disable / enable signal is NORed with the clock signal and, after inversion, produces the clock disable / enable signal as shown.
If it is desired that the clock disable / enable signal be deactivated at a steady state high voltage level, it is preferable to use a NOR gate instead of a NAND gate. Thus, either embodiment shown in FIGS. 2 and 3 may be used depending on the design requirements of the steady state output of the clock disable / enable signal. The embodiment of FIG. 2 produces a low voltage steady state deactivated output, and the embodiment of FIG. 3 produces a high voltage steady state deactivated output. One of two embodiments is selected depending on the desired disable / enable signal value. If clocking in the low transition state is desired, the embodiment shown in FIG. 2 is preferred. Conversely, if a high state clock disable is desired, the embodiment shown in FIG. 3 is preferred. Table 2 below shows the operation of the circuit 20 shown in FIG. 3, in which the delayed disable / enable signal represents a delayed polarity signal similar to the disabled / enable signal.

[0023]

[Table 2]

Details regarding the disable and enable circuit 20 for both embodiments are shown in FIGS.
Is shown in. Specifically, FIG. 4 shows a timing diagram of various signals generated in accordance with the embodiment of FIG. Figure 5
Shows various signals generated according to the embodiment of FIG.

Referring to FIG. 4, the disable / enable signal is within the clock signal period (ie, T1 and T1).
It is possible to toggle from a high voltage state to a low voltage state at any time (in 2 hours). Delayed disable / enable signals always disable / enable
It will be delayed by at least a half clock cycle from the enable signal transition (ie delayed until time T3). The disable / enable signal is T early,
Or the delayed disable / enable signal will always transition at least half a clock cycle thereafter, up to 1.5 clock cycles, regardless of whether it transitions late at T2 or at any time in between. By delaying the disable / enable signal by at least half a clock cycle, the clock disable / enable
The enable signal will transition to its steady state or deactivated value synchronously with the clock signal. Specifically, the clock disable / enable signal corresponds to the high-to-low transition of the clock signal, and coincides with the delayed disable / enable signal's high-to-low transition, resulting in a high voltage at time T3. The state will transition to the low voltage state. The operation of the circuit of FIG. 2, shown in FIG. 4, also provides a sync enable. At any time from T4 to T5, the disable / enable signal can transition back to the high state, causing the delayed disable / enable signal to transition for at least its second half clock cycle. When the delayed disable / enable signal transitions coincident with the clock signal transition (ie, during time T6), the clock disable / enable signal goes into the clock state again, but at the low pulse level but at the clock signal. Be synchronized. Thus, at the beginning of time T6, the clock disable / enable signal is substantially equal to the clock signal.

With reference to FIG. 5, the operating states of the various signals in the embodiment of FIG. 3 are shown. Specifically, the disable / enable signal may toggle low at one time between T1 and T2, and then toggle high at a time between T4 and T5. The delayed disable / enable signal should be at least 1.5 clock cycles after the disable / enable signal was activated.
Only one clock cycle later, it is activated at time T3.
Once activated, the delayed disable / enable signal transitions coincident with the clock transition, causing the clock disable / enable signal to transition to time T3.
Transitions to the steady state high value with. When the delayed disable / enable signal is no longer activated at time T6, the clock disable / enable signal initially returns to the high clock state.

Those skilled in the art having the benefit of this disclosure will appreciate that the present invention has application in various types of synchronized digital and analog circuits. This disable and enable circuit provides and maintains clock synchronization to the connected digital and / or analog circuits through the disable and re-enable cycles. It is also understood that the form of the described invention is to be taken as the presently preferred embodiment. Various modifications and variations may be made without departing from the spirit and scope of the invention as set forth in the claims. One modification would be to use more than three latching stages. In addition, other types of logic functions of logic gate 32 may be included in addition to NAND gates, NOR gates, or combinations thereof. Multiple latching stages or logic gates if the clock disable / enable signal transitions to the clock circuit during the non-disable period and transitions to the steady state during the disable period in synchronization with the clock signal transition. Any modification to can be made and is still within the spirit and scope of the invention. The claims below are intended to be construed to include all such modifications and variations.

[Brief description of drawings]

FIG. 1 is a block diagram of an exemplary carrier signal frequency tracking system in accordance with the present invention.

FIG. 2 is a schematic diagram of one embodiment of a clock disable and enable circuit according to the present invention.

FIG. 3 is a schematic diagram of another embodiment of clock disable and enable in accordance with the present invention.

4 is a timing diagram of various signals received and generated by the clock disables and enables shown in FIG.

5 is a timing diagram of various signals received and generated by the clock disable and clock enable circuits shown in FIG.

[Explanation of symbols]

20 clock disable and enable circuit 22 multistage latching circuit 32 logic gate D / E Delayed disable / enable signal CLKD / E Clock disable / enable signal

Claims (20)

[Claims] 1. A multi-stage latching circuit having an input and an output, said latching circuit being capable of receiving a disable signal at said input, said output having said disable until said latching circuit receives a clock signal. It is possible to delay the enable signal,
Further included is a logic gate coupled to the output of the latching circuit, the logic gate being capable of producing a steady state output signal during the transition of the clock signal and in receiving the delayed disable signal. , Clock disable circuit. 2. The clock of claim 1, wherein the latching circuit includes at least three latching stages connected in series, each latching stage including a selective conduction path serially connected to the latch. circuit. 3. The clock circuit of claim 2, wherein the conductive path is modulated upon receiving the clock signal. 4. The clock circuit of claim 1, wherein the logic gate comprises a NAND gate and the transition of the clock signal is from a relatively high voltage level to a relatively low voltage level. 5. The logic gate includes a NOR gate,
The clock circuit of claim 1, wherein the transition of the clock signal is from a relatively low voltage level to a relatively high voltage level. 6. The clock circuit of claim 1, wherein the steady state output signal lasts for a duration approximately equal to a plurality of half cycles of the clock signal. 7. The steady state output signal transitions low immediately after the high to low voltage transition of one cycle of the clock signal occurs, and the steady state output signal is different from the clock signal. 2. The clock circuit of claim 1 lasting shortly after the low-to-high voltage transition of one cycle of. 8. The steady state output signal transitions high immediately after a low to high voltage transition of one cycle of the clock signal and the steady state output signal transitions to another cycle of the clock signal. 6. The clock circuit of claim 1, which lasts until shortly after the high-to-low voltage transition of. 9. A multi-stage latching circuit having a latching input and a latching output, said latching circuit being capable of receiving a disable signal at said input, and at said output until said latching circuit receives a clock signal. It is possible to delay the disable signal and further comprises two logic inputs and one logic output, one logic input coupled to receive the delayed disable signal and the other logic input. Coupled to receive the clock signal, the logic output being synchronized to the clock signal to produce a logic output signal substantially equal thereto, the logic output signal being the other when one input receives a transition of the clock signal. Steady at the same time as when the input of the DUT receives the delayed disable / enable signal Transitioning to a state voltage and the logic output is further removed from the steady state voltage at the same time as one input undergoes a clock signal transition and the other input ceases receiving the delayed disable signal. A clock disable and enable circuit that transitions and becomes approximately equal to it in synchronization with the clock signal. 10. The clock circuit of claim 9, wherein the latching circuit includes at least three latching stages connected in series, each latching stage including a selective conduction path connected in series with the latch. . 11. The clock circuit of claim 10, wherein the selective conduction path is modulated upon receiving the clock signal. 12. The clock circuit of claim 9, wherein the logic gate comprises a NAND gate and the transition of the clock signal is from a relatively high voltage level to a relatively low voltage level. 13. The clock circuit of claim 9, wherein the logic gate comprises a NOR gate and the transition of the clock signal is from a relatively low voltage level to a relatively high voltage level. 14. The clock circuit of claim 9, wherein the steady state output signal lasts for a duration approximately equal to a plurality of half cycles of the clock signal. 15. The clock circuit of claim 9, wherein the steady-state output signal occurs after a complete low-to-high voltage transition of one cycle of the clock signal. 16. The clock circuit of claim 9, wherein the steady state output signal begins after a complete high to low voltage transition of one cycle of the clock signal has occurred. 17. A carrier frequency tracking device with synchronized clock disable and clock enable comprising: (1) an oscillator; and (2) a clock disable and enable circuit having two inputs and one output. And one input is coupled to receive a clock signal from the oscillator, the other input is coupled to receive a disable / enable signal, and the clock disable and enable circuit further comprises: 1) latching input and latching A multistage latching circuit having an output, the latching circuit being capable of receiving the disable / enable signal at the input, the latching circuit delaying the disable / enable signal at the output until receiving the clock signal. 2) includes a logic gate having two logic inputs and one logic output, one logic input being coupled to receive the delayed disable / enable and the other logic An input is coupled to receive the clock signal, the logic output produces a logic output signal synchronous with and approximately equal to the clock signal, the logic output signal having one input of a steady state voltage of the logic output signal. The logic output signal transitions to a steady state voltage when it receives a state of the clock signal that is equal to the desired state, and the logic output signal transitions to a steady state voltage when the other input receives a delayed disable / enable signal. And the logic output signal further receives a clock signal in a steady state where one input equals the desired state of the logic output signal. Synchronized to the clock signal in synchronism with the transition from the steady state voltage to become and approximately equal to the clock signal and when the other input ceases to receive the delayed disable / enable signal. The carrier frequency tracking device further includes (3) a frequency shift detection circuit having two detection inputs and one detection output, the detection output being a carrier signal placed on one detection input and the other detection input. A device in which the voltage amplitude changes due to a difference in frequency between the placed logical output signal. 18. The oscillator of claim 17, wherein the oscillator includes an oscillating input for receiving a plurality of voltage levels and an oscillating output for carrying the clock signals of a plurality of frequencies according to their respective voltage levels. Frequency tracking device. 19. The frequency tracking device of claim 17, wherein the oscillator is a voltage controlled oscillator and the frequency shift detector comprises a phase detector. 20. The frequency tracking device of claim 19, wherein the voltage controlled oscillator and the phase detector are feedback coupled.