JPH11163722A - Pll frequency synthesizer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a PLL frequency synthesizer, with low power consumption and a short lockup time that receives an optional inter-station frequency. SOLUTION: This synthesizer that outputs signal which is phase-locked to a reference signal is provided with a frequency divider 10a that frequency-divides an output signal of a voltage controlled oscillator 11 at a frequency division ratio N second or N+ 1/2 to produce a feedback signal, a first phase comparator 3 that compares a phase of the feedback signal with a phase of the reference signal in a first timing and outputs a first error signal, a second phase comparator 5 that compares the phase of the feedback signal with the phase of the reference signal in a second timing and outputs a second error signal, and the voltage controlled oscillator 11 that outputs signals in response to the first error signal and the second error signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a PLL frequency synthesizer.

[0002]

2. Description of the Related Art Conventional P used for radio receivers and the like
An LL frequency synthesizer includes a reference oscillator that generates a reference signal, a programmable frequency divider that divides an output signal to generate a feedback signal, and compares an error by comparing the phase and frequency of the feedback signal with the phase and frequency of the reference signal. A phase comparator for generating a signal; a low-pass filter for generating a control voltage in response to the error signal; and a voltage-controlled oscillator for generating an output signal in response to the control voltage. Such a PLL frequency synthesizer is known as “SANYO TECHNICA”.
L REVIEW ”, VOL. 10, NO. 1, FE
B. This is disclosed in FIG. 1 on page 32 of 1978.

[0003]

It is desirable that the lock-up time of the above-mentioned PLL frequency synthesizer be short, but the relationship between the reference frequency of the reference signal and the lock-up time is theoretically and unitarily determined if it is designed optimally. It will be done. As a method of shortening the lock-up time, there is a method of switching a time constant of a low-pass filter.

In the above-mentioned system, the reference frequency can be set higher than the inter-station frequency. However, since a phase error always occurs, a compensation output for the phase error is required. There is a first disadvantage that adjustment is required.

[0005] In the manner described above, the oscillation frequency of the output signal to be oscillated by an integer multiple of the reference frequency, for example, by setting the reference frequency in 100KH _Z at the receiver, the frequency between the stations not receiving stations 50KH _Z There is a second disadvantage.

Further, the above-described logic circuit portion of the synthesizer is mainly composed of CMOS, but there is a third disadvantage that power consumption is large because the internal load capacitance of CMOS is large.

Therefore, the present invention provides a PLL frequency synthesizer which has a short lock-up time, can receive an arbitrary inter-station frequency, and consumes less power, in consideration of such a conventional drawback.

[0008]

In order to solve the above-mentioned problems, according to the first aspect of the present invention, in generating an output signal phase-synchronized with a reference signal, the output signal is divided by a dividing ratio N.
A frequency divider that divides the frequency of the feedback signal by N + を to generate a feedback signal; and a first phase comparator that compares the phase of the feedback signal with the phase of the reference signal at a first timing to generate a first error signal. A second phase comparator that compares the phase of the feedback signal with the phase of the reference signal at a second timing to generate a second error signal, and generates an output signal in response to the first and second error signals. And a voltage-controlled oscillator.

According to the second aspect of the present invention, the first switch for passing or stopping the feedback signal from the frequency divider to the first phase comparator, and the passing or stopping of the feedback signal from the frequency divider to the second phase comparator. And a second switch configured to open the first switch and the second switch in response to the first timing and the second timing, respectively.

According to the third aspect of the present invention, the frequency divider comprises a variable frequency divider and a fixed frequency divider.

According to a fourth aspect of the present invention, there is provided a frequency divider for generating an output signal which is phase-synchronized with a reference signal, wherein the frequency divider divides the output signal to generate a feedback signal; A phase comparator that compares the phases of the signals and outputs a pump-up signal or a pump-down signal; and a voltage-controlled oscillator that generates an output signal corresponding to the signal. The frequency divider includes a variable frequency divider and a fixed frequency divider. It is composed of one connected with a frequency divider.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS P according to a first embodiment of the present invention
The LL frequency synthesizer will be described with reference to the block diagram of FIG. In the present PLL frequency synthesizer 1 shown in FIG. 1, a reference oscillator 2 generates a reference signal FR.

The reference signal FR is supplied to the first phase comparator 3 as the first reference signal fr1 without delay. The delay circuit 4 delays the reference signal FR by a 1/4 cycle, and supplies it to the second phase comparator 5 as a second reference signal fr2. The delay circuit 6 delays the reference signal FR by a half cycle, and supplies it to the third phase comparator 7 as a third reference signal fr3. The delay circuit 8 converts the reference signal FR to 3/4.
The signal is delayed by the period and given to the fourth phase comparator 9 as the fourth reference signal fr4.

Variable frequency divider (programmable frequency divider) 10
Fixes the output signal f ₀ from the voltage controlled oscillator 11 (1
/ 2) frequency-divided via the frequency divider 12 and the feedback signal fv1,
Generate fv2, fv3, fv4. Thus, the frequency divider 10a is constituted by the variable frequency divider 10 and the fixed frequency divider 12.

The first phase comparator 3 converts the phase and frequency of the feedback signal fv1 from the frequency divider 10a into a first reference signal fr.
1 to generate a first error signal ER1. The second phase comparator 5 compares the phase and frequency of the feedback signal fv2 with the phase and frequency of the second reference signal fr2, and generates a second error signal ER2. The third phase comparator 7 compares the phase and frequency of the feedback signal fv3 with the phase and frequency of the third reference signal fr3, and generates a third error signal ER3. The fourth phase comparator 9 compares the phase and frequency of the feedback signal fv4 with the phase and frequency of the fourth reference signal fr4, and generates a fourth error signal ER4.

A low-pass filter (LPF) 13 outputs the error signals ER1, ER2, ER2 from the phase comparators 3, 5, 7, 9.
A control voltage CN is generated in response to ER3 and ER4. Voltage controlled oscillator 11 generates output signal f ₀ in response to control voltage CN from low pass filter 13.

The CPU (Central Processing Unit, not shown) includes delay circuits 4, 6, 8, a first switch (gate circuit) 14, a second switch (gate circuit) 15, and a third switch. (Gate circuit) 16 and Fourth switch (Gate circuit) 17
Control.

The switches 14 to 17 synchronize the start of frequency division of the frequency divider 10a with the output signal f ₀ from the voltage controlled oscillator 11, and operate only for the first cycle of the reference signal FR. . More specifically, the second switch 15 opens later than the first switch 14 by １ ／ cycle. The third switch 16 is opened with a delay of 周期 cycle of the second switch 15. The fourth switch 17 is opened with a delay of 周期 cycle with respect to the third switch 16. The switches 14 to 17 are continuously open after two cycles.

Next, the operation of the PLL frequency synthesizer will be described with reference to the timing charts of FIGS. The reference oscillator 2 has a reference frequency fr (period Tref =
1 / fr) of the reference signal FR. Reference signal FR
Is the first reference signal fr1 shown in FIG.
To the first phase comparator 3. The reference signal FR is also delayed by a 1/4 cycle (Tref / 4) by the delay circuit 4, and the second reference signal fr2 shown in FIG.
To the second phase comparator 5. The reference signal FR is also halved by the delay circuit 6 (Tref / 2).
And is provided to the third phase comparator 7 as the reference signal fr3 shown in FIG. The reference signal FR is also subjected to 3/4 period (3Tref / 4) by the delay circuit 8.
The fourth reference signal fr shown in FIG.
4 is provided to the fourth phase comparator 9. The frequencies of the reference signals fr1 to fr4 supplied to the phase comparators 3, 5, 7, and 9 are the same, but their phases are shifted by π / 2.

On the other hand, the output signal f ₀ from the voltage controlled oscillator 11 is frequency-divided by the fixed frequency divider 12 and the variable frequency divider 10 and supplied to the first phase comparator 3 as a feedback signal fv1. The output signal f ₀ is also frequency-divided by the fixed frequency divider 12 and the variable frequency divider 10 and provided to the second phase comparator 5 as a feedback signal fv2. The output signal f ₀ is also frequency-divided by the fixed frequency divider 12 and the variable frequency divider 10, and the feedback signal f 0
This is given to the third phase comparator 7 as v3. Output signal f
_{Further, 0} is frequency-divided by the fixed frequency divider 12 and the variable frequency divider 10 and supplied to the fourth phase comparator 9 as a feedback signal fv4. Wherein the frequency of the output signal f ₀ and the frequency division ratio of the frequency divider 10a and N is expressed by the following equation.

F ₀ = N · fr or f ₀ = (N + ／) · fr The phase and frequency of the feedback signal fv 1 are determined by the first phase comparator 3.
Is compared with the phase and frequency of the first reference signal fr1. As a result, the first error signal ER1 is
Given to. The phase and frequency of the feedback signal fv2 are compared with the phase and frequency of the second reference signal fr2 by the second phase comparator 5, and as a result, the second error signal ER
2 is provided to the LPF 13. The phase and frequency of the feedback signal fv3 are determined by the third phase comparator 7 as the third reference signal fv3.
This is compared with the phase and frequency of r3, and as a result, the third error signal ER3 is provided to the LPF 13. The phase and frequency of the feedback signal fv4 are compared with the phase and frequency of the fourth reference signal fr4 by the fourth phase comparator 9, and as a result, the fourth error signal ER4 is provided to the LPF 13. Therefore, the phase comparators 3, 5, 7, and 9 as a whole perform the phase comparison four times during one cycle of the reference signal RF (the first timing T1, the second timing T2, the third timing T3, and the fourth timing). Timing T4).

The error signals ER1 to ER4 are converted into a control voltage CN by the LPF 13. Voltage controlled oscillator 11
Is an output signal f having a frequency proportional to the control voltage CN.
Generates ₀ .

As described above, the first switch 14 is opened only between the first timing T1 and the second timing T2, and at the first timing T1, the first phase comparator 3 outputs the first reference signal f.
The phase and frequency of r1 and the feedback signal fv1 are compared. The second switch 15 opens only between the second timing T2 and the third timing T3. At the second timing T2, the second phase comparator 5 determines the phase and the phase of the first reference signal fr2 and the feedback signal fv2. Compare frequencies. The third switch 16 and the fourth switch 17 perform the same operation.

The error signals ER1 to ER4 are converted into a control voltage CN by the LPF 13. Voltage controlled oscillation circuit 11
Is an output signal f ₀ having a frequency proportional to the control voltage CN.
Occurs. As a result, the output signal f ₀ becomes the reference signal FR.
Are synchronized with each other.

In the PLL frequency synthesizer 1, the reference signal FR is shifted by π / 2,
Since the phase comparison is performed four times during one period, the lock-up time is reduced. For example the frequency fr of the reference signal FR and 1 kH _Z, the division ratio N of the frequency divider 10a 10
When 00 is set, 100 which is phase-synchronized with the reference signal FR
The output signal f ₀ of 0KH _Z is outputted. 1000KH _Z of the output signal f ₀ is a frequency divider in the state of being stably output 1
When the dividing ratio N of 0a is changed from 1000 to 2000,
The output signal f ₀ is changed toward the 1000KH _Z to 2000KH _Z, since the phase comparison is performed 4 times during one cycle of the reference signal FR, a frequency FR is the speed of conventional 4 times the output signal f ₀ in converges to 2000KH _Z. This reference signal FR 4KH _Z frequency apparently four times the
It means that it became. As described above, according to the PLL frequency synthesizer 1, since the phase comparison is performed four times during one cycle of the reference signal FR, the lock-up time is reduced to one-fourth of the conventional one.

In the above-described embodiment, the phase comparison is performed when the reference signal rises. However, the phase comparison may be performed when the reference signal falls. Therefore, a normal phase comparator that performs a phase comparison when the reference signal rises and an opposite phase comparator that performs a phase comparison when the reference signal falls may be provided. In short, one of the reference signals
The phase comparison may be performed a plurality of times during the cycle.

Next, the variable frequency divider 10 used in the PLL frequency synthesizer 1 will be described with reference to the block diagram of FIG.
explain.

To the variable frequency divider 10, a signal D0 for specifying whether or not to perform 1/2 frequency division, signals D1 to D4 for specifying a frequency division ratio N ', and a fixed frequency division from the voltage controlled oscillator 11 are provided. Table 12
The signal A1 (f ₀ ) passed through is input. D0 to D4 are Low (“0”) or High (“1”) signals,
A1 is a pulse signal in which Low / High times are equal to each other.

Reference numeral 18 denotes an adder, which outputs the frequency dividing ratio N 'of the signals D1 to D4 input to the terminal B to the programmable frequency dividing device 19 as it is when a signal A4 described later input to the terminal A is low. , When A4 is High (1)
A signal of the frequency dividing ratio N ′ + 1 obtained by adding one to the frequency dividing ratio of 1 to D4 is output to the programmable frequency dividing device 19.

The programmable frequency dividing device 19 has A1 (f
o) as a clock pulse, count down with the frequency division ratio (N ′ or N ′ + 1) from the adder 18, and
A down count is preset by the High of a signal A5 described later applied to AD. 20 is a coincidence circuit,
When the output of the programmable frequency divider 19 becomes "2", a detection signal A2 which becomes High is output.

Reference numeral 21 denotes a D flip-flop, A2
Is a clock pulse, and the inverted output A4 of the self 21 is fed back as an input signal. When the signal D0 input to the terminal PRE is low, a signal A3 that repeats ON / OFF in synchronization with the rise of A2 is output from the terminal Q, and a signal A4 obtained by inverting A3 is output from the terminal inversion Q. When the signal D0 is High, A3 becomes High and A4 becomes Low.

Reference numeral 22 denotes a D flip-flop, A1
Is used as a clock pulse and the output A2 of the matching circuit 20 is set to A1
Is output from the terminal Q. 2
An inverter 3 outputs a signal A6 obtained by inverting A1. Here, A1 is a clock pulse whose ON / OFF time is equal to each other.
/ 2 frequency-shift. Reference numeral 24 denotes a D-flip-flop, which outputs from the terminal Q a signal A7 obtained by delaying A5 by 1/2 of A1 because A6, which is shifted by 1/2 the frequency of A1, is used as a clock pulse. I do.

Reference numeral 25 denotes a NAND gate, which includes A3 and A5.
And outputs a signal A8, which is the NAND of. 26 is NAN
A signal A which is a D-gate and is a NAND of A4 and A7
9 is output. 27 is a NAND gate, A8 and A
The signal A10 (fv), which is the logical product of N.9, is output.
Since A8 and A9 are in an inverse relationship to each other, in this case, A10 is a signal that alternately outputs A5 and A7 in synchronization with A3 and A4. That is, three NAND gates 2
The selection circuit 28 composed of 5, 26 and 27 alternately outputs two signals A by dividing the output of the D-flip-flop 21.
5 and A7 are switched and output.

The operation of the variable frequency divider having the above configuration will be described. The variable frequency divider performs N + ／ frequency division when D0 is Low (“0”), and D0 is High (“1”).
In this case, frequency division by N is performed. First, the operation of N + ／ frequency division (5.5 frequency division in this case) will be described.

D0-D4 are "0", "1",
“0”, “1”, and “0” are input. At this time D0 is "0" So, the output signal f ₀ is then passed through the fixed frequency divider 12 is input to the variable frequency divider 10. In this state, the local oscillation frequency A1 (f ₀ ) is
9, when A4 is Low, the programmable frequency divider 19 counts down from 5, and A4 becomes High.
If so, count down from 6. Here, A4 is set to Low and “2” is detected when “2” is detected by the matching circuit 20.
Outputs a high detection signal A2.

Outputs A3 and A of D-flip-flop 21
In No. 4, since D0 is Low, Low / High is repeated in synchronization with the rise of A2. The output A5 of the D-flip-flop 22 is delayed by one division from A2. A5 Hi
gh presets the programmable frequency divider 19. The output A7 of the D-flip-flop 24 is delayed by 1/2 the frequency of A5 due to the output A6 of the inverter 23.

The output A8 of the NAND gate 25 is A3 and A
This is the NAND of 5, which extracts the high of A5 on the divide-by-5 side. The output A9 of the NAND gate 26 is the NAND of A4 and A7, and extracts the High of A7 on the divide-by-6 side. The output A10 (fv) of the NAND gate 27 is the NAND of A8 and A9, and combines the extraction units of A5 and A7. That is, as described above, A10 is a signal that alternately outputs A5 and A7 in synchronization with the D flip-flop 21.

Since A4 is input to the terminal A of the adder 18, when A4 is Low and A5 is High, the programmable frequency divider 19 is preset to 5, and when A4 is High, A5 is High. , The programmable frequency divider 19 is preset to 6. Therefore, the count of the programmable frequency divider 19 is 5,
5,4,3,2,6,6,5,4,3,2 are repeated.

In this way, when D0 is "0", when the programmable frequency divider 19 counts down to 2, the preset is switched from 5 to 6 or from 6 to 5. When the preset is 5 (divided by 5), the High of the two detection signals A5 synchronized with A1 is extracted, and when the preset is 6 (divided by 6), the High of A7 delayed by half a circle from A5 is extracted. By doing so, the frequency becomes 5.5. That is, when D0 is “0”, the oscillation frequency f ₀
Can be divided by the division ratio N + ／.

Next, the operation of dividing by N (in this case, dividing by 5) will be described. D0 to D4 are “1” (High),
“1”, “0”, “1”, “0” are input. In this state, the oscillation frequency A1 (f ₀ ) is input to the programmable frequency divider 19, and when the coincidence circuit 20 detects “2”, it outputs a detection signal A2 which becomes “High” at “2”. Since D0 is high in the D-flip-flop 21, A3 is high and A4 is low. Since A4 input to the terminal A of the adder 19 is always Low, the frequency division ratio of the programmable frequency divider 19 is always 5
It is.

The output A5 of the D flip-flop 22 is A
One minute delay from 2. High of A5 causes the programmable frequency divider 19 to be preset. The output A7 of the D-flip-flop 24 is delayed by 1/2 the frequency of A5 due to the output A6 of the inverter 23. The output A8 of the NAND gate 25 is the NAND of A3 and A5, which is the inverse of A5.

The output A9 of the NAND gate 26 is A4 and A
7 is a NAND, and becomes High. The output A10 (fv) of the NAND gate 27 is the NAND of A8 and A9, which is the same as A5.

Thus, when D0 is "1", D-
The flip-flop 21 always divides the frequency of the programmable frequency divider 19 by 5, and the selection circuit 28 always outputs A
In order to operate to select 5, A10 is divided by 5. That is, when the D0 is "1", the variable frequency divider 10 can divide the signal A1 is an oscillation frequency f ₀ by the division ratio N. In this way, the variable frequency divider 10 can divide the signal A1 by the division ratio N and / or (N +＋ １).

That is, the frequency divider 10a can switch between the N frequency division operation and the N + 1/2 frequency division operation according to the signal (D0). This switching is performed at a predetermined timing (for example, immediately after the signal of A5 or A7 becomes Low). Thus, the frequency division ratio can be changed in a 1/2 frequency division step.

[0045] For example, the AM band 522KH _Z ~16
A 29KH _Z, Using 459KH _Z as the intermediate frequency fi, a conventional variable frequency reference frequency in circumferential 9K
H _Z and the division ratio are 109, 110,... 232,
The reference frequency in this variable frequency divider device 18KH _Z, the division ratio becomes 54.5,55,56.5,57 ...... 116. Thus, the reference frequency can be increased, and the lock-up time is shortened. The feedback signal fv shown in FIG.
1, fv2, fv3, fv4 are obtained by connecting the feedback signal fv shown in FIG. 3 in parallel.

Next, the PL according to the second embodiment of the present invention will be described.
The variable frequency divider 29 used in the L frequency synthesizer will be described with reference to the block diagram of FIG. The variable frequency divider 29 is 1 /
A signal D0 designating whether or not to divide by two, signals D1 to D4 designating a frequency division ratio N, and a signal A1 (f ₀ ) passed from the voltage controlled oscillator 11 through the fixed frequency divider 12 are input. .

The variable frequency divider 29 includes a programmable frequency divider 30, a coincidence circuit 31, and a D-flip-flop 3.
2, 33, 34, 35, an inverter 36, a first selection circuit 37 and a second selection circuit 38. As described above, the frequency divider 29a including the variable frequency divider 29 and the fixed frequency divider 12
Can divide the signal f ₀ into the frequency division ratio N and / or N + ／, like the frequency divider 10a.

In the frequency divider 29a, the output of the frequency divider is 1
The output is delayed by a half cycle of the input clock using the inverter 36 for each clock. Therefore, the inverter 36
Therefore, a signal delayed by a half cycle cannot be produced accurately due to the propagation delay time, and this has a disadvantage that it appears as jitter in the output frequency of the voltage controlled oscillator 11. However, as a result of analysis by the present inventor, it was found that when the delay amount of the inverter 36 was set to 100 ns or less, almost no jitter occurred.

Next, Table 1 shows a correspondence table of set division ratios in the present PLL frequency synthesizer. In Table 1,
N is the overall frequency division ratio of the variable frequency divider 29 and the fixed (1/2) frequency divider 12, and n is the frequency division ratio of the variable frequency divider 29. Also, as shown in Table 1, by dividing n into m1 to m4, four frequency divider outputs can be obtained (m is an integer).

[0050]

[Table 1]

Next, the PL according to the third embodiment of the present invention will be described.
The L frequency synthesizer will be described with reference to the block diagram of FIG. In FIG. 5, the reference oscillator 39 is the same as the reference oscillator 2 of FIG. 1, and is connected to the phase comparator 40. The phase comparator 40 is connected to a low-pass filter 42 via a charge pump 41. The low-pass filter (same as the low-pass filter 13 in FIG. 1) 42 is connected to a voltage-controlled oscillator (same as the voltage-controlled oscillator 11 in FIG. 1) 43. The variable frequency divider 44 outputs the output signal f ₀ from the voltage control circuit 43 to the feedback signal f ₀ via the fixed frequency divider 45.
, and outputs fv to the phase comparator 40.

As described above, in generating the output signal f ₀ which is phase-locked to the reference signal 4 × fr, the frequency divider 44a
Consists that connects the variable frequency divider 44 and fixed frequency divider 45, the divider 44a is divides the output signal f _0, to generate a feedback signal fv. The phase comparator 40 compares the phase of the feedback signal fv with the phase of the reference signal 4 × fr, and outputs a pump-up signal PU or a pump-down signal PD to the charge pump 41 based on the comparison result.

The signal PU or PD is supplied to the charge pump 4
1, is output to a low-pass filter 42, is converted by the low-pass filter 41 into a control signal CN, and the voltage-controlled oscillator 43 generates an output signal having a frequency proportional to the control signal CN. Thus, the voltage controlled oscillator 4
3 is a pump-up signal PU or a pump-down signal PD
In response to, for generating an output signal f _0.

As described above, as the frequency divider 44a, a fixed (1/4 frequency divider) frequency divider 45 is provided at the preceding stage, and a variable (N frequency dividing) frequency divider 44 is provided at the subsequent stage. With this configuration, the reference frequency (fr) can be quadrupled (4 × fr). As the reference frequency increases, the number of comparison operations per unit time increases, and the gain of the phase comparator 39 can be increased.

The input signal f ₀ as the frequency divider 44a (which can be varied) necessarily increases the input frequency to the frequency divider 44a as the band used by the system increases. Here, a fixed (1/4) frequency divider 45 is inserted in the preceding stage to divide the frequency by 4, and output to the variable frequency divider 44 in the subsequent stage. The variable frequency divider 44 satisfies the loop characteristics by setting a frequency division ratio corresponding to the fixed frequency divider 45.

Further, among the frequency dividers of the frequency divider 44a, only the fixed frequency divider 45 at the preceding stage is required to operate at high speed, and the variable frequency divider 44 at the subsequent stage is required to operate at a higher speed. Low speed operation is sufficient. Therefore, only the former fixed frequency divider 45 can be operated at high speed by a high-speed device, and the latter variable frequency divider 44 can be constituted by a low-speed device, and the power consumption of the frequency divider 44a can be reduced.

[0057]

As described above, according to the first aspect of the present invention, the phase of the feedback signal and the phase of the reference signal are compared at a first timing to generate a first error signal. Change the signal. Also, the phase of the feedback signal and the phase of the reference signal are compared at a second timing to generate a second error signal, thereby changing the output signal of the voltage controlled oscillator. As described above, since the phase comparison is performed a plurality of times during one cycle of the reference signal, the lock-up time is much shorter than in the related art.

According to the present invention, the first switch and the second switch are opened in response to the first timing and the second timing, whereby the phase comparison between the first reference signal and the feedback signal is performed and The phase comparison between the two reference signals and the feedback signal is accurately performed.

According to the third aspect of the present invention, the frequency divider comprises a variable frequency divider (for example, N frequency division) and a fixed frequency divider (for example, 1/2 frequency division). As a result, the output signal is frequency-divided to the frequency division ratio N and / or N + 1/2, so that an arbitrary frequency division ratio can be created, an arbitrary inter-station frequency can be received, and the lock-up time is shortened.

According to a fourth aspect of the present invention, a frequency divider that divides an output signal to generate a feedback signal, compares the phase of the feedback signal with the phase of the reference signal, and outputs a pump-up signal or a pump-down signal. A phase comparator and a voltage controlled oscillator are provided. Then, only the fixed (for example, 1/4 frequency divider) frequency divider forming the frequency divider can be constituted by a high-speed device, and the variable frequency divider (for example, frequency division by N) can be constituted by a low-speed device having a small internal load capacity. As a result, a circuit configuration with low power consumption becomes possible.

[Brief description of the drawings]

FIG. 1 is a block diagram of a PLL frequency synthesizer according to a first embodiment of the present invention.

FIG. 2 is a timing chart of the synthesizer.

FIG. 3 is a block diagram of a variable frequency divider used in the synthesizer.

FIG. 4 is a block diagram of a variable frequency divider used in a PLL frequency synthesizer according to a second embodiment of the present invention.

FIG. 5 is a block diagram of a PLL frequency synthesizer according to a third embodiment of the present invention.

[Explanation of symbols]

 3, 5, 7, 9 phase comparator 10a frequency divider 11 voltage controlled oscillator

Claims (4)

[Claims] In generating an output signal phase-locked to a reference signal, the output signal is divided by a frequency dividing ratio N and / or N.
A frequency divider that divides the frequency by + ／ to generate a feedback signal, a first phase comparator that compares a phase of the feedback signal with a phase of the reference signal at a first timing and generates a first error signal; ,
A second phase comparator for comparing a phase of the feedback signal with a phase of the reference signal at a second timing to generate a second error signal, and a second phase comparator responsive to the first error signal and the second error signal; And a voltage controlled oscillator for generating a signal.
LL frequency synthesizer. 2. A first switch for passing or stopping the feedback signal from the frequency divider to the first phase comparator, and passing or stopping the feedback signal from the frequency divider to the second phase comparator. And a second switch for causing the first switch and the second switch to open in response to the first timing and the second timing, respectively. PLL frequency synthesizer. 3. The PLL according to claim 1, wherein said frequency divider is configured by connecting a variable frequency divider and a fixed frequency divider.
Frequency synthesizer. 4. A frequency divider for generating an output signal phase-locked to a reference signal, wherein the frequency divider divides the output signal to generate a feedback signal, a phase of the feedback signal and a phase of the reference signal. A phase comparator that outputs a pump-up signal or a pump-down signal, and a voltage-controlled oscillator that generates the output signal in response to the signal, wherein the frequency divider includes a variable frequency divider and a fixed frequency divider. A PLL frequency synthesizer characterized by being connected to a frequency synthesizer.