JPH07135497A - Frame synchronization pattern detector - Google Patents

Abstract

PURPOSE:To prevent the generation of erroneous synchronizing signal by detecting a bit deviation, in which erroneous synchronization is not detectable with all 1 and all 0 detectors, with a 4th word detector when bit deviation patterns SAV, EAV are received. CONSTITUTION:An all 1 detector 102 detects consecutive 1s in 20 bits of a 1st word. An all 0 detector 103, a DFF 108 and an AND element 110 detect a pattern of 40-bit consecutive 0 of 1+1, 1+2-th words. A 4th word detector 104 detects a 4th word being 1+3-th word. That is, the detector 104 detects it that MSB is 1, the 1st bit and the LSB are 0 and the 6th bit is 1 or 0. The timing of the signal detected by the detectors 102, 103, 104 is adjusted by DFFs 105, 107, 109, 106, 108 and only when the four signals are received in the same timing, a frame synchronizing signal is outputted from the AND element 110.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame sync pattern detecting device for outputting a frame sync signal of a digital video signal.

[0002]

2. Description of the Related Art In BTA (Broadcasting Technology Development Association), among HDTV devices, BTA is used as a standard for an interface between video devices used for studio program production and having digital video input or output.
S-002 1125/60 system HDTV video signal encoding and bit parallel interface standard (hereinafter referred to as BTAS
-002 standard. )It was determined.

In the BTA S-002 standard, in order to clarify the timing relationship between the video signal and the analog synchronizing waveform, SAV (START OF ACTIVE VIDEO) is added at the beginning of each video data block as a video timing reference code.
EAV (END OF ACTIV) at the end of each video data block
E VIDEO). In each video device, SAV and EAV are detected from the sent digital signal, and the frame synchronization timing of the video signal of the video signal is detected. 1 frame here means 1 of analog HDTV
Corresponds to a horizontal line.

FIG. 7 shows SAV, EAV and analog HDT.
The timing relationship of one horizontal line of V is shown. BTA S
Table 1 shows the video timing reference code of the -002 standard. In Table 1, T is a clock cycle of 13.468 ns.

[0005]

[Table 1]

Each timing reference code is 3 in hexadecimal notation.
It consists of 4 words of FF, 000000 and XYZ. The first 3 words are prefix information of a fixed value. The fourth word is information indicating field identification, field blanking period identification, and SAV and EAV identification.

An HDTV bit serial interface is shown in FIG. FIG. 8A shows Y, Pb / Pr system serial interface, and FIG. 8B shows R,
It is a digital interface of the G and B systems.

In both the Y, Pb / Pr system, the R, G, and B systems, the parallel interface of BTAS-002 is time-division multiplexed, additional data such as a line number is added, and the data is transmitted from the LSB.

FIG. 9 shows the structure of a conventional frame synchronization pattern detection circuit. In FIG. 9, 901 is a data input terminal, 902 is an all 1 detector that detects 20 consecutive 1s, 903 is an all 0 detector that detects 20 consecutive 0s, 904 is an H bit detector, 905,
906, 907, 908, and 909 are D-type flip-flops, 910 is an AND element, and 911 is a data output terminal.

FIG. 10 shows a frame synchronization device including a conventional frame synchronization pattern detection device. In FIG. 10, 1001 is a data input terminal, 1002 is a serial / parallel conversion circuit, 1003 is a frame synchronization pattern detection device, 1004
Is a bit shift generation circuit, 1005 is a parallel data output terminal, and 1006 is a frame synchronization signal output terminal.

In the conventional frame synchronization pattern detection circuit of FIG. 10, a serial digital signal input from the data input terminal 1001 is converted into a parallel signal in the serial / parallel conversion circuit 1002, and the converted parallel signal is Frame sync pattern detector 1003
At, the frame sync signal is detected and the frame sync signal is output.

Parallel data is output from the parallel data output terminal 1005, and a frame synchronization signal is output from the frame synchronization signal output terminal 1006. In the subsequent circuit, these signals are used to start the reproduction of the horizontal synchronization signal. Video signal processing is performed. The bit shift generation circuit 1004 detects a bit shift, and the serial / parallel conversion circuit 1002
A bit shift signal is generated to correct the bit shift.

FIG. 9 is a block diagram showing the configuration of the frame synchronization pattern detecting apparatus shown in FIG. FIG. 11 is a signal waveform diagram showing the operation of the conventional frame synchronization pattern detection device of FIG. The frame synchronization pattern detection circuit in FIG. 9 detects EAV. First, at a timing t, the all-one detector 902 detects a 20-bit consecutive 1s, and at a timing t + 1, an all-0 detector 903 detects a 20-bit consecutive 0s. The signals detected by the all 1 detector 902 and the all 0 detector 903 are like signals b and c, and when inputted to the AND element 910, they are like signals e, f and g. . Since the signal h distinguishes between EAV and SAV, it detects that the H bit is 1.

At the timing t + 3, the AND element 91
All signals input to 0 become 1 and the frame synchronization signal is output from the frame synchronization signal input terminal.

[0015]

FIG. 12 shows SAV and EAV portions of the HDTV serial digital interface. FIG. 12A shows the EAV after serial / parallel conversion when no bit shift has occurred.

Since the transmission order is from the LSB to the MSB, the transmission is in the direction of the arrow in FIG. 12 (a). For example, LS of Pb / Pr of the Vth word
When the MSB of Y is transmitted from B, the LSB of Pb / Pr of the (V + 1) th word is transmitted next.

The conventional frame synchronization detecting apparatus shown in FIG. 9 detects the portion surrounded by the solid line in FIG.
I recognize that.

FIG. 12B shows an EAV when a 1-bit shift occurs in the serial-parallel converter. As shown in the figure, since the EAV is deviated by 1 bit, normally, the pattern in the figure is not erroneously detected as the EAV. It is Pb / P of the W + 1th word
This is because the LSB of r is 1 instead of 0. However, since an error occurs in the LSB of Pb / Pr in the (W + 1) th word, the signal in FIG. 12B has a high probability of being erroneously detected as EAV. The probability is the W + 1 word,
In addition to the probability that the LSB of Pb / Pr is incorrect, the LSB of Pb / Pr of the Wth word is 1 by chance, the 6th bit of the W + 3th word is 1 by chance, and the Yth of the W + 3th word is Y.
Is the probability that the 6th bit of is 1.

The probability of occurrence of 1s and 0s in the transmitted data is 1/2, and there are X bits and F bits, H bits, V bits, P3 bits, P2 bits, P1 bits and P0 bits in FIG. If the probability of occurrence of 1 and 0 is also 1/2, the probability that three bits are accidentally 1 is 1 / each.
It becomes 2. If the probability of error is Pe,
The probability of occurrence of false synchronization is as shown in the following equation (1). P1 = (Pe) .multidot. (1-Pe) ^58.multidot. (1/2) ³ ... (1) Further, as shown in FIG. 12 (c), a pattern shifted by 1 bit is detected as false synchronization. The probability is as shown in the following equation (2). P2 = (Pe) · (1 -Pe) 59 · (1/2) 2 ··· (2) Further incorrectly 2 bit shift pattern as in FIG. 12 (d), thereby detecting a false synchronization Since the probability cannot be obtained unless an error occurs in the LSB of Pb / Pr of the Xth word and the first bit, the pattern of FIG. 12D is changed to the pattern of FIG.
The probability of being erroneously detected as the pattern is as shown in the following expression (3). P3 = (Pe) ² · (1-Pe) ⁵⁶ · (1/2) ⁴ (3) Similarly, if we examine the missynchronization probabilities of 3 bit deviation and 4 bit deviation, , (Pe) ³ , and (Pe) ⁴ are included.

BTA S-002 standard and HDTV
According to the digital interface standard, all 1 words and all 0 words are prohibited in the signal in the video section. Therefore, the video data word is mistaken,
In order to detect it as an erroneous synchronization pattern, at least one bit error must occur per word.

The pattern pattern of FIG. 12 (e) shows the case where the sync detection pattern is composed of a pattern in which the video data word is bit-shifted.

Z _{0 to} Z ₉ , A _{0 to} A ₉ , B _{0 to} B ₉ , C in the figure
_{0 ~C 9, D 0 ~D 9} , E 0 ~E 9, F 0 ~F 9, G 0 ~G 9, H
₀ to H ₉ are those respectively shown video data words.

In order to erroneously detect the portion surrounded by the solid line in FIG. 12E as a synchronization pattern, A0 to A9 must be all 1's. Further, the data words of C0 to C9, D0 to D9, E0 to E9 must be all 0s. In each of the four data words, if at least one bit error does not occur, false synchronization does not occur.
The false synchronization probability of the pattern (e) includes the term (Pe) ⁴ .

If the error rate of the transmission line is Pe = 10 ^-5 or less, the false synchronization probability becomes higher in FIG.
In the patterns of (b) and (c), SAV and EAV are patterns in which bit shift has occurred.

An error occurs in the pattern of FIG. 12 (b),
Since the pattern becomes the same as that in FIG. 12A, the frame synchronization signal is generated at the incorrect timing position from the erroneous synchronization pattern as in the section 2 in FIG. By performing video signal processing such as sync signal reproduction on the basis of an erroneous frame sync signal in a circuit in the subsequent stage, a signal with a larger error is produced.

Incidentally, in the conventional example, the frame synchronization pattern detecting device for detecting the frame synchronization pattern after conversion into the parallel signal has been described.
The frame synchronization device that detects frame synchronization also has a very high probability of false synchronization when the detected serial frame synchronization pattern section is deviated by 1 bit.

In view of the above points, an object of the present invention is to provide a frame synchronization pattern detecting device for reducing erroneous frame synchronization in a serially transmitted digital video signal receiving device.

[0028]

In order to achieve the above object, the present invention provides an all-one detector for detecting 1s in a series of 20 bits and an all-0 detector for detecting 0s in a series of 40 bits.
The MSB is 1 and the first bit and the LSB is 0, and the fourth word detector for detecting that the 6th bit is 1 or 0 is provided.

[0029]

The present invention has the above-mentioned structure, and thus SAV, EA
Even if a V bit shift pattern is input, false sync detection cannot be detected by the all 1 detector and all 0 detector. A bit shift is detected by the fourth word detector to prevent generation of a false frame sync signal. Is.

[0030]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A frame synchronization pattern detecting apparatus according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows the structure of a frame synchronization apparatus according to an embodiment of the present invention. In FIG. 1, 101 is a data input terminal, 102 is an all-1 detector for detecting 1s of 20 bits in succession, 103 is an all 0 detector for detecting 0s of 20 bits in succession, and 104 is a fourth word for detecting a fourth word. 4-word detector, 105, 106, 107, 108,
109 is a D flip-flop, 110 is an AND element,
111 is a data output terminal.

FIG. 2 is a signal waveform diagram showing the operation of the frame synchronizer of one embodiment of the present invention, and FIG. 3 is a bit shift pattern of SAV and EAV. The frame synchronization detecting device of one embodiment of the present invention detects the pattern of the portion surrounded by the solid line in FIG. Compared to the conventional frame synchronizer, the LSB, the first bit, and the MSB are detected more often for Pb / Pr and Y in the fourth word.

FIG. 3A shows a pattern in which no bit shift occurs between SAV and EAV. 1 of the 20th bit in the 1st word of FIG. 3A is the all 1 detector 102 of FIG.
Detect with. The pattern of 40-bit continuous 0s in the (l + 1) th and (l + 2) th words is detected by the all-zero detector 103, the D flip-flop 108 and the AND element 110.
The fourth word detector 104 detects the fourth word of the (l + 3) th word.

As shown in section 1 of FIG. 2, 102, 10
The signals detected by the detectors 3 and 104 are adjusted in timing by a D flip-flop, and four signals are detected.
The frame synchronization signal and the signal h are output from the AND element 110 only after the signals d, e, f, and g are input at the same timing.

FIG. 3B shows a pattern in which SAV and EAV are shifted by 1 bit. MSB of Pb / Pr in LSB of Y
Is shifting. Therefore, the m + 1st word, Pb /
At the same time that an error occurs in the LSB of Pr, an error must also occur in the Y LSB of the (m + 3) th word.

Therefore, assuming that the pattern of FIG. 3B is a synchronization pattern by mistake, the probability of erroneous detection is as shown in the following equation (4), where the error probability of 1 bit is Pe. P4 = (Pe) ² · (1-Pe) ⁶¹ · (1/2) ⁵ (4) If the probability of one bit error is Pe = 10 ⁻⁸ to 10 ⁻⁵ , the same as in the conventional example. False synchronization probability P1 = (P
Compared with e) ・ (1-Pe) ⁵⁸・ (1/2) ³ , the false synchronization probability is significantly lower.

FIG. 3C shows a pattern in which SAV and EAV are oppositely shifted by 1 bit. The probability of erroneously synchronizing the portion surrounded by the frame must be such that an error occurs in the MSB of Y in the nth word and an error occurs in the MSB of Pb / Pr in the (n + 3) th word. Therefore, the false synchronization probability is expressed by the following equation (5). P5 = (Pe) ² · (1−Pe) ⁶¹ · (1/2) ⁵ (5) Similarly, the probability that the 2-bit shift pattern in FIG. As shown in the following equation (6), P6 = (Pe) ³ · (1-Pe) ⁵⁸ · (1/2) ⁷ (6) The false synchronization probability is Pe ² or more for any pattern. And the false synchronization probability is lower than that of the conventional example.

Assume that a pattern in which the SAV and EAV patterns are shifted by 1 bit is input as shown in FIG. It is assumed that Pb / Pr of the (p + 1) th word is mistaken and the p + 1th word has a pattern of all zeros. In addition, the LSB of the p-th word Pb / Pr is 1, the 6th bit of Pb / Pr of the p + 3th word is 1, the MSB is 1, the 6th bit of Y is 1, and the MSB is 1, and they are input. The operation in this case is shown in section 2 of FIG.

In the pth word, the signal b is detected,
The signal c is detected in the (p + 1) th word and the (p + 2) th word. However, in the Y LSB of the (p + 3) th word, 1 of the MSB of Pb / Pr is shifted, so that the fourth word detector of 1-4 cannot detect the pattern. Therefore, the signal d cannot be detected, and the frame synchronization signal and the signal h are not output.

FIG. 4 shows the structure of an RGB compatible frame synchronizing apparatus according to another embodiment of the present invention. 4, 401 is a data input terminal, 402 is an all 1 detector, 403 is an all 0 detector, 404 is a fourth word detector, 405, 406, 407, 408, 409 are D flip-flops, 4010 is an AND element. , 4011 are data output terminals.

FIG. 5 is a signal waveform diagram showing the operation of the conventional frame synchronizer. FIG. 6 shows bit shift patterns of SAV and EAV of the HDTV digital serial interface GBR system.

In FIG. 4, the all-one detector 402 has three
Detect 1's of 0 bits in succession The all-zero detector 403, the D flip-flop 408, and the AND element 410 detect 0 for 60 consecutive bits. Fourth word detector 40
4 detects the fourth word of SAV and EAV. Further, the frame synchronization pattern detection apparatus of FIG.
The pattern in the portion surrounded by the solid line in the EAV pattern is detected.

FIG. 5 shows a normal SA as shown in FIG. 6 (a).
It is assumed that the V and EAV patterns have been transmitted. Figure 6
The signal b from the all-1 detector 402 becomes 1 at the timing when the q-th word of the SAV and EAV patterns of (a) is input. When the q + 1th word is input, the output of the all-zero detector 403 and the signal c become 1,
When the q + 3rd word is input, the signal d becomes 1
Becomes Flip-flops 405, 406, 407, 4
The signals whose timings have been adjusted in 08 and 409 are the signals e,
The signal f, the signal g, and the signal h become, and all the signals become 1 at the same time in the (q + 3) th word. By this,
A frame synchronization signal and a signal h are output from the AND element 410.

FIG. 6B shows a frame synchronization pattern signal when the SAV and EAV patterns are deviated by 1 bit.

Since a bit shift of 1 bit has occurred, 1 of the MSB of the R signal of the rth word is shifted to the LSB of G of the (r + 1) th word. Therefore, originally 0
1 is input in the portion where is to be input.

Further, 1 of the MSB of G in the r + 3rd word
Is input to the B LSB of the (r + 3) th word. Therefore, 1 is input to the portion where 0 is originally input.

Further, 1 of B MSB of the r + th 3rd word is inputted to R LSB. Now, a bit error has occurred and 1
Let Pe be the probability that 0 becomes 1 or 0 becomes 1, and F, V,
Assuming that the occurrence probabilities of the H, P3, P2, P1, P0 bits and the X are 1 and 2, respectively, are ½, an error occurs in the three bits, and the error is generated in FIG.
The pattern of (b) is erroneously detected as a synchronization pattern. Therefore, the pattern of FIG.
The probability of erroneous detection as a synchronization pattern is given by the following expression (7). P7 = (Pe) ³ · (1−Pe) ⁹² · (1/2) ⁷ ... (7) As in the past, the first, second, third and fourth words of SAV and EAV When only 6 bits are detected, the false synchronization probability becomes as shown in the following equation (8), and P8 = (Pe) · (1-Pe) ⁸⁸ · (1/2) ⁴ (8) ) If the bit error rate Pe is about ^10-5 or less, (Pe)
^Since the term of ³ is included, the false synchronization probability is greatly improved.

In the reverse 1-bit shift pattern of SAV and EAV shown in FIG. 6C, the S + 1th word and the LSB 0 of the G signal are input to the Sth word and the MSB of the R signal.

The S + 3rd word, 0 of B LSB is erroneously input to G MSB.

Further, the 0th of the R LSB of the S + 3rd word is input to the B MSB by mistake.

Therefore, the probability of erroneously detecting the pattern of FIG. C as an erroneous synchronization pattern is given by the following equation (9). P9 = (Pe) ³ (1-Pe) ^92. (1/2) ⁷ ... (9) First, second, third and fourth words of SAV and EAV and the sixth of the fourth word When only bits are detected, the false synchronization probability is as shown in the following equation (10). P10 = (Pe) · (1 -Pe) 89 · (1/2) 3 ··· (10) The pattern is also the bit error rate, as long as Pe10 ^-5 or less, synchronization probability erroneous is greatly improved.

[0052]

As described above, the frame synchronizer of one embodiment of the present invention is an all-one detector that detects the first word of SAV and EAV, and an all-detector that detects the second and third words. In addition to the above, a fourth word detector for detecting 0 of the MSB of the fourth word, 0 or 1 of the sixth word, 0 of the first bit, and 0 of the LSB is provided, so Also, the false synchronization probability can be reduced.

As a result, even when a data signal in which an error has occurred is received, an accurate frame synchronization signal can be generated and error-free video signal processing can be performed.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a frame synchronization pattern detection device according to an embodiment of the present invention.

FIG. 2 is a signal waveform diagram showing the operation of the frame synchronization pattern detection device of one embodiment of the present invention.

FIG. 3 is a diagram showing SAV and EAV bit shift patterns input to a frame synchronization pattern detection apparatus according to an embodiment of the present invention.

FIG. 4 is a block diagram showing the configuration of a frame synchronization pattern detection device according to another embodiment of the present invention.

FIG. 5 is a signal waveform diagram showing the operation of the frame synchronization pattern detection device of the same embodiment.

FIG. 6 is a diagram showing SAV and EAV bit shift patterns input to the frame synchronization pattern detection apparatus of the embodiment.

FIG. 7 is a timing diagram of one horizontal line of SAV, EAV and analog HDTV.

FIG. 8A is a diagram showing a Y, Pb / Pr system HDTV digital serial interface, and FIG. 8B is a diagram showing an R, G, B system HDTV digital serial interface.

FIG. 9 is a block diagram showing a configuration of a conventional frame synchronization pattern detection device.

FIG. 10 is a block diagram showing a configuration of a frame synchronization device including a conventional frame synchronization pattern detection device.

FIG. 11 is a signal waveform diagram showing the operation of the conventional frame synchronization pattern detection device.

FIG. 12 is a diagram showing a 1-bit shift pattern of SAV and EAV input to a conventional frame synchronization pattern detection device.

[Explanation of symbols]

 102 All 1 Detector 103 All 0 Detector 104 Fourth Word Detector 105 D Flip Flop 106 D Flip Flop 107 D Flip Flop 108 D Flip Flop 109 D Flip Flop 110 AND Element 402 All 1 Detector 403 All 0 Detector 404 Fourth word detector 405 D flip-flop 406 D flip-flop 407 D flip-flop 408 D flip-flop 409 D flip-flop 410 AND element

Claims (4)

[Claims] 1. A receiving unit for receiving a serially transmitted digital video signal, comprises an all 1 detector for detecting 1s of 20 bits in succession, an all 0s detector for detecting 0s of 40 bits in succession, and an MSB. 1st bit and LSB
And a fourth word detector for detecting that the sixth bit is 1 or 0. 2. The frame synchronization pattern detection device according to claim 1, wherein the received digital video signal is a BTA standard HDTV bit serial interface. 3. Digital HDT serially transmitted
In the receiving unit that receives the V signal, 1 of 30 bits consecutive
All 1 detector for detecting 0s, all 0 detector for detecting 0s of 60 consecutive bits, MSB of 1 and the first bit and L
And a fourth word detector for detecting that the SB is 0 and the 6th bit is 1 or 0. 4. The frame synchronization pattern detection device according to claim 3, wherein the received digital video signal is a BTA standard HDTV bit serial interface.