JPH07122519A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To reduce the contact resistance between an electrode part and a semiconductor layer by continuously forming one-layer metal layer and a semiconductor layer on one part of a semiconductor surface without exposing to atmosphere, causing the metal layer to react with the semiconductor, and forming the compound of the metal layer and the semiconductor. CONSTITUTION:An opening 104 is provided at SiO2 102 which is formed on the surface of a wafer 101 and Ta layer 105 and Si layer 106 are formed on it but the Ta layer 105 and Si layer 106 are formed continuously without exposing to atmosphere using a thin-film forming device for a high vacuum. Then, after an impurity ion which is of the same type as a high-density layer 103, heat treatment is performed and silicide layer 107 is formed and an ion implantation layer is recrystallized. Further, Ta layer 108 is formed on the silicide layer 107, the Ta layer 108 and the silicide layer 107 are subjected to patterning, and then an extraction electrode is formed, thus forming a metal electrode with an extremely low contact resistance.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to an ultra high density integrated circuit (ULS).
The present invention relates to a semiconductor device conforming to I) and a manufacturing method thereof.

[0002]

[Related Art] Currently, the degree of integration of ULSI continues to increase at a remarkable rate, and the element size is 0.1 μm.
Furthermore, research and development are being actively pursued with the aim of realizing devices with ultra-fine dimensions that surpass that.

Due to the high integration of elements, the wiring structure is becoming more complicated and multilayered. Along with this, the number of contact portions for connecting wires to each other and for connecting metal wires to a semiconductor has explosively increased, and further miniaturization has been promoted with respect to the size thereof. UL
High reliability and high performance of various contacts existing in SI are one of the important development items that are the key to realize high reliability and high performance of ULSI.

In order to achieve high reliability and high performance of the contact portion between metal and semiconductor, low contact resistance is essential, and in order to realize it, formation of an ultraclean contact interface is necessary. It is essential. The reason is that the presence of an insulating layer (such as an oxide film) that hinders electrical conduction at the contact interface causes an increase in contact resistance and a variation in contact resistance value.

However, an ultra-clean contact interface is obtained whether it is a contact for connecting metal wirings or a metal-semiconductor contact for forming an ohmic contact electrode of a semiconductor element. Things are very difficult. The reason is that in order to form a contact, the electrode material must be formed on a surface of a material that is very easily oxidized, such as a metal surface or a surface in which impurities are added to a semiconductor at a high concentration. This is because an oxide film is likely to remain on the formed interface. For example, if it is a metal surface, an oxide film of 2 to 5 nm is formed only by exposing it to the atmosphere for a few seconds, and if it is an n ⁺ -Si surface, it is 0.5 to 5 1 nm of SiO ₂ is formed. From this, it can be easily understood how difficult it is to stably realize a contact interface without an oxide film in forming a contact structure of a semiconductor element. Therefore, in the ULSI manufacturing technology, the establishment of a technology for forming a contact interface between a super-clean metal and a semiconductor plays a great role.

Conventionally, in forming a contact, a heat treatment after forming a contact electrode material has been carried out as a solution to the above-mentioned contamination existing on the interface, particularly the growth of an oxide film. In forming a bond between metal and silicon,
A technique has been developed in which a silicide of a refractory metal is formed to reduce contact resistance. After forming a refractory metal thin film on silicon, heat treatment is performed to form a silicide compound, and the interface between the silicide and silicon is brought to a position deeper than the position of the interface immediately after contact formation, whereby clean silicide and Si are formed. It becomes possible to obtain the interface with. Furthermore, a silicide formation technique using ion beam mixing has been developed for the purpose of forming a stable silicide or reducing the silicidation temperature. This is a technique of forming a silicide by forming a film of a refractory metal on silicon, performing ion implantation from the film, and then performing heat treatment.

However, there are some problems to be solved in the method of forming a contact between a metal and a semiconductor by forming these silicides.

Here, taking the case of forming a Ta silicide electrode on n ⁺ -Si as an example, the problems associated with the prior art will be described with reference to FIGS. FIG. 10 is a sectional view showing a step of forming a Ta silicide electrode on n ⁺ -Si. In FIG. 10A, 1001 is a p-type silicon wafer, and the resistivity is 0.3 to 1.0 Ω · cm.
SiO ₂ 1002 is formed as an insulating film on the surface of the wafer to a thickness of about 500 nm. On the surface of the wafer,
Partly n ⁺ with an n-type impurity concentration of 2 × 10 ²⁰ cm ⁻³
The high-concentration layer 1003 is formed, and the high-concentration layer 10
At least one opening 1004 is provided in the SiO ₂ 1002 so that a part of the region inside 03 can be electrically connected to the outside. A Ta layer 1005 is formed thereon with a thickness of about 10 nm. A wafer having this structure is heat-treated to form a silicide layer (TaSi ₂ )
1006 is formed (see FIG. 10B). As the heat treatment method, an electric furnace was used, and the Ar gas flow rate was 2 l / mi.
n, and an annealing treatment was performed at 900 ° C. for 1 hour. A Ta layer 1007 having a thickness of about 500 nm was formed thereon as a lead wiring material, and then patterned (see FIG. 10C).

FIG. 11 shows the measurement results of the contact resistance of the TaSi ₂ / n ⁺ -Si contact formed by this manufacturing process. Neither the resistance value nor the width of the variation in the value is a sufficient value for realizing a high-performance ULSI. The contact resistance of the metal semiconductor of the source of the MOS transistor and the emitter of the bipolar transistor is required to be extremely low. This is because if the resistance Rs of the source or the emitter is large, the current I flowing through the transistor cannot be increased and high-speed operation of the LSI cannot be realized. If a resistor Rs exists in the source and the emitter, the voltage Vgi applied to the intrinsic transistor is Vgi = Vg-RsI
Therefore, the control voltage Vg applied from the outside is reduced by RsI. If the transconductance of the transistor is gm, I = gm (Vg-RsI)
It becomes gmVg / (1 + gmRs), and when Rs is large, the denominator becomes large and the current I becomes extremely small. For example, the area of the contact hole is 0.1 × 0.1 μm ²
When (= 10 ^-10 cm ² ), the conventional contact resistance Rc = 1x
At 10 ⁻⁷ Ωcm ² , a single contact results in a contact resistance of 1 KΩ. Usually, in the case of CMOS structure,
Since at least four contacts are inserted between the power supply and ground, it is essential that Rc be 1 × 10 ⁻⁹ Ωcm ² or less.

FIG. 12 shows the result of secondary ion mass spectrometry (SIMS) measurement of the impurity concentration distribution in the depth direction of the TaSi ₂ / n ⁺ -Si junction formed by the above manufacturing process. With the above technique, although the interface between the silicide and Si can be cleaned to some extent, oxygen existing at the initial interface is taken into the silicide layer,
It was found to contribute to the increase in resistance. It was also confirmed that if an oxide film was formed on the metal surface before the heat treatment, the oxygen was mixed into the silicide layer during the heat treatment, and the resistance of the formed silicide layer increased.

Further, as a serious problem in the electrode forming process using silicidation according to the prior art, there is a problem that the silicide layer digs into the silicon substrate.

In the silicidation reaction between the refractory metal and silicon, since the silicide layer penetrates deeply into the silicon layer, it is very difficult to achieve an extremely shallow junction between the silicide and silicon. .

The formation of tantalum silicide (TaSi ₂ ) by the reaction between Ta and silicon is taken as an example, and the results of examining how much the silicide layer digs into the silicon substrate are shown in FIG. When a Ta film having a thickness of 10 nm is formed on a silicon substrate and heat-treated to react with the silicon substrate, a tantalum silicide layer having a thickness of about 24 nm is formed on the surface of the silicon substrate. Based on the interface between Ta and silicon at the initial stage, the silicide layer penetrates to a position of 22 nm in depth. It can be seen that the formed silicide has a shape in which 90% or more of the film thickness is submerged in the silicon substrate. Therefore, a large strain is locally generated due to the difference in the lattice spacing between Si and silicide, which causes defects and dislocations. Therefore, the electrode forming method using silicidation according to the prior art involves a limitation on the element structure in order to use it for forming an electrode of a semiconductor element having an ultrathin / ultra-shallow junction.

With the progress of ultra-miniaturization and ultra-high integration of ULSI, junctions in semiconductors, such as source / drain of MOSFET and emitter of bipolar transistor,
The depth has become extremely shallow, reaching about 10 to 50 nm. When a silicidation process of a metal thin film and silicon is used in the process of forming an ohmic contact electrode for a semiconductor layer having such an extremely shallow junction depth, according to the formation method of the prior art, the silicide layer is a source / drain layer. There is a risk of penetrating an ultra-thin layer such as an emitter or an emitter.

Judging from these facts, the conventional silicide formation technique cannot be said to be a perfect solution for drastically reducing the contact resistance, and also has a problem for extremely shallow junction, resulting in high ULSI. It must be said that achieving high performance and high reliability is extremely difficult.

[0016]

SUMMARY OF THE INVENTION The main object of the present invention is to realize two important requirements which are indispensable in an electrode / wiring forming process in a semiconductor device for high performance and high reliability ULSI. First, in order to reduce the contact resistance between the electrode portion and the semiconductor layer, the contamination layer mainly composed of the oxide film is eliminated, and the impurity concentration in the semiconductor layer in the region of about 1 nm near the interface between the metal layer and the semiconductor layer, that is, The aim is to form a high-quality metal-semiconductor contact structure that maximizes electron and hole densities, and the other is a metal-semiconductor contact structure for semiconductor devices having ultra-shallow and ultra-thin layers. Is to form.

[0017]

According to a method of manufacturing a semiconductor device of the present invention, at least a part of a semiconductor surface is continuously formed with at least one metal layer and a semiconductor layer without being exposed to the atmosphere, and then a heat treatment is performed. Then, the metal layer and the semiconductor are reacted to form a compound of the metal and the semiconductor.

Further, before the heat treatment, it is preferable to ion-implant a predetermined impurity atom or impurity molecule into the semiconductor through the semiconductor layer and the metal layer. An atom that generates electrons or holes in the semiconductor or a molecule containing the atom is preferable, and the injection amount is 1 ×.
It is preferably 10 ^{13 to 4} × 10 ¹⁸ cm ^-2 .

Further, the metal layer is made of Ta, Ti, W, C.
o, Mo, Hf, Ni, Zr, Cr, V, Pd and Pt
Among them, a refractory metal containing at least one of the above, an alloy containing a refractory metal, or a compound of a refractory metal is preferable, and its film thickness is preferably 1 to 50 nm.

Further, the semiconductor layer has an impurity concentration of 1 ×.
It is preferably 10 ¹⁸ cm ^-3 or less, and the concentration is preferably such that the surface is not immediately oxidized even when exposed to the atmosphere or washed with ultrapure water. Further, the film thickness is preferably 0.3 nm or more. Furthermore, it is preferable that the thickness of the semiconductor layer be larger than the thickness of the metal layer.

Furthermore, it is preferable that the semiconductor and the semiconductor layer are silicon semiconductors.

In the present invention, after the heat treatment, a second
When there is an unreacted semiconductor layer in forming the metal layer of, the unreacted semiconductor layer is removed to form a second metal layer, or the second metal layer is formed on the unreacted semiconductor layer. And then heat treatment is performed to form the unreacted semiconductor layer and the second layer.
To form a compound with the metal of the metal layer.

The method of manufacturing a semiconductor device according to the present invention is
After continuously forming a metal layer and a semiconductor layer on the substrate without exposing them to the atmosphere, heat treatment is subsequently performed to react the metal layer and the semiconductor layer to form a compound of the metal and the semiconductor, and then the unreacted It is characterized in that the metal layer is removed by etching to form a compound of a metal and a semiconductor in a predetermined shape. A semiconductor device of the present invention is manufactured by the above manufacturing method.

Further, at the contact portion between the semiconductor and the electrode,
In the semiconductor device in which the compound of the semiconductor and the metal is formed, the depth of the interface between the compound and the semiconductor is 22n.
It is characterized by making it shallower than m. Furthermore, the semiconductor device of the present invention is a semiconductor device in which a compound of the semiconductor and a metal is formed in the contact portion between the semiconductor and the electrode,
At least half the thickness of the compound is located above the semiconductor surface.

Furthermore, the semiconductor device of the present invention is characterized in that, in the semiconductor device having a multi-layered metal wiring structure, a thin silicide layer is provided in a contact portion connecting upper and lower metal wirings.

[0026]

In the present invention, in forming a junction between metal wirings or an electrode material and a semiconductor, a semiconductor layer is covered on a super-clean surface of a metal which is very easily oxidized so as to prevent contamination such as growth of an oxide film. Then, heat treatment is performed to form a compound of a metal and a semiconductor. This makes it possible to form a junction between an electrode having no oxide film and a semiconductor, and to form an electrode layer having very low impurities such as oxygen and low resistance. At the same time, by reacting the metal and the semiconductor such that the upper and lower sides of the metal layer are sandwiched by the semiconductor, the semiconductor required for the reaction can be supplied from both the upper and lower sides of the metal. Thereby, when the whole metal layer is reacted,
It is possible to reduce the depth of penetration of the compound layer of the metal and the semiconductor into the semiconductor. In particular, by setting the thickness of the semiconductor layer to be equal to or greater than the thickness of the metal layer, this bite can be made even shallower. In the present invention, the semiconductor layer is preferably made of the same material as the semiconductor, but the same effect can be obtained even if the material is different.

Further, it is also effective to improve the characteristics such as reduction of contact resistance by allowing the metal layer and the semiconductor layer to pass through and performing ion implantation near the interface between the metal layer and the semiconductor before the heat treatment. By the ion implantation, the metal and the semiconductor are mixed and the heat treatment temperature and the treatment time for forming the compound can be reduced. As the implanted ion species, a semiconductor dopant, a semiconductor constituent element, a metal layer constituent element, and the like are preferably used from the viewpoints of further reduction of contact resistance, recrystallization of semiconductor, and the like. In particular, by controlling the manufacturing process conditions so that the dopant concentration is maximized at the final interface between the compound layer of the metal and the semiconductor and the semiconductor by using the ion serving as the dopant of the semiconductor, the metal and the semiconductor are controlled. The contact resistance with can be reduced. The ion implantation amount and ion energy are appropriately determined depending on the implanted ion species, heat treatment conditions, the film thickness of the semiconductor layer and the metal layer, the constituent elements, etc., but from the viewpoint of further reduction of contact resistance and recrystallization of the semiconductor. , 1x10 ^{13 to} 4x1 respectively
It is preferably 0 ¹⁸ cm ^-2 and 16 to 200 KeV. Further, the injection amount is more preferably 1 × 10 ^{15 to} 1 × 10 ¹⁷ cm ⁻² .

In the manufacturing method of the present invention, the semiconductor and the semiconductor layer are made of Si, Ge, etc., and the metal layer is made of Ta, T.
i, W, Co, Mo, Hf, Ni, Zr, Cr, V, P
d, Pt and the like are preferably used. In particular, when Si is used as a semiconductor material and a refractory metal such as Ta, Ti, W, or Pt is selected as a metal material, it is suitably applied, and is extremely useful as a manufacturing method capable of further improving the performance of LSI. It is a promising manufacturing method.

The film thicknesses of the semiconductor layer and the metal layer are mutually determined by the ion implantation conditions, the heat treatment conditions, and the purpose of use. The preferred thickness of the semiconductor layer is 0.3n
It is m or more. The metal layer preferably has a thickness of 1 to 50 nm. When the thickness is 1 nm or more, a more uniform metal-semiconductor compound is formed, and when the thickness is 50 nm or less, generation of crystal defects at the time of compound formation can be suppressed.
Further, in the present invention, the impurity concentration of the semiconductor layer is 1 × 1.
The resistance is preferably 0 ¹⁸ cm ^-3 or less, and the resistance of the compound formed in this range can be further reduced. This is because if the impurity concentration of the semiconductor layer is higher than this, the surface is likely to be oxidized when exposed to the atmosphere.

The heat treatment of the present invention is preferably 100 ° C. or higher, more preferably 300 to 500 ° C. In this range, a compound of a metal and a semiconductor with low resistance and low contact resistance is formed.

Further, in the present invention, after the metal layer and the semiconductor layer are continuously formed on the substrate without exposing them to the air, heat treatment is subsequently performed to react the metal layer and the semiconductor layer with each other to form the metal and the semiconductor. Of the refractory metal or its compound, which has been difficult to form a fine pattern in the related art, by forming the compound of (1) and then removing the unreacted metal layer by etching to form the compound of the metal and the semiconductor in a predetermined shape. It is possible to precisely and finely pattern (silicide etc.).

[0032]

EXAMPLES The present invention will be described in more detail below with reference to examples.

(First Embodiment) A first embodiment of the present invention will be described below with reference to FIG. 1 (a)-(c)
It is sectional drawing which shows the process of forming the ohmic contact electrode by Ta silicide on n ^<+>- Si. 101 is, for example, a p-type silicon wafer and has a resistivity of, for example, 0.
It is 3 to 1.0 Ω · cm. The wafer is n
A mold may be used. For example, SiO ₂ 102 is formed as an insulating film on the surface of the wafer to a thickness of about 500 nm. On the surface of the wafer, an n ⁺ high-concentration layer 103 having a partial n-type impurity concentration of, for example, 1 to 2 × 10 ²⁰ cm ^−3.
Is formed, and an opening 104 is provided in the SiO ₂ 102 so that a part of the region in the high concentration layer 103 can be electrically connected to the outside. An electrode material layer 105 (for example, Ta layer) having a thickness of about 5 to 50 nm is formed thereon. Further, on the Ta layer 105, a Si layer 106 containing an impurity having a resistivity of about 0.01 to 10 kΩ · cm in an extremely low concentration (1 × 10 ^{12 to} 1 × 10 ¹⁵ cm ⁻³ ) and having a thickness of about 2 to 30 nm. Has been formed. Ta
The layer and the Si layer are continuously formed by using a high vacuum thin film forming apparatus without being exposed to the atmosphere. The reason why continuous film formation is necessary is that the surface of metal is instantaneously oxidized by 2 to 5 nm when exposed to the atmosphere. Especially when non-doped Si is formed on Ta, it is not oxidized for about 1 hour even when exposed to the atmosphere. Needless to say, a metal other than Ta may be used and the layer thickness can be freely selected according to the purpose and conditions. Also for the Si layer, the thickness of the layer can be freely selected according to the purpose and conditions (up to this point, see FIG. 1A). Ta is n-Si,
Schottky barrier height is 0.56 for p-Si
Since it is almost equal to eV, 0.58 eV, n ⁺ -Si, p ⁺
An extremely low contact resistance is realized for each of -Si. T
i is also a metal having similar characteristics.

Ion implantation was performed on the wafer having this structure. As the ion species to be implanted, impurities having the same type as the high concentration layer 103 on the wafer, for example, As ions are implanted. This may be P or Sb, but it is desirable that it is the same element as the impurity in the high concentration layer 103 in consideration of the matching of the crystal structures. The implantation dose is, for example, 2 × 10 ¹⁵ cm ⁻² , and the ion acceleration energy is, for example, 75 keV.

In the present embodiment, As ions were used to maximize the impurity concentration at the interface between the silicide and the Si semiconductor to further lower the contact resistance. However, when the purpose is simply ion mixing, other ions ( For example, Ta, Si, etc.) may be used.

After the ion implantation, heat treatment was performed to form a silicide layer (TaSi ₂ ) 107 and recrystallize the ion implanted layer. As the heat treatment method, an electric furnace is used, and A
Annealing treatment was performed at 900 ° C. for 1 hour while flowing r gas at a rate of 2 l / min. The heat treatment method may be lamp heating or any other method. The temperature is not limited to 900 ° C, but 400 to 500 ° C is sufficient. The gas is not limited to Ar, but may be H ₂ , N ₂ , H depending on the purpose and conditions.
Gases such as e or the like, or a mixed gas thereof may be used, and the flow rate may be other than the conditions described here.
It does not matter if the cleanliness of the gas is guaranteed. Alternatively, it may be more effective to perform the heat treatment in a vacuum in consideration of process consistency. It goes without saying that optimum conditions may be used for the temperature and the processing time depending on the purpose and conditions. Then, in a high-purity inert gas atmosphere, for example, in an N ₂ atmosphere, the unreacted Si layer remaining on the outermost surface is removed by an etching solution (for example, a mixed aqueous solution of hydrofluoric acid and nitric acid) to expose the silicide layer. It was For removing Si, Cl radicals may be generated in a Cl ₂ gas atmosphere. This is a treatment performed to completely eliminate the concern of residual Si layer. If the Si layer is entirely silicidized, the etching treatment as described here may not be performed (here Up to Figure 1 (b)
reference).

Further, the silicide layer exposed on the surface was transported in an ultrahigh-purity N ₂ atmosphere, and an electrode material was formed using an ultrahigh vacuum sputtering film forming apparatus. In this embodiment, for example, the Ta layer 108 is formed to a thickness of about 500 nm. The Ta layer 108 and the silicide layer 107 were patterned to form a lead electrode. Needless to say, an electrode material other than Ta may be used as the extraction electrode, and the film thickness may be any thickness other than that described here (see FIG. 1C).

FIG. 2 shows the contact resistance measurement results of the TaSi ₂ / n ⁺ -Si contact formed by the manufacturing process of the present invention. It can be seen that both the resistance value and the width of its variation are reduced as compared with the conventional example (FIG. 11). FIG. 3 shows a T formed by the manufacturing process of this embodiment.
The results of measuring the impurity concentration distribution in the depth direction by secondary ion mass spectrometry (SIMS) for the aSi ₂ / n ⁺ -Si junction are shown. Regarding oxygen, it is below the measurement limit value except for the surface. The presence of oxygen on the surface is due to the oxide film formed on the surface before the measurement is carried in to the SIMS device and the measurement is started.

From these results, the method of the present invention makes it possible to thoroughly prevent the mixing of oxygen in the formation of the junction between the electrode and the semiconductor, and to reduce the mixing of such pollutants, it is possible to form the electrode of the semiconductor device. It can be easily understood that it is very effective in reducing the resistance value in the process.

It is also understood from this figure that the As concentration is high near the silicide interface.

In this embodiment, an example of forming an electrode on an n-type high-concentration Si layer is shown, but the same applies to forming an electrode on a p-type high-concentration Si layer. However, in that case, as the high concentration layer 103, a p-type high concentration impurity layer is formed. Further, as the ion species to be implanted, impurities having the same type as the high concentration layer 103 on the wafer (for example, B ⁺ ions or BF ₂ ⁺ ions) are implanted. For example, when B ions are used, the energy of the ions is 16 to 25 Ke.
It becomes V. Alternatively, other ions (eg Si,
(Ta, etc.) may be sufficient.

As described above, by using the present invention, for example, the contact resistance between the electrode material layer and the semiconductor in the semiconductor device can be further reduced. As a result, it becomes possible to further improve the performance of ULSI.

(Embodiment 2) A second embodiment of the present invention is shown in FIG.
Will be explained. In this embodiment, ions are injected through the semiconductor layer formed on the metal layer to simultaneously perform ion implantation for ion mixing and ion implantation for forming a semiconductor high-concentration layer. Figure 4 (a)
The wafer of Example 1 satisfies the same conditions except that the high concentration layer 103 is not formed.

Ion implantation was performed on the wafer having the structure of FIG. As the ion species to be implanted, n
As ions, which serve as a dopant for the mold, were implanted. this is,
It may be P or Sb. The implantation dose is, for example, 2 × 10 ¹⁵ cm ⁻² , and the ion acceleration energy is, for example, 75 keV.

After the ion implantation, heat treatment was performed to form a silicide layer (TaSi ₂ ) 407 and recrystallize the ion implanted layer. In the heat treatment method, an electric furnace was used and Ar gas was caused to flow at a flow rate of 2 l / min for annealing at 500 ° C. for 1 hour (see FIG. 4B). The heat treatment method and conditions are the same as in Example 1.

Then, in a high-purity inert gas atmosphere, for example, an Ar atmosphere, unreacted S remaining on the outermost surface.
The i layer was removed by an etching solution such as a mixed aqueous solution of hydrofluoric acid and nitric acid to expose the silicide layer. Further, without exposing to the atmosphere, as an electrode material, for example, a Ta layer 4 is formed thereon.
08 was formed to a thickness of about 500 nm. The Ta layer 408 and the silicide layer 407 were patterned to form a lead electrode (see FIG. 4C). Needless to say, an electrode material other than Ta may be used, and the film thickness may be a thickness other than that described here.

FIG. 5 shows the measurement result of the current-voltage characteristic of the pn diode having the n ⁺ Si / pSi structure having TaSi ₂ as an electrode formed by the above manufacturing process. As shown in FIG. 5, it can be seen that good diode characteristics are obtained. As described in Example 1, this result is due to the thorough reduction of contamination such as oxygen during the formation of the bond, and is due to the effect of the bond forming method according to the present invention. .

In this embodiment, an example concerning the formation of the n-type high-concentration Si layer and the electrode formation is shown.
The same applies to the formation of layers and the formation of electrodes. However, in that case, as the ion species to be implanted, ions serving as p-type dopants (for example, B ions) are used.

(Embodiment 3) A third embodiment of the present invention relating to formation of a silicide-silicon junction having a very shallow junction will be described with reference to FIG.

Reference numeral 601 denotes p-type silicon on the wafer surface. The Si layer 601 may be a silicon layer formed on the wafer or the silicon wafer itself. Also, S
The surface of the i layer 601 may be covered with an insulating layer or a metal layer at some places, or a diffusion layer to which impurities are added may be formed at some places of the Si layer 601. The resistivity of the Si layer is, for example, 0.3 to 1.0 Ω · cm. The Si layer 601 may use an n-type depending on the purpose. Also,
The resistivity is not limited to the range described here, depending on the purpose and conditions. On the Si layer 601, for example, SiO ₂ 602 having a thickness of about 500 nm is formed as an insulating film. At least one opening 603 is provided in the SiO ₂ 602. A metal that reacts with silicon to generate a silicide, for example, a Ta layer 604 having a thickness of about 10 is formed thereon.
It is formed to have a thickness of about nm. Regarding the thickness, it may be thinner or thicker than this value, but in consideration of forming the silicide layer uniformly or preventing the generation of defects due to the volume change during the formation of the silicide as much as possible, the film thickness is about 10 nm. Optimally, it should be thick. Furthermore, a Si layer 605 containing an extremely low-concentration impurity having a resistivity of, for example, about 0.01 to 10 kΩ · cm is formed thereon with a thickness of about 30 nm. The thickness of the Si layer 605 is not limited to 30 nm, but the surface of the Ta layer 604 may be completely covered by the Si layer 6.
In consideration of covering with 05 and completely siliciding the entire Ta layer 604, there is no problem if the thickness is about 25 nm or more (see FIG. 6A).

Heat treatment is performed to form a silicide layer (TaSi
₂ ) 606 was formed. As the heat treatment method, an electric furnace is used, Ar gas is caused to flow at 2 l / min, and 700 ° C.
Annealing treatment was performed for 1 hour. The heat treatment method may be lamp heating or any other method. The gas is not limited to Ar, but may be H ₂ , N ₂ , H depending on the purpose and conditions.
Other gas such as e or the like, or a mixed gas thereof may be used, and the flow rate is not a problem other than the conditions described here as long as the cleanliness of the gas is guaranteed. In some cases, it may be more effective to perform the heat treatment in vacuum. Regarding temperature and processing time,
It goes without saying that the optimum conditions may be used according to the purpose and conditions.

After the formation of the silicide, the junction depth x _j with respect to the initial outermost surface of silicon before the reaction of the silicide layer was measured and found to be 12 nm (see FIG. 6B). When a similar measurement was performed on a silicide layer formed by a conventional method without forming the Si layer 605,
The junction depth was 22 nm.

From this result, it can be seen that the use of the silicide forming method of the present invention succeeds in making the junction depth shallow to a value of about 50% as compared with the conventional method. In order to manufacture high-performance and highly-integrated semiconductor devices, it is essential to make the junction extremely shallow. It is apparent from this example that the method for forming a silicide electrode according to the present invention is very effective in meeting this requirement.

(Embodiment 4) FIG. 7 is a sectional view showing a manufacturing process for forming a multilayer wiring structure according to a fourth embodiment of the present invention.

Reference numeral 701 is a semiconductor on the wafer surface. Here, a p-type silicon layer is used as an example. Si layer 701
May be a silicon layer formed on the wafer or the silicon wafer itself. Further, the surface of the Si layer 701 may be covered with an insulating layer or a metal layer at some places,
Diffusion layers to which impurities are added may be formed in some places of the Si layer 701. The resistivity of the Si layer is, for example, 0.3 to 1.0 Ω · cm. Depending on the purpose, n-type may be used. Further, the resistivity is not limited to the range described here, depending on the purpose and conditions. For example, a SiO ₂ layer 702 is formed as an insulating film layer on the Si layer 701, and at least one opening 703 for exposing the Si layer 701 is formed in a part of the SiO ₂ layer 702. . A metal layer (here, for example, a Ti layer) 704 is formed with a thickness of about 10 nm so as to cover the opening 703. Regarding the thickness, it may be thinner or thicker than this value, but in consideration of forming the silicide layer uniformly or preventing generation of crystal defects as much as possible at the time of forming the silicide, the thickness is about 10 nm. Is best done. Furthermore, the resistivity is, for example, 0.01 to
Si containing an extremely low concentration of impurities of about 10 kΩ · cm
The layer 705 is formed with a thickness of about 18 nm. The thickness of the Si layer 705 is not limited to 18 nm, but the surface of the Ti layer 704 is completely covered with the Si layer 705, and after the heat treatment, the metal and the unreacted Si layer should be at least one atomic layer or more. It may be determined in consideration of the thickness of the unreacted Si layer which is left unreacted. Here, T
The thickness is thicker than the i layer 704, for example, about 18 nm. Then, the Ti layer 704 and the Si layer 705 were patterned into an appropriate shape (up to this point, FIG. 7A).
See).

Then, heat treatment was performed. As a heat treatment method, an electric furnace was used, and Ar gas was caused to flow at 2 l / min.
Annealing treatment was performed at 700 ° C. for 1 hour. The heat treatment method may be lamp heating or any other method. The gas is not limited to Ar, and other gases such as H ₂ , N ₂ , He, etc., or a mixed gas thereof may be used depending on the purpose and the conditions, and the flow rate may be other than the conditions described here. But it doesn't matter. In some cases, it may be more effective to perform the heat treatment in vacuum. It goes without saying that optimum conditions may be used for the temperature and the processing time depending on the purpose and conditions. This heat treatment causes Ti and Si to react with each other, so that titanium silicide (T
iSi ₂ ) 706 was formed with a thickness of about 25 nm.
The junction depth of the titanium silicide layer to the Si layer 701 is about 12.5 nm, and the junction is made extremely shallow. The film thickness of the unreacted Si layer 705 was about 5.5 nm (see FIG. 7B up to this point).

Next, a SiO ₂ layer 707, for example, was formed as an interlayer insulating layer to electrically insulate the wirings by a chemical vapor deposition (CVD) method to a thickness of about 500 nm to 1 μm. An opening 708 for exposing the unreacted Si layer 705 on the silicide layer 706 is provided in at least one portion of the interlayer insulating layer 707 by reactive ion etching of the interlayer insulating film after the photolithography process. (Up to here, refer to FIG. 7C).

Next, the opening 708 was thoroughly washed with ultrapure water containing a few ppm of ozone, and then the oxide film on the surface of the Si layer 705 was removed using a 0.5 to 1% dilute hydrofluoric acid aqueous solution. . Then, a metal layer 709 is formed so as to cover the opening 708,
For example, a Ti layer was formed with a thickness of about 500 nm. Metal layer 7
09 may be another metal such as Ta or Pt as long as it is a metal that reacts with silicon stably to form a silicide compound. Further, regarding the film thickness, S exposed in the opening 708 is also included.
The film thickness may be such that it completely reacts with the i layer 705 and the contact portions of the metal layer 709 and the silicide layer 706 are entirely silicidized. The cleaning method is the opening 708.
Has a sufficient cleaning effect, and the Si layer exposed in the opening 708 is not completely lost, and is exposed in the opening 708 without leaving any passivation film on the surface of the Si layer. If the condition that the Si surface can be kept in an ultra-clean state is satisfied, the method used in this embodiment is not necessarily required. (See FIG. 7 (d)).

After that, heat treatment was performed to newly form a silicide layer 710. The heat treatment method is the same as the conditions already described in this example. Finally, Ti layer 7
11 was patterned into at least one arbitrary shape to form a wiring structure (see FIG. 7E).

According to the method for forming a multilayer wiring structure of this embodiment,
Even in the formation of a contact portion between metal wirings, the metal surface was covered with silicon to prevent the metal surface from being oxidized, and oxygen contamination at the interface of the metal layer was thoroughly suppressed. Further, in the cleaning of the opening immediately before the formation of the metal wiring on the contact portion, the method of covering the metal surface with Si was used, and thus it could not be used for the contact opening portion where the metal surface is exposed. It became possible to clean using an acidic solution, succeeded in achieving super cleaning of the contact interface, and improved the reliability of the contact part between metal wirings. Furthermore, conventionally, an interlayer insulating film, mainly SiO, is formed by directly contacting the metal surface.
_{Since 2} was formed, there was a problem that the electrical properties such as electric resistance and electromigration resistance due to oxidation of the metal surface deteriorate, or the problem of poor adhesion between the metal and the oxide film. In this method, since the insulating film is formed with the silicon layer left on the silicide layer, the metal surface is not oxidized and SiO ₂ is formed on the silicon layer firmly remaining on the silicide. Adhesion was also improved. In this example, the purpose is to reduce the contact resistance between the multilayer metal wirings. Figure 7
In the above, the example in which the metal layer 709 formed on the Si layer 705 is formed of Ti and on the entire surface has been described. However, selective film formation of tungsten (W) using WF ₆ and SiH ₄ gas for the purpose of surface flattening. It is extremely effective to perform the above step only on the Si layer of the opening 708 and form WSi ₂ by the reaction with the Si layer 705.

In a super high speed microprocessor or the like, metal multilayer wiring is often used. When the metal surface is exposed to the air, the surface is instantly oxidized and an oxide film of about 2 to 5 nm is formed. Therefore, the contact resistance between metal and metal is inevitably increased, which deteriorates the high-speed characteristics of the microprocessor and reduces the logic amplitude. In order to prevent the oxidation of the metal surface, the process shown in FIG. 14 is effective.
Here, for selectively filling the contact holes, WF ₆ , S
An example of using selective growth of W using iH ₄ will be described.

A first layer of Al metal wiring (about 0.5 to 1 μm) 1402 and non-doped S are formed on the interlayer insulating film 1401.
The i layer (about 5 to 10 nm) 1403 is continuously formed. It is preferable that the interlayer insulating film 1404 be continuously formed by a cluster tool, but since the non-doped Si 1403 is less likely to be oxidized, the surface may be hydrogen-terminated and then transferred in the atmosphere to be formed. Then, a hole is formed in the interlayer insulating film 1404 according to a predetermined pattern by a photolithography process. At this time, although it is currently exposed to the atmosphere, the Al alloy surface is not oxidized due to the presence of non-doped Si.

Only in the non-doped Si, W1405 is selectively formed in the contact hole portion by WF ₆ + SiH ₄ system selective CVD (about 180 ° C.), and the non-doped Si 1403 is entirely reacted with W by heat treatment at 400 to 450 ° C. Change to ₂ . In this way, WSi ₂ intervenes in the W and Al alloys, and W and Al alloys are contacted without any oxide film.

Further, by preventing the oxide film from existing even in contact with the Al alloy 1406 on W1405, it is possible to realize contact without an oxide film at all contact portions in the multilayer wiring structure. When the Al alloy thin film 1406 can be formed without being exposed to the atmosphere by using a cluster tool or the like, oxygen is mixed by forming the Al alloy thin film 1406 directly on the surface of the formed W1405 as shown in FIG. It is possible to form an interface with less heat. Here, instead of the W and Al alloys, metals such as Ta, Ti, Cu, Al and Ag, or alloys thereof may be used. Further, this method may be applied to any layer of the multilayer wiring structure.

Even if a device such as a cluster tool is not used, by forming the non-doped Si layer 1408 on the W 1405 as shown in FIG. 15, it is possible to realize a multi-layer wiring structure having no oxide film at the interface. That is, since the non-doped Si is hard to be oxidized by forming the Al alloy thin film 1406 by transporting it in the air after forming the non-doped Si, an interface without an oxide film can be formed between the wirings. Further, in order to further improve the oxidation resistance, the surface may be hydrogen-terminated after the formation of non-doped Si.

The non-doped Si 1408 can be continuously formed by using, for example, a W1405 forming CVD apparatus. That is, using WF ₆ and SiH ₄ gas, W 14
No. 05 is formed, and then the WF ₆ gas is stopped to form the non-doped Si 1408 by using only the SiH ₄ gas. A
After processing the 1-alloy thin film 1406, the non-doped Si remaining on the insulating film 1404 is usually removed, but it may not be necessary to remove it because it has high resistance. On the other hand, undoped Si
It is also possible to selectively form 1408 only on W1405. In this case, after processing the Al alloy thin film 1406, the structure as shown in FIG.
No undoped Si is formed on top. Also in this case, as described above, the undoped Si1408 and W14
Formation of 05 can be continuously performed in the same CVD apparatus.

A non-doped Si thin film 1407 is continuously formed on the second Al alloy thin film 1406. Thus, if non-doped Si is formed on the Al alloy thin film, especially if the non-doped Si surface is hydrogen-terminated, W
W selective growth with F ₆ + SiH ₄ can be perfectly performed, and it is extremely effective for surface flattening. Here, it goes without saying that the Al alloy may be pure Al, Cu, or Ag.

(Embodiment 5) FIG. 8 is a sectional view showing a method of manufacturing an ohmic contact electrode / wiring structure of a semiconductor and a metal by forming a silicide according to a fifth embodiment of the present invention.

Reference numeral 801 is a semiconductor layer. Here, an n-type silicon layer is used as an example. A p-type may be used depending on the purpose. The Si layer 801 may be a silicon layer formed on the wafer or the silicon wafer itself. Further, the surface of the Si layer 801 may be covered with an insulating layer or a metal layer at some points, or a diffusion layer having impurities added thereto may be formed at some points of the Si layer 801. The resistivity of the Si layer is, for example, 0.3 to 1.0 Ω · cm. Further, the resistivity is not limited to the range described here, depending on the purpose and conditions.

[0070] on the Si layer 801, the insulating film layer such as SiO ₂ layer 802 is formed, the SiO ₂ layer 80
A part of 2 is an opening 803 for exposing the Si layer 801.
Is formed in at least one place. Opening 803
To cover the metal layer, here, for example, Ti layer 804 is 1
It has a thickness of about 0 nm and is formed almost all over the wafer. The metal layer 804 may be another metal such as Ta, Co, or W as long as it is a metal that reacts with silicon stably to form a silicide compound.

However, the solution for etching the metal is
It is necessary that the etching reaction is difficult to proceed with respect to the silicide of the metal, that is, the etching solution is such that the ratio of the etching reaction of the metal to the etching reaction of the silicide can be made large. The same applies to dry etching. Regarding the thickness, it may be thinner or thicker than this value, but in consideration of forming the silicide layer uniformly or preventing generation of crystal defects as much as possible during the formation of the silicide, a film of about 5 to 10 nm is formed. Optimally, it should be thick.

Furthermore, the resistivity is 0.0, for example.
A Si layer 805 containing an extremely low-concentration impurity of about 1 to 10 kΩ · cm is formed to a thickness of about 8 to 13 nm, and a part of the Si layer 805 is patterned in at least one or more arbitrary shapes. The thickness of the Si layer 805 is 8 to
The thickness is not limited to 13 nm, but in the present embodiment, T
completely covering the surface of the i layer 804 with the Si layer 805,
Taking into consideration silicidation of the entire Si layer 805, the thickness is set to, for example, about 8 to 13 nm (see FIG.
(See (a)).

Ion implantation was performed on the wafer having the structure of FIG. As the ion species to be implanted,
For example, As ions serving as an n-type dopant are implanted. This may be P or Sb. In this embodiment, ions for n-type dopant are implanted for manufacturing the ohmic contact electrode / wiring structure. However, when the purpose is simply silicidation, other ions (for example, Si, Ti) are used. But good. The implantation dose is, for example, 2 × 10 ¹⁵ cm ⁻² , and the ion acceleration energy is, for example, 75 keV. In this embodiment, the mixing by ion implantation is used to promote the silicidation reaction, but the ion implantation need not necessarily be performed.

After the ion implantation, heat treatment was performed to form a silicide layer (TiSi ₂ ) and recrystallize the ion implanted layer. As a heat treatment method, an electric furnace was used and Ar gas was caused to flow at a flow rate of 2 l / min to carry out annealing treatment at 450 ° C. for 3 hours. The heat treatment method may be lamp heating or any other method. The gas is not limited to Ar, and other gases such as H ₂ , N ₂ , He, etc., or a mixed gas thereof may be used depending on the purpose and the conditions, and the flow rate may be other than the conditions described here. But it doesn't matter.

In some cases, it may be more effective to perform the heat treatment in vacuum. It goes without saying that optimum conditions may be used for the temperature and the processing time depending on the purpose and conditions. By this heat treatment, only Ti in the vicinity of the portion covered with the Si layer 805 reacts with silicon, and titanium silicide (TiSi ₂ ) 806 has a thickness of 12 to 25 nm.
It was formed with a thickness of the order. Other portions of Ti not covered with the Si layer 805 remained unreacted. The implanted As was activated as a dopant by heat treatment, and an n-type high concentration layer 807 was formed around the silicide layer 806 (up to this point, see FIG. 8B).

Next, this wafer was mixed with NH ₄ OH, H ₂ O ₂ and H ₂ O in a volume ratio of 5: 1: 1 to prepare an aqueous solution (25
C.). Mixing ratios of liquids may be other ratios such as 4: 1 :.
1: can be The liquid temperature is not limited to 25 ° C, but if the liquid temperature is too high, H ₂ O ₂ is decomposed or evaporated, and conversely, if the liquid temperature is too low, the reaction rate decreases, so the temperature is 25 ° C. It was about degree. By immersing in this aqueous solution, the unreacted Ti layer is etched and disappears, and SiO ₂
The surface of layer 802 was exposed. On the other hand, the portion where TiSi ₂ is formed remains without being etched, and titanium silicide (TiSi ₂ ) for ohmic contact with Si is left.
An electrode and its lead wiring structure were formed (see FIG. 8).
(See (c)). In this embodiment, the method relating to TiSi ₂ is shown. However, when another metal such as Co is used, for etching after silicide formation, for example, an aqueous solution containing a mixture of HCl, H ₂ O ₂ and H ₂ O is used. Should be used.

In forming the ultrafine structure, patterning by a dry etching process is essential. However, when it is difficult to perform dry etching like CuSi, the wet etching method is also effective. That is, a silicon layer patterned into a predetermined shape is formed on the refractory metal. It is easy to perform fine patterning on silicon by using dry etching. Next, heat treatment may be applied or ion mixing may be preceded, but a silicide layer is formed over the entire refractory metal layer. Since only the refractory metal in the portion in contact with silicon is silicide, the width of the formed silicide and the width of the previously patterned silicon layer are almost equal. Then, only the unreacted refractory metal is selectively wet-etched so that only the silicide remains, and it becomes possible to form a fine structure such as an electrode and a wiring in a predetermined shape (see FIG. 8D).

(Embodiment 6) FIG. 9 is a sectional view showing a sixth embodiment of the present invention. The present embodiment has a semiconductor layer having an extremely shallow junction depth, an electrode structure of a compound of a semiconductor and a metal, and can form an electrode / wiring structure with an arbitrary film thickness.

Reference numeral 901 denotes a semiconductor layer. Here, a silicon wafer is used as an example. The surface of the Si layer 901 may be covered with an insulating layer or a metal layer at some places, or Si
Diffusion layers to which impurities are added may be formed in some parts of the layer 901. An SiO ₂ layer 902, for example, is formed as an insulating film layer on the Si layer 901. On the surface of the wafer, a portion of the n-type impurity concentration is, for example, 1-2.
An n ⁺ high-concentration layer 903 of × 10 ²⁰ cm ⁻³ is formed, and an opening 904 is formed in the SiO ₂ 902 so that a part of the region in the high-concentration layer 903 can be electrically connected to the outside.
Is provided in at least one place.

On the insulating film layer 902, a metal layer, for example, the Ta layer 905-here is formed so as to cover the opening 904.
1 has a thickness of about 10 nm and is formed almost all over the wafer. If the metal layer 905-1 is a metal that reacts with silicon stably to form a silicide compound, Ti, W,
Other metals such as Pt may be used. Regarding the thickness, it may be thinner or thicker than this value, but in consideration of forming the silicide layer uniformly or preventing generation of crystal defects as much as possible during the formation of the silicide, a film of about 5 to 10 nm is formed. Optimally, it should be thick.

Further on that, the resistivity is, for example, 0.0.
A Si layer 906-1 containing an extremely low concentration of impurities of about 1 to 10 kΩ · cm is formed with a thickness of about 22 nm. The thickness of the Si layer 906-1 is not limited to 22 nm, but in the present embodiment, the surface of the Ta layer 905-1 is completely covered with the Si layer 906-1, or the Si layer 906 is formed.
In consideration of silicidation of the whole -1, it is set to about 22 nm, for example.

Then, ion implantation was performed. As the ion species to be implanted, for example, As ions serving as an n-type dopant were implanted. This may be P or Sb.
The implantation dose is, for example, about 2 × 10 ¹⁵ cm ⁻² , and the ion acceleration energy is, for example, 75 keV.
(See FIG. 9A up to here).

On the Si layer 906-1, a metal layer, for example, a Ta layer 905-2 here is formed over the entire surface of the wafer with a thickness of about 10 nm. Metal layer 905-
2 may be another metal, but the metal layer 905-
Optimally, it is the same material as 1. Regarding the thickness, it may be thinner or thicker than this value, but in consideration of forming the silicide layer uniformly or preventing generation of crystal defects as much as possible at the time of forming the silicide, it is 5 to 1
Optimally, the film thickness is about 0 nm. Furthermore, a Si layer 906-2 containing an extremely low-concentration impurity having a resistivity of, for example, about 0.01 to 10 kΩ · cm is formed thereon with a thickness of about 22 nm. The thickness of the Si layer 906-2 is not limited to 22 nm, but in the present embodiment, the surface of the Ta layer 905-2 is completely covered with the Si layer 906-2.
In consideration of covering with, and silicidation of the entire Si layer 906-2, for example, the thickness is set to about 22 nm (up to this point, see FIG. 9B).

After that, considering the thickness of the silicide layer to be formed, the formation of the metal layer and the formation of the silicon layer on the metal layer may be repeated an arbitrary number of times. For example, four pairs of metal layers and silicon layers were formed. Ta layers are 905-3 and 90
5-4, Si layers are 906-3 and 906-4 (see FIG. 9C up to this point).

Then, heat treatment was performed. The methods and conditions are exactly the same as those for the heat treatment described in Example 1. By heat treatment, the tantalum silicide layer 9
07 was formed to a thickness of about 96 nm. In this example, four pairs of the metal layer and the silicon layer are formed to have a thickness of 96 nm, but the thickness of the silicide layer can be controlled relatively freely by controlling the number of times the layers are formed. Further, in the present embodiment, the heat treatment is performed once after the final film is formed, but if the Si layer 906-2 is formed, the heat treatment may be performed at least once and any number of times at any time. . Further, after the Si layer 906-2 is formed, the ion implantation may be performed at any time and any number of times. After forming the silicide layer 907, patterning was performed in an arbitrary shape to fabricate an electrode / wiring structure (up to this point, see FIG. 6D).

By this method, a contact electrode of silicide and silicon having a very shallow junction could be formed. As described in Example 1, as a result of the high performance of the contact formation process, the dopant concentration at the interface was maximized, and the contamination such as oxygen was thoroughly reduced, resulting in a very low contact resistance value. Was realized.

Further, in the contact portion, it is desirable that the film thickness of the metal is as thin as possible in order to suppress the crystal strain caused by the stress strain caused by the thermal stress at the time of forming the silicide or the difference in the lattice constant. However, in consideration of the problem of wiring resistance or disconnection, it is desirable that the film thickness of the metal be as thick as possible in order to simultaneously form the contact electrode and the lead wiring by silicidation. By using the manufacturing method shown in this embodiment, the contact electrode and the lead-out wiring structure can be simultaneously formed by using the silicide layer having a certain thickness while thoroughly suppressing the generation of crystal defects, and the electrical characteristics thereof can be improved. In addition, the depth of penetration into the silicon layer caused by silicide formation and the extremely shallow depth can be realized at the contact portion. Therefore,
The semiconductor device manufacturing method according to the present embodiment is a high-performance ULSI.
It can be said that it is very useful for realizing.

[0088]

As described above, according to the present invention, it is possible to form a metal electrode having a very low contact resistance and achieve an extremely shallow junction depth. Realization is possible.

[Brief description of drawings]

FIG. 1 is a conceptual diagram showing a first embodiment of the present invention, which is a conceptual diagram showing a method of manufacturing an ohmic contact electrode for high-concentration silicon using a silicide electrode in the order of steps.

FIG. 2 is a graph showing contact resistance between an electrode and a semiconductor of Example 1.

FIG. 3 is a graph showing the impurity concentration distribution in the depth direction in the electrode structure of Example 1.

FIG. 4 is a conceptual diagram showing a second embodiment of the present invention, p
It is a conceptual diagram which showed the manufacturing method of an n-junction diode structure in process order.

5 is a graph showing the current-voltage characteristics of the diode of Example 2. FIG.

FIG. 6 is a conceptual diagram showing a third embodiment of the present invention, which is a conceptual diagram showing a method of manufacturing a junction structure of a silicide having a very shallow junction and a semiconductor in the order of steps.

FIG. 7 is a fourth embodiment of the present invention and is a conceptual diagram showing a method of manufacturing a multilayer wiring structure having high reliability in the order of steps.

FIG. 8 is a conceptual diagram showing a fifth embodiment of the present invention, which is a conceptual diagram showing a method of manufacturing an electrode / wiring shape by forming a silicide in the order of steps.

FIG. 9 is a conceptual diagram showing a sixth embodiment of the present invention, which is a concept showing a method for manufacturing a highly reliable silicide electrode / wiring structure in which the junction depth between silicide and silicon is extremely shallow, in the order of steps. It is a figure.

FIG. 10 is a conceptual diagram showing a contact between a prior art electrode and a semiconductor.

FIG. 11 is a graph showing contact resistance between a prior art electrode and a semiconductor.

FIG. 12 is a graph showing an impurity concentration distribution in the depth direction in a prior art electrode structure.

FIG. 13 is a conceptual diagram showing the depth of a silicide / silicon junction surface in the prior art.

FIG. 14 is a conceptual diagram showing another example of the multilayer wiring structure of the present invention.

FIG. 15 is a conceptual diagram showing another example of the multilayer wiring structure of the present invention.

FIG. 16 is a conceptual diagram showing another example of the multilayer wiring structure of the present invention.

[Explanation of symbols]

101 semiconductor, 102 insulating layer, 103 high-concentration semiconductor layer, 104 opening, 105 metal layer, 106 semiconductor layer, 107 compound layer of semiconductor and metal, 108 metal layer, 403 high-concentration semiconductor layer, 407 semiconductor and metal Compound layer, 408 metal layer, 601 semiconductor, 602 insulating layer, 603 opening, 604 metal layer, 605 semiconductor layer, 606 compound layer of semiconductor and metal, x _j junction depth, 701 semiconductor, 702 insulating layer, 703 opening Part, 704 metal layer, 705 semiconductor layer, 706 compound layer of semiconductor and metal, 707 insulating layer, 708 opening, 709 metal layer, 710 compound layer of semiconductor and metal, 711 metal layer, 801 semiconductor, 802 insulating layer , 803 opening, 804 metal layer, 805 semiconductor layer, 806 compound layer of semiconductor and metal, 901 semiconductor, 902 insulating layer, 903 high concentration semiconductor layer, 904 opening, 905-1, -2, -3, -4 metal layer, 906-1, -2, -3, -4 semiconductor layer, 907 semiconductor and Compound layer with metal, 1001 semiconductor, 1002 insulating layer, 1003 high concentration semiconductor layer, 1004 opening, 1005 metal layer, 1006 compound layer with semiconductor and metal, 1007 metal layer, 1401, 1404 interlayer insulating film, 1402 first Al alloy wiring, 1403, 1407, 1408 Non-doped Si layer, 1405 Selectively grown tungsten (W), 1406 Second Al alloy wiring.

Claims (23)

[Claims] 1. A metal layer and a semiconductor layer are continuously formed on at least a part of a semiconductor surface without exposing to the atmosphere, and then heat treated to react the metal layer and the semiconductor with a metal. A method of manufacturing a semiconductor device, which comprises forming a compound with a semiconductor. 2. The method for manufacturing a semiconductor device according to claim 1, wherein a predetermined impurity atom or impurity molecule is ion-implanted into the semiconductor through the semiconductor layer and the metal layer before the heat treatment. . 3. The manufacturing of a semiconductor device according to claim 2, wherein the ion is an element forming the semiconductor, an atom generating an electron or a hole in the semiconductor, or a molecule containing the atom. Method. 4. The manufacturing of a semiconductor device according to claim 3, wherein the impurities of the semiconductor are ion-implanted so that the impurity concentration in the semiconductor becomes maximum at the interface between the semiconductor and the compound. Method. 5. The ion implantation amount is 1 × 10 ¹³ to 4
It is x10 ^{< 18} > cm ^<-2 >, The manufacturing method of the semiconductor device of any one of Claims 2-4 characterized by the above-mentioned. 6. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor is a silicon (Si) semiconductor. 7. The semiconductor device according to claim 1, wherein the metal layer is a refractory metal, an alloy containing a refractory metal, or a compound of a refractory metal. Production method. 8. The metal layer comprises Ta, Ti, W, Co,
8. The method of manufacturing a semiconductor device according to claim 7, further comprising at least one of Mo, Hf, Ni, Zr, Cr, V, Pd and Pt. 9. The method of manufacturing a semiconductor device according to claim 1, wherein the metal layer has a thickness of 1 to 50 nm. 10. The semiconductor layer has an impurity concentration of 1 × 1.
The method for manufacturing a semiconductor device according to claim 1, wherein the method is 0 ¹⁸ cm ⁻³ or less. 11. The semiconductor layer according to claim 1, wherein the thickness of the semiconductor layer is 0.3 nm or more.
A method of manufacturing a semiconductor device according to item. 12. The method of manufacturing a semiconductor device according to claim 11, wherein the thickness of the semiconductor layer is equal to or larger than the thickness of the metal layer to make the interface between the compound and the semiconductor shallow. 13. The method of manufacturing a semiconductor device according to claim 11, wherein more than half of the thickness of the compound formed after the heat treatment is located on the semiconductor layer side. 14. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor layer is made of a silicon (Si) semiconductor. 15. The second metal layer is subsequently formed when no unreacted semiconductor layer remains after the heat treatment, according to any one of claims 1 to 14. Of manufacturing a semiconductor device of. 16. The method of manufacturing a semiconductor device according to claim 1, wherein after the heat treatment, the unreacted semiconductor layer is removed to form the second metal layer. . 17. After the heat treatment, a second metal layer is formed on the unreacted semiconductor layer and then heat treated to form a compound of the unreacted semiconductor layer and the metal of the second metal layer. The method for manufacturing a semiconductor device according to claim 1, wherein the method is for manufacturing a semiconductor device. 18. A metal layer and a semiconductor layer are continuously formed on a substrate without being exposed to the air, and then the semiconductor layer is patterned into a predetermined shape, followed by heat treatment to react the metal layer and the semiconductor layer. A method of manufacturing a semiconductor device, comprising: forming a compound of a metal and a semiconductor, and then etching and removing an unreacted metal layer to form a compound of the metal and the semiconductor in a predetermined shape. 19. A semiconductor device manufactured by the method for manufacturing a semiconductor device according to claim 1. Description: 20. A semiconductor device in which a compound of a semiconductor and a metal is formed at a contact portion between a semiconductor and an electrode, and a depth of an interface between the compound and the semiconductor is 22 nm.
A semiconductor device characterized by being made shallower. 21. A semiconductor device having a compound of a semiconductor and a metal formed in a contact portion between a semiconductor and an electrode, wherein a depth of an interface between the compound and the semiconductor is 12 nm.
21. The semiconductor device according to claim 20, wherein: 22. In a semiconductor device in which a compound of a semiconductor and a metal is formed at a contact portion between a semiconductor and an electrode, at least half the thickness of the compound is located above the surface of the semiconductor. A semiconductor device characterized by the above. 23. A semiconductor device having a multi-layered metal wiring structure, wherein a thin silicide layer is provided in a contact portion connecting upper and lower metal wirings.