JPH0661177A - Semiconductor integrated circuit device and manufacture thereof - Google Patents

Abstract

PURPOSE:To lessen a base metal film of a wiring which forms a semiconductor integrated circuit device and a semiconductor substrate in contact resistance between them. CONSTITUTION:A silicide layer 12 which is made of combined material composed of the component atoms of a base metal film 10a and a semiconductor substrate 1 and epitaxial to the semiconductor substrate 1 is provided to a contact surface between the base metal film 10a of a wiring 10 which forms a semiconductor integrated circuit device and a semiconductor layer 5 located on the semiconductor substrate 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a manufacturing technique thereof, and more particularly to a connection technique between a wiring which constitutes the semiconductor integrated circuit device and a semiconductor substrate.

[0002]

2. Description of the Related Art Aluminum (Al) or its alloy is used as a wiring material of a semiconductor integrated circuit device.
Al has a low resistivity, has a low contact resistance with a p ^{+ type} or n ^{+ type} semiconductor layer formed on silicon (Si), and is easy to form and process. This is because it has excellent properties for use as.

However, in the case of a single-layer Al wiring, wiring disconnection defects due to electromigration / stress migration and Si deposition on the Al wiring side are caused by miniaturization of wiring and connection holes in a semiconductor integrated circuit device. The problem of the reliability of the wiring has become remarkable, such as an increase in contact resistance between the Al wiring and the semiconductor substrate.

Therefore, in recent years, for example, titanium tungsten (TiW) and titanium nitride (Ti) are formed under the Al wiring.
N), tungsten (W), molybdenum (Mo), or the like provides a base metal film to prevent wiring disconnection defects, deposition of Si, and the like, and tends to secure the reliability of the wiring.

However, when the underlying metal film is brought into direct contact with the Si substrate, contact resistance, especially p-channel MOS.F
There is a problem that the contact resistance at the contact portion becomes high when the p-type semiconductor layer forming the source / drain regions such as ET (hereinafter simply referred to as pMOS) is directly contacted.

A possible solution is to increase the contact area, but in this case, it is against the tendency of miniaturization of the semiconductor integrated circuit device. Further, it is conceivable to set the impurity concentration of the p-type semiconductor layer to be higher, but in that case, there arises a problem of degrading the characteristics of the pMOS such as a short channel effect, which hinders miniaturization of the pMOS.

Therefore, without causing such a problem,
As a method of reducing the contact resistance between the underlying metal film and the p-type semiconductor layer, a low-resistance silicide layer such as a platinum silicide (PtSi) layer is interposed between the underlying metal film and the p-type semiconductor layer. The method of making it proposed is proposed. This method is as follows, for example.

First, an opening for exposing a p-type semiconductor layer is formed in the insulating film on the main surface of the Si substrate, and then P is formed on the Si substrate.
Deposit a t-film. Then, heat treatment is applied to the Si substrate to cause Pt and Si to react with each other at a contact portion between the Pt film and the p-type semiconductor layer to form a PtSi layer at the contact portion, and then the Pt film is subjected to aqua regia. Remove by. At this time, the PtSi layer remains on the p-type semiconductor layer in the connection hole. After that, a base metal film and an Al alloy film are sequentially deposited on the Si substrate, and then the laminated film thereof is patterned by a photolithography technique to form a two-layer structure wiring.

The prior art of forming a base metal film under the Al wiring is described in, for example, Nikkan Kogyo Shimbun, Showa 6
It is described in "CMOS Device Handbook" P332 to P333, published on September 29, 2013, and explains the necessity of providing a barrier metal under the Al wiring.

[0010]

By the way, a conventional low-resistance silicide layer such as a PtSi layer is provided at a contact portion between a base metal film forming a wiring and a p-type semiconductor layer of a semiconductor substrate. Does not conflict with the miniaturization of the semiconductor integrated circuit device, and since it is not necessary to increase the impurity concentration of the semiconductor layer, the short channel effect does not occur and the miniaturization of the element can be promoted. However, the present inventor has found that the steps of depositing the Pt film and the step of removing the Pt film are required, which increases the number of manufacturing steps of the semiconductor integrated circuit device and complicates the steps. It was

The present invention has been made in view of the above-mentioned problems, and an object thereof is to prevent the increase and complexity of the manufacturing process of a semiconductor integrated circuit device, and to provide a base metal film forming a wiring and a semiconductor substrate. It is to provide a technology capable of lowering the contact resistance with.

The above and other objects and novel features of the present invention will be apparent from the description of the specification and the accompanying drawings.

[0013]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

That is, according to the first aspect of the invention, a wiring is formed by laminating a base metal film and a conductor film in order from the lower layer on an insulating film on a semiconductor substrate, and the base metal film and the semiconductor substrate are provided. In the semiconductor integrated circuit device structure, the underlying metal film and the constituent atoms of the semiconductor substrate are combined with each other in the contact portion, and a compound layer that is epitaxial with respect to the semiconductor substrate is provided.

According to a fourth aspect of the present invention, a step of forming a connection hole reaching the semiconductor substrate in an insulating film on the semiconductor substrate, and a base metal film for forming a wiring is deposited on the insulating film in which the connection hole is formed. And the semiconductor substrate is annealed, and at the contact portion between the base metal film and the semiconductor substrate, the constituent atoms of the base metal film and the semiconductor substrate are combined to form an epitaxial film on the semiconductor substrate. And a step of electrically connecting the underlying metal film and the semiconductor substrate to each other.

[0016]

According to the invention described in claim 1, for example, since the work function difference between the base metal film forming the wiring and the semiconductor layer of the semiconductor substrate can be reduced, the wiring and the p
It is possible to lower the contact resistance with the shaped semiconductor layer.

Therefore, for example, the impurity concentration of the p-type semiconductor layer forming the source / drain region of the pMOS can be made lower than before, so that the short channel effect of the pMOS can be suppressed and the miniaturization of the pMOS can be promoted. It becomes possible.

According to the invention described in claim 4, for example, the step of depositing the Pt film and the step of removing the Pt film are not required, so that the number of manufacturing steps of the semiconductor integrated circuit device can be reduced. The process can be simplified.

[0019]

Embodiment 1 FIG. 1 is a cross-sectional view of an essential part of a semiconductor integrated circuit device according to an embodiment of the present invention, and FIGS. 2 to 4 are cross-sectional views of an essential part of a semiconductor integrated circuit device shown in FIG. 5 is a graph showing the relationship between the contact resistance between the wiring and the semiconductor substrate and the annealing temperature.

The semiconductor integrated circuit device of the first embodiment is composed of, for example, a CMOS (Complimentary MOS) circuit. FIG. 1 shows the pMOS portion of the semiconductor integrated circuit device of the first embodiment.

The semiconductor substrate 1 is made of, for example, an n ^--type Si single crystal, and a non-active region on its main surface is made of, for example, SiO 2.
_A field insulating film 2 made of 2 is formed. A channel stopper layer 3 is formed below the field insulating film 2. Phosphorus, which is an n-type impurity, is introduced into the channel stopper layer 3.

On the main surface of the semiconductor substrate 1, for example, a pMOS 4 is formed in the active region surrounded by the field insulating film 2. That is, the periphery of the pMOS 4 is defined by the field insulating film 2.

The pMOS 4 is composed of semiconductor layers 5 and 5 formed on the semiconductor substrate 1, a gate insulating film 6 formed between the semiconductor layers 5 and 5, and a gate formed on the gate insulating film 6. And an electrode 7.

The semiconductor layer 5 is formed by introducing, for example, boron which is a p-type impurity.
^{And + type} semiconductor layer 5b. That is, in the first embodiment, the pMOS 4 is LDD (Lightly
Doped Drain) structure.

The gate insulating film 6 is made of SiO ₂ , for example. The gate electrode 7 is configured, for example, by stacking two layers of conductor films 7a and 7b in order from the lower layer. Conductor film 7a
Is made of doped polysilicon, for example. The conductor film 7b is made of, for example, tungsten silicide (WSi ₂ ).

A spacer 8 is formed on the side wall of the gate electrode 7. The spacer 8 is an insulating film for forming the LDD structure and is made of, for example, SiO ₂ .

An interlayer insulating film 9 is deposited on the semiconductor substrate 1. The interlayer insulating film 9 is made of, for example, SiO ₂ , and the wiring 10 is formed thereon.

The wiring 10 is formed by laminating a base metal film 10a and a conductor film 10b in order from the lower layer, and a part of the base metal film 10a is formed in the interlayer insulating film 9 as a connection hole 11 which is formed in the connection hole 11.
Is electrically connected to the semiconductor layer 5 through.

In the first embodiment, the base metal film 10a is provided at the contact portion between the base metal film 10a and the semiconductor layer 5.
a and each of the constituent atoms of the semiconductor layer 5 are combined,
In addition, a silicide layer (compound layer) 12 that becomes epitaxial with respect to the semiconductor substrate 1 is formed.

That is, in the semiconductor integrated circuit device according to the first embodiment, since the silicide layer 12 is provided at the contact portion between the base metal film 10a and the semiconductor layer 5, the base metal film 10a and the semiconductor layer 5 are separated from each other. Since the work function difference can be reduced, the contact resistance between the underlying metal film 10a and the semiconductor layer 5 can be reduced.

The base metal film 10a is, for example, 30 atm%.
It is made of TiW containing titanium (Ti) to a degree, and its thickness is, for example, about 150 nm.

However, the amount of Ti in the base metal film 10a is
The amount is not limited to 30 atm%, but can be variously changed, and for example, a range of 15 atm% or more and 60 atm% or less is preferable. This is based on the following research results of the inventor.

That is, for example, when the amount of Ti contained in the base metal film 10a is 15 atm% or less, the epitaxial silicide layer is not sufficiently formed at the contact portion between the base metal film 10a and the semiconductor layer 5, and the base metal film is not formed. The contact resistance between the film 10a and the semiconductor layer 5 was not so low.

On the other hand, when the contact resistance between the underlying metal film 10a and the semiconductor layer 5 is sufficiently reduced, the underlying metal film 10
When a was removed and the silicide layer 12 was analyzed by an X-ray microanalyzer, the molar ratio of Ti and W was
It was about 6 to 4.

Although the composition ratio of Ti and W is slightly different even if the same sputtering target is used due to the difference in the sputtering apparatus and the like, from the above analysis result, if TiW containing Ti of about 60 atm% or less is used, the silicide layer 12 is formed. It has been found that the semiconductor substrate 1 can be made epitaxial.

However, the underlying metal film 10a is not limited to TiW, but can be changed in various ways.
W, TiTa or the like may be used.

The conductor film 10b is made of, for example, Al or Al-.
It is made of Si-copper (Cu) alloy and has a thickness of, for example, 4
It is about 00 nm.

The silicide layer 12 is made of, for example, a compound of Ti, W and Si, and its thickness is, for example, about 3 nm.

Although not shown, a surface protective film is deposited on the wiring 10 and the interlayer insulating film 9. The surface protection film is formed, for example, by stacking an insulating film made of SiO ₂ deposited by a plasma CVD method and an insulating film made of silicon nitride (Si ₃ N ₄ ) also deposited by a plasma CVD method in order from the lower layer. It is configured.

Next, a method of manufacturing the semiconductor integrated circuit device according to the first embodiment will be described with reference to FIGS. In the first embodiment, for simplification of description, the n-channel MO
The description of the manufacturing process part of S is omitted.

First, as shown in FIG. 2, for example, the n ^- type S
The inactive region on the main surface of the semiconductor substrate 1 made of i single crystal is selectively oxidized to form the field insulating film 2 in that region. At this time, at the same time, the n-type channel stopper layer 3 is formed under the field insulating film 2.

Subsequently, on the main surface of the semiconductor substrate 1, the active region whose periphery is defined by the field insulating film 2 is oxidized, and the gate insulating film 6 is formed in that region.

After that, a conductor film made of doped polysilicon and a conductor film made of WSi ₂ are deposited on the semiconductor substrate 1, and then the conductor films are patterned by a photolithography technique to form a gate electrode 7.

Next, using the gate electrode 7 as a mask, the semiconductor substrate 1 is lightly ion-implanted with, for example, p-type impurities such as boron, to form a p-type semiconductor layer 5a.

Then, after depositing an insulating film (not shown) on the semiconductor substrate 1, the insulating film is etched back to form spacers 8 on the sidewalls of the gate electrode 7.

After that, a thin oxide film is formed on the entire surface of the semiconductor substrate 1, and then the semiconductor substrate 1 is ion-implanted with, for example, p-type impurities such as boron by using the gate electrode 7 and the spacer 8 as a mask, and p ⁺ The shaped semiconductor layer 5b is formed. In this way, the pMOS 4 is formed on the semiconductor substrate 1.

Next, as shown in FIG. 3, the semiconductor substrate 1
After depositing an interlayer insulating film 9 made of, for example, SiO ₂ by a CVD method or the like, a connection hole 11 reaching the semiconductor layer 5 is formed in the interlayer insulating film 9 by a photolithography technique.

Subsequently, a metal film 10a ₁ made of TiW for forming the base metal film 10a (see FIG. 1) is deposited on the semiconductor substrate ₁ by a sputtering method or the like.

The amount of Ti in the metal film 10a ₁ at this time is, for example, about 30 atm% for the above reason. The thickness of the metal film 10a ₁ is, for example, about 150 nm.

Thereafter, the semiconductor substrate 1 is housed in an ordinary furnace body (not shown), and annealed at 650 ° C. for 30 minutes in a nitrogen atmosphere, for example, to form TiW of the metal film 10a ₁ and Si of the semiconductor layer 5. And the silicide layer 1 is formed at the contact portion between the metal film 10a ₁ and the semiconductor layer 5 as shown in FIG.
Form 2.

That is, in the first embodiment, the step of depositing the Pt film and the step of removing the Pt film as in the prior art for forming the PtSi film at the contact portion between the base metal film 10a and the semiconductor layer 5 are unnecessary. Therefore, the manufacturing process of the semiconductor integrated circuit device can be reduced and the process can be simplified.

The silicide layer 12 formed by annealing was epitaxial with respect to the semiconductor substrate 1 and was a thin layer having a thickness of about 3 nm. Therefore, the stress on the semiconductor substrate 1 and the semiconductor layer 5 due to the volume change accompanying the chemical reaction when forming the silicide layer 12 can be small, and an increase in junction leak due to the stress is not observed, and the pMOS 4 Showed good electrical characteristics.

Furthermore, by annealing, the resistance of the conductor film 10b (see FIG. 1) becomes lower and the resistance of the wiring 10 can be made lower than in the case where annealing is not performed. This is because the low-reactive Ti oxide or the like is segregated on the surface of the metal film 10a ₁ due to the annealing, and thereafter, the conductor film 10b made of Al and the metal film 10a ₁ deposited on the metal film 10a ₁ are deposited. It is assumed that as a result of suppressing the reaction of 10a _1, the original conductivity of the conductor film 10b made of Al was secured.

However, the annealing temperature is not limited to 650 ° C. and can be changed in various ways, for example, 550 ° C.
℃ ~ 750 ℃, ideally 600 ℃ or more, 70
The range of 0 ° C. or lower is preferable.

FIG. 5 shows the relationship between the contact resistance of the contact portion between the underlying metal film 10a and the semiconductor layer 5 and the annealing temperature.
As shown in FIG. 5, it can be seen that the contact resistance between the underlying metal film 10a and the semiconductor layer 5 significantly decreases at approximately 600 ° C. or higher.

However, according to the research conducted by the present inventor, when the annealing temperature is set to 750 ° C. or higher, nonuniform crystal grains having a diameter of several tens nm are observed in the silicide layer 12. As a result of observing the cross section of the sample in this case with a transmission electron microscope or the like, strong strain is observed in the p ^{+ type} semiconductor layer 5b around the connection hole 11, which causes the p ⁺ semiconductor layer 5 and the semiconductor substrate 1.
It was found that the joint with and was destroyed.

Further, according to the research conducted by the present inventor, the silicide layer of each sample at the annealing temperature of 600 ° C. and 700 ° C. was removed, and the underlying metal film was removed after each annealing treatment. As a result of investigation by a spectroscopy method or the like, it was found that the silicide layer in that case has substantially the same surface state as that of the good silicide layer 12 when the annealing temperature is 650 ° C.

Therefore, it is assumed that the temperature varies depending on the annealing method and the like, and therefore it cannot be specified unconditionally, but if the annealing temperature is at least in the range of, for example, about 600 ° C. to 700 ° C., it is epitaxial with respect to the semiconductor substrate 1. As a result, a good silicide layer 12 is formed.

After the silicide layer 12 is formed by the annealing treatment, for example, Al--Si-- is formed on the metal film 10a _1.
After depositing a conductor film (not shown) made of a Cu alloy, the conductor film and the metal film 10a ₁ are patterned by a photolithography technique to form the wiring 10 shown in FIG.

Thereafter, although not shown, a SiO ₂ film and a Si ₃ N ₄ film are deposited on the wiring 10 and the interlayer insulating film 9 by, for example, the plasma CVD method, and the semiconductor substrate 1
A surface protective film is formed on top.

As described above, according to the first embodiment, the following effects can be obtained.

(1). Base metal film 10a forming the wiring 10
And a silicide layer 12 that is epitaxial with respect to the semiconductor substrate 1 is provided in a contact portion between the semiconductor layer 5 and the semiconductor layer 5 that forms the pMOS 4, thereby reducing the work function difference between the base metal film 10a and the semiconductor layer 5. Therefore, the contact resistance between the underlying metal film 10a and the semiconductor layer 5 can be reduced.

(2). By the above (1), the p ^{+ type} semiconductor layer 5b is formed.
Since the impurity concentration of can be made lower than before,
The short channel effect of pMOS4 can be suppressed, and p
It is possible to promote miniaturization of the MOS4. Therefore, it is possible to improve the degree of element integration of the semiconductor integrated circuit device.

(3). A step of depositing a Pt film as in the prior art in which a PtSi film is formed at the contact portion between the base metal film 10a and the semiconductor layer 5 by forming the silicide layer 12 by annealing, Since the step of removing the Pt film is unnecessary, the number of manufacturing steps of the semiconductor integrated circuit device can be reduced as compared with the case of the related art, and the step can be simplified.

(4). The base metal film 10a is, for example, 15 at
m% or more and 60 atm% or less, ideally 30 atm
% Ti, and the annealing temperature is, for example, 550 ° C. to 750 ° C., ideally 6
By annealing in the range of 00 ° C. or higher and 700 ° C. or lower, for example, the silicide layer 1 that is extremely thin and has a thickness of about 3 nm and is epitaxial with respect to the semiconductor substrate 1.
2 can be formed.

(5) Due to the above (4), the stress to the semiconductor substrate 1 and the semiconductor layer 5 due to the volume change accompanying the chemical reaction when forming the silicide layer 12 is small, and the bonding caused by the stress is small. No increase in leakage was observed, and pMOS4
It is possible to obtain good electrical characteristics in.

[0067]

[Embodiment 2] FIGS. 6 to 10 are cross-sectional views of a main part of a semiconductor substrate during a manufacturing process of a semiconductor integrated circuit device according to another embodiment of the present invention. FIG. 11 is a main part of the manufacturing process of the semiconductor integrated circuit device. FIG. 12 is a graph showing the annealing temperature dependence of the contact resistance between the wiring and the p ^{+ type} semiconductor layer in the contact hole, FIG. 13 is a graph showing the annealing temperature dependence of the junction leakage current, and FIG. a) is a graph showing the forward current-voltage characteristics of the Schottky barrier diode, FIG.
4 (b) is a graph showing the reverse current-voltage characteristics of the Schottky barrier diode, FIG. 15 is a cross-sectional view of the silicide layer after post-annealing observed by SEM, and FIG.
6 is a cross-sectional view of the interface between the annealed base metal film and the semiconductor substrate observed by TEM, FIG. 17 is a graph showing an X-ray diffraction spectrum of the silicide layer, and FIG.
(C) is a graph showing the ESCA spectrum of the silicide layer, and FIG. 19 is an explanatory view showing a model of silicidation of the underlying metal film.

The method of manufacturing the semiconductor integrated circuit device according to the second embodiment includes, for example, a CMOS circuit and a Schottky barrier diode (Shyottoky Barrier Diode) on the same semiconductor substrate.
e: Hereinafter, it is a method for manufacturing a semiconductor integrated circuit device having SBD. Hereinafter, a method of manufacturing the semiconductor integrated circuit device according to the second embodiment will be described with reference to FIGS.

The semiconductor substrate 1 shown in FIG. 6 is a (100) substrate made of, for example, p-type Si single crystal and having a resistivity of 10 Ω · cm.

First, for such a semiconductor substrate 1,
After the field insulating film 2 is formed by the LOCOS method or the like, phosphorus (P), which is an n-type impurity, is ion-implanted into the pMOS formation region P and the SBD formation region S to form the n well 13n. Note that N in FIG. 6 indicates an nMOS formation region.

Then, as shown in FIG. 7, for example, boron (B) which is a p-type impurity is ion-implanted into the nMOS formation region N to form a p-well 13p.

After that, as shown in FIG.
After the formation of the, in the pMOS forming region P, for example boron, into the nMOS forming region N, such as phosphorus is ion-implanted, source, p ⁺ -type semiconductor layer 5c constituting the drain,
5c and n ^{+ type} semiconductor layers 5d and 5d are formed.

Next, as shown in FIG. 9, the semiconductor substrate 1
After the insulating film 14 is formed on the insulating film 14, the p ⁺ semiconductor layer 5c, the n ⁺ semiconductor layer 5d and the SBD formation region S are formed on the insulating film 14.
Connection holes 11a reaching the n-well 13n in
Open ~ 11c.

Then, on the semiconductor substrate 1, for example, TiW
After depositing the underlying metal film 10a made of, it is silicidated. As a result, a silicide layer (compound layer) not shown in FIG. 9 is formed between the underlying metal film 10a and the p ^{+ type} semiconductor layer, the n ^{+ type} semiconductor layer and the n well 13n, as in the first embodiment. It is formed. The silicidation will be described later.

Then, as shown in FIG. 10, for example, Al
CuSi and TiW are sequentially deposited, for example TiW / AlC
The wiring 10 made of uSi / TiW is formed. As a result, in the nMOS formation region N, the n-channel MOS • FET1
5, a pMOS 4 is formed in the pMOS formation region P, and a Schottky barrier diode (SBD) formation region S is formed.
Then, a Schottky barrier diode (SBD) 16 is formed.

FIG. 11 shows a process flow of TiW silicidation of the second embodiment, for example.

After the connection hole 11 (see FIGS. 9 and 10) is formed by a dry etching method or the like (step 101), a wet pretreatment is performed (step 102), and then, for example, TiW is sputtered on the semiconductor substrate 1. Form on top (step 103).

For sputtering, for example, an ordinary DC sputtering device (not shown) is used, and the target is, for example, 10 w.
A t% Ti-W target was used. Then, using a general horizontal furnace body (not shown), for example, in an N ₂ atmosphere, 50
Annealing was performed at 0 to 800 ° C. for 30 minutes (step 104).

Finally, for example, AlCuSi and TiW are
For example, the wiring 10 was formed in order by a sputtering method to form the wiring 10 (steps 105 and 106).

Next, the evaluation items and the evaluation method of the semiconductor integrated circuit device thus formed will be described.

As the electric characteristics, contact resistance, junction leak current and SBD characteristics were measured.

For the contact resistance, a contact hole of about 0.6 μm × 0.6 μm was measured by using, for example, the Kelvin method. For the junction leakage current, a reverse current was measured using a large-area p / n junction of, for example, 35,000 μm ² . SB
For the D characteristic, for example, an SBD having an area of 600 μm ² is manufactured,
The forward and backward characteristics were measured.

In order to clarify the physical phenomenon of silicidation, the cross section of the silicide layer was observed with a scanning electron microscope (SEM) and a transmission electron microscope (TEM).

The TiW / Si interface was analyzed by X-ray photoelectron spectroscopy (ESCA) and X-ray diffraction (XRD).

Next, the electrical characteristics of the semiconductor integrated circuit device based on the evaluation will be described.

FIG. 12 shows the dependency of the contact resistance on the annealing temperature. contact resistance to the p ⁺ -type semiconductor layer (p ⁺ Si), compared to about 600Ω and high without annealing, the resistance is low as a higher annealing temperature, the following values 100Ω is obtained, for example, 650 ° C. or higher. The contact resistance to the n ⁺ -type semiconductor layer (n ⁺ Si) is about 50Ω and sufficiently low even without annealing, little change was observed even when annealed.

FIG. 13 shows the annealing temperature dependence of the junction leakage current. The leakage current is as small as up to about 700 ° C. in both cases of the n ⁺ / p junction and the p ⁺ / n junction without annealing, but it shows a sharp increase after annealing at 750 ° C. or higher.

From the above results, the annealing was performed at about 650 ° C. under which the contact resistance was sufficiently low and the junction leakage current did not increase, and the samples prepared under these conditions were measured.

An example of the measurement result of the SBD characteristic in that case is shown in FIGS. FIG. 14A shows the result of the forward characteristic, and FIG. 14B shows the result of the backward characteristic. SBD
According to the thermionic emission theory, the forward current of is expressed by the following equation (SM Sze, Physics of Semiconducto).
r Devices, 2nd ed. (Wiley, New York, 198
1)).

J = Js [exp (qV / nkT) -1] Js = A * T2 exp (-qφB / kT) where q is elementary charge, k is Boltzmann constant, T is absolute temperature, A * Is valid Richardson (Richa
rdson) constant, φB is the barrier height. n is a correction coefficient from an ideal value, and ideally n = 1.

From FIG. 14A, for example, φB = 0.61e
V, n = 1.03 was obtained. φB = 0.61 eV is Ti
ΦB of Si ₂ = 0.60 eV and φB of WSi ₂ = 0.65 e
It is a value between V (SM Sze, Physics of Semic
onductor Devices, 2nd ed. (Wiley, New York, 1
981)). Further, it can be seen that n = 1.03 is close to the ideal value and has a good SBD characteristic.

Next, FIG. 15 shows a cross-sectional SEM photograph of the connection hole portion annealed at 700 to 800 ° C., for example. After polishing the cross section of the semiconductor substrate, for example, HF: HNO ₃ : CH
_The diffusion layer (n ⁺ semiconductor layer) was etched by immersing it in a ₃ COOH mixed solution and observed.

At 800 ° C., for example, it can be seen that the silicide layer grows beyond the thickness of the diffusion layer, which increases the junction leakage current. On the other hand, for example, at 750 ° C. or lower, no clear formation of the silicide layer is observed.

Further, for example, a cross-sectional TEM photograph of the TiW / Si interface when annealed at 650 ° C. for 30 minutes is shown in FIG.
6 shows. Base metal film 1 composed of semiconductor substrate 1 and TiW
0a, a silicide layer 12 having a thickness of about 4 to 5 nm is formed epitaxially, and the lattice spacing is about 0.
It is 39 nm.

This is 0.391n of WSi ₂ (002).
m (F. d'Heurle, et al., J. Appl. Phys., Vol.
51, p. 5976 (1980), S. Murarka, et a.
l., J. Appl. Phys., Vol. 52, p. 7450 (1
981)) or 0.3 of Ti ₃ W ₂ Si ₁₀ (100)
99 nm (F. Nova, et al., J. Appl. Phys., Vo
l.54, p. 2434 (1983), J. M. Harris, et.
al., J. Electrochem. Soc., Vol. 123, p. 12
0 (1976)).

Next, FIG. 17 shows the XRD spectrum of the silicide layer. For example, after TiW silicidation, TiW on the surface was removed with, for example, H ₂ O ₂ , and measurement was performed using Cu kα.

At 650 ° C., for example, a clear peak due to silicidation is not observed, but at 700 ° C., for example.
A slight peak of (Ti _1-X W _X ) Si ₂ is observed at 2θ = 22 ° in ° C. Furthermore, for example, at 750 ° C. or higher intense peak (Ti _1-X W _X) Si _2, WSi ₂ was observed, a thick (Ti _1-X W _X) that a mixed crystal of Si ₂ and WSi ₂ are formed I understand.

Next, the ESCA spectrum of the surface of the semiconductor substrate after removing TiW with, for example, H ₂ O ₂ is shown in FIG.
It shows in (a)-(c). For example, for an annealing temperature of 500 ° C. to 750 ° C., for example, Si (2p), Ti
The change of the spectrum of (2p) and W (4f) is shown.

First, paying attention to the spectrum of Si (2p) in FIG. 18A, the Si (metal) peak and the Si (metal) peak
For example, the binding energy difference (chemical shift) from the (oxide) peak is 4.40 eV at 550 ° C. or lower, whereas it is 4.24 eV at 600 ° C. or higher, and 0.16.
eV is getting smaller. This result shows that, for example, silicide was generated at 600 ° C. or higher.

In addition, Ti (2p) in FIGS.
And W (4f) spectrum, for example, 550 ° C
Until now, only the peak of oxide is observed, but at 600 ° C or higher, for example, metal and oxide are observed.
The peak of e is observed. This suggests that a silicide layer of Ti and W is formed at 600 ° C. or higher, for example. The oxide peak was observed not only because it was oxidized in air but also because it was oxidized by removing TiW with H ₂ O ₂ .

Next, FIG. 19 shows a model of TiW silicidation, for example. After the base metal film 10a made of TiW is formed on the semiconductor substrate 1, the silicide layer 12 is formed between the base metal film 10a and the semiconductor substrate 1 by annealing, for example, at a temperature of 600 ° C. or higher.

From the results of TEM and ESCA, for example, 60
In the range of 0 to 700 ° C, a ternary alloy of Ti, W and Si (T
It was found that i _1-X W _X ) Si ₂ was formed epitaxially. The formation of the silicide layer 12 reduces the contact resistance.

S. E. Babcock et al., 500-900 ° C.
In the case of annealing, when Ti-rich TiW is used, TiW
25nm TiSi ₂ is formed at the Si / Si interface.
In the case of rich TiW, it is thick at 750 ° C or higher (Ti
_It has been reported that only _1-X W _X ) Si ₂ or WSi ₂ is formed (SE Babcock, et al., J. Appl.
Phys., Vol. 53, p. 6898 (1982), S.
E. Babcock, et al., J. Appl. Phys., Vol. 59,
p. 1599 (1986)).

This is because their analysis method is XRD and RBS.
Therefore, it is very thin (about 4 nm) (Ti
_{This is} probably because the _1-X W _X ) Si ₂ silicide layer could not be observed. Onishi et al. Reported that TiSi ₂ was formed at the TiW / Si interface by TiW lamp annealing (RTA) (Shigeo Onishi, et al., 2nd symposium of ECS Japan Chapter, “Al wiring in ULSI”). Problems concerning Technology >> p. 50 (1989)).

Further, in annealing at 750 ° C. or higher, the silicide layer is made of polycrystalline (Ti _1-X Wx) Si ₂ and WSi.
It becomes a mixed crystal of ₂ and the film thickens rapidly. Then, this thick silicide layer 17 penetrates through the diffusion layer, causing an increase in junction leak current.

A difference in silicidation due to annealing of TiW / Si and W / Si has already been reported (M.
Suzuki, et al., 1991 SSDM p. 213 (1
991)), as described above, an epitaxial layer of (Ti _1-x W _x ) Si ₂ is formed in TiW / Si, whereas epitaxial growth does not occur in W / Si, and polycrystalline WSi
_{Since 2} is formed, a junction leak occurs at a low temperature,
The process window becomes narrow. That is, TiW silicidation is a process suitable for fine ULSI as compared with W.

As described above, according to the second embodiment, the silicidation of TiW deposited on the semiconductor substrate 1 makes it possible to simultaneously obtain a low contact resistance and a good SBD characteristic.

As a result, for example, the connection hole 11b of 0.6 μm is formed.
In the case of p ^{+ type} semiconductor layer 5c,
It is possible to obtain a contact resistance as low as 0Ω or less. Also, for example, SB with barrier height φB = 0.61 eV
It becomes possible to obtain D.

Particularly, during the TiW silicidation, for example, by annealing at 600 to 700 ° C., TiW /
The ternary alloy (Ti _1-X W _X ) Si ₂ is epitaxially formed at the Si interface, which makes it possible to reduce the contact resistance and obtain good SBD characteristics.

Further, by forming the silicide layer 12 by annealing, a Pt film as in the case of the prior art in which the PtSi film is formed at the contact portion between the base metal film 10a and the semiconductor layer is formed as in the first embodiment. Since the step of depositing and the step of removing the Pt film are unnecessary, the number of manufacturing steps of the semiconductor integrated circuit device can be reduced as compared with the case of the conventional technique.
The process can be simplified.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above-mentioned Embodiments 1 and 2, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

For example, in the first and second embodiments, the case where the wiring is formed by laminating the conductor film made of Al or the like on the base metal film made of TiW has been described. However, the present invention is not limited to this. , For example, Ti as a base metal film
Mo, TiTa, ZrW, ZrMo, ZrTa, Hf
You may use W, HfMo, and HfTa. This is IV
Since Ti, Zr, and Hf of the a group can reduce SiO ₂ at the metal / Si interface, they function to cause the interfacial reaction uniformly, and T
The a, W, and Mo have a slower rate of silicidation than the group IVa metal and form only a thin silicide layer. And
This is because the silicide layer is thin and can exist stably on Si even if the lattice strain is large.

Further, for example, the wiring may be formed by laminating a W film on the base metal film. In these cases, after patterning the wiring, annealing for forming a silicide layer may be performed.

In the first and second embodiments, the case where the annealing for forming the silicide layer is performed in the furnace has been described, but the present invention is not limited to this. For example, the lamp ranier method is used. Is also good. At the time of lamp annealing, the atmosphere in the processing chamber is, for example, a nitrogen atmosphere or an ammonia atmosphere.

When lamp annealing is used, the annealing time can be shortened to about 1 minute. In this case, a thin silicide layer was formed even if annealing was performed at, for example, 750 ° C., and no increase in junction leak was observed.

When a nitrogen atmosphere was used for the lamp anneal, oxidation T was formed on the surface of the underlying metal film made of TiW or the like.
Since i is deposited, the wiring resistance can be reduced as compared with the case where no annealing is performed.

When lamp annealing is performed in an ammonia atmosphere, TiN, tungsten nitride, or the like is formed on the surface of the underlying metal film made of TiW or the like, and a conductor film made of Al is formed as compared with the case of annealing in a nitrogen atmosphere. It was possible to lower the reactivity and to reduce the wiring resistance.

In the above description, the CMO, which is the field of application of the invention mainly made by the present inventor, was the background.
The case where the present invention is applied to the semiconductor integrated circuit device configured by the S circuit has been described, but the present invention is not limited to this and various applications are possible. For example, a semiconductor integrated circuit device configured by a bipolar transistor or BiC-MOS (Bipola).
It can also be applied to other semiconductor integrated circuit devices such as a semiconductor integrated circuit device configured by r CMOS).

[0119]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
It is as follows.

(1). That is, according to the invention described in claim 1, for example, the work function difference between the underlying metal film forming the wiring and the p-type semiconductor layer of the semiconductor substrate can be reduced, so that the wiring can be reduced. The contact resistance between the p-type semiconductor layer and the p-type semiconductor layer can be reduced. Therefore, for example, the impurity concentration of the p-type semiconductor layer forming the source / drain region of the pMOS can be reduced, so that the short channel effect of the pMOS can be suppressed and the miniaturization of the pMOS can be promoted. Therefore, the degree of element integration of the semiconductor integrated circuit device can be improved.

(2) According to the invention described in claim 4, for example, the step of depositing the Pt film, the step of removing the Pt film, and the like are not necessary, so that the number of manufacturing steps of the semiconductor integrated circuit device can be reduced. In addition, the process can be simplified. That is, it is possible to reduce the contact resistance between the wiring and the semiconductor substrate without increasing or complicating the manufacturing process of the semiconductor integrated circuit device.

[Brief description of drawings]

FIG. 1 is a sectional view of an essential part of a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view of essential parts in a manufacturing process of the semiconductor integrated circuit device of FIG.

3 is a cross-sectional view of essential parts in a manufacturing process of the semiconductor integrated circuit device of FIG.

4 is a cross-sectional view of essential parts in a manufacturing process of the semiconductor integrated circuit device of FIG.

FIG. 5 is a graph showing a relationship between a contact resistance between wiring and a semiconductor substrate and an annealing temperature.

FIG. 6 is a fragmentary cross-sectional view of a semiconductor substrate during a manufacturing process of a semiconductor integrated circuit device which is another embodiment of the present invention.

7 is a fragmentary cross-sectional view of the semiconductor substrate during a manufacturing step of the semiconductor integrated circuit device, following FIG. 6;

8 is a fragmentary cross-sectional view of the semiconductor substrate during a manufacturing step of the semiconductor integrated circuit device, following FIG. 7;

9 is a fragmentary cross-sectional view of the semiconductor substrate during a manufacturing step of the semiconductor integrated circuit device, following FIG. 8;

10 is a fragmentary cross-sectional view of the semiconductor substrate during a manufacturing step of the semiconductor integrated circuit device, following FIG. 9;

FIG. 11 is a process drawing of a main part of a manufacturing process of a semiconductor integrated circuit device.

FIG. 12 is a graph showing the annealing temperature dependence of the contact resistance between the wiring and the p ^{+ type} semiconductor layer in the connection hole.

FIG. 13 is a graph showing the annealing temperature dependence of junction leakage current.

FIG. 14A is a graph showing a forward current-voltage characteristic of the Schottky barrier diode, and FIG. 14B is a graph showing a reverse current-voltage characteristic of the Schottky barrier diode.

FIG. 15 is a cross-sectional view of a silicide layer after annealing observed by SEM.

FIG. 16 is a cross-sectional view of an interface between a base metal film after annealing and a semiconductor substrate observed by TEM.

FIG. 17 is a graph showing an X-ray diffraction spectrum of a silicide layer.

18A to 18C are ESCA of a silicide layer.
It is a graph which shows a spectrum.

FIG. 19 is an explanatory diagram showing a silicidation model of a base metal film.

[Explanation of symbols]

1 semiconductor substrate 2 field insulating film 3 channel stopper layer 4 p channel MOS • FET 5 semiconductor layer 5a p-type semiconductor layer 5b p ^{+ type} semiconductor layer 5c p ^{+ type} semiconductor layer 5d n ^{+ type} semiconductor layer 6 gate insulating film 7 gate electrode 7a conductor film 7b conductor film 8 spacer 9 interlayer insulating film 10 wiring 10a underlying metal film 10a ₁ metal film 10b conductor film 11 connection hole 11a connection hole 11b connection hole 11c connection hole 12 silicide layer (compound layer) 13n n well 13p p well 14 Insulating Film 15 n-Channel MOS • FET 16 Schottky Barrier Diode 17 Silicide Layer P pMOS Forming Area N nMOS Forming Area S Schottky Barrier Diode Forming Area

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical indication location H01L 29/46 R 9055-4M 21/336 29/784 (72) Inventor Yasushi Oka Kodaira, Tokyo 5-22-1 Jousuihonmachi, Hitachi Microcomputer System Co., Ltd. (72) Inventor Yasuko Yoshida 5-20-1 Josuihoncho, Kodaira-shi, Tokyo Hitachi Ltd. Musashi Factory (72) Inventor Haruta Ryo 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Inside the Musashi Factory, Hitachi Ltd.

Claims (5)

[Claims] 1. A wiring is formed by laminating a base metal film and a conductor film in order from the lower layer on an insulating film on a semiconductor substrate, and at the contact portion between the base metal film and the semiconductor substrate,
A semiconductor integrated circuit device, comprising a compound layer formed by combining respective constituent atoms of a base metal film and a semiconductor substrate and being epitaxial with respect to the semiconductor substrate. 2. The semiconductor integrated circuit device according to claim 1, wherein the underlying metal film is titanium tungsten. 3. The semiconductor according to claim 1, wherein the contact portion is formed in a semiconductor layer for forming a source / drain of a MIS • FET or a semiconductor layer for forming a Schottky contact of a Schottky barrier diode. Integrated circuit device. 4. A step of forming a connection hole reaching the semiconductor substrate in an insulating film on the semiconductor substrate, and a step of depositing a base metal film for forming wiring on the insulating film in which the connection hole is formed.
Annealing is performed on the semiconductor substrate, and the constituent atoms of the base metal film and the semiconductor substrate are combined at the contact portion between the base metal film and the semiconductor substrate to form a compound layer that becomes epitaxial with respect to the semiconductor substrate. And a step of electrically connecting the base metal film and the semiconductor substrate to each other, the method for manufacturing a semiconductor integrated circuit device. 5. The semiconductor integrated circuit device according to claim 4, wherein a Schottky contact portion is formed at a contact portion between the compound layer and the semiconductor substrate at the same time when the base metal film and the semiconductor substrate are connected. Production method.