JPH07111711B2 - Processing end interrupt control system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] A processing end interrupt control system for notifying other computer systems of execution results for shared resources of a plurality of computer systems, the execution results of which are designated after execution of a command for shared resources. It stores the control information necessary for the device used as a shared resource to execute and the interrupt control information related to the computer system that should be notified when the device finishes executing, for the purpose of notifying the computer system A command word is provided, the computer system stores predetermined control information in this command word, requests the device to be used as the shared resource for processing, and stores it in this command word after this device finishes processing. Interrupted notification to the computer system specified based on the interrupt control information Be configured so that.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processing end interrupt control system that notifies other computer systems of execution results for shared resources of a plurality of computer systems.

[Prior Art] Conventionally, a device used as a shared resource of a plurality of computer systems executes this process only for the computer system of the starting source after executing the process corresponding to the command instructed by the computer system of the starting source. The end result was notified.

[Problems to be Solved by the Invention] Therefore, even if shared memory and shared DASD are shared by each computer system as a quasi-main memory of the computer system and distributed processing and a simple communication function are realized, these devices can be used. However, there is a problem in that after the command execution is completed, asynchronous notification cannot be promptly made to another computer system, for example, a specified computer system, by an interrupt or the like.

In order to solve these problems, the present invention aims at promptly asynchronously notifying the execution result to a designated computer system after executing a command for a shared resource.

[Means for solving problems]

Means for solving the problem will be described with reference to FIG.

In FIG. 1, command word 1 is a shared resource.
It stores control information for CM (shared memory) 5-1, 5-2 and information such as a notification destination by an interrupt after execution of processing.

MSs (main memory devices) 2-1 to 2-4 are for CPUs (processors) 3-1 to 3-4, respectively, and read and write data and the like.

CMA (shared memory controller) 4-1 and 4-2 are CM5-
The control for 1, 5-2, for example, data transfer control is performed.

CMs 5-1 and 5-2 are shared memories which are shared resources.

[Action]

The present invention, as shown in FIG. 1, includes CPUs 3-1 to 3-4.
Was started based on the command (for example, read / write command) stored in the command word 1 by any of the
After the CMAs 4-1 and 4-2 have finished executing the process corresponding to the command, the instructed notification destination is notified of the completion of the process by an interrupt.

Therefore, for example, MS2-1 to 2-4 to CM5-1, 5
After transferring the data to -2, it becomes possible to notify the designated CPUs 3-1 to 3-4 that the processing is completed by an interrupt. The CPUs 3-1 to 3-4 that have received the notification execute predetermined processing in response to this interrupt.

〔Example〕

Next, the configuration and operation of one embodiment of the present invention will be described in detail with reference to FIGS.

First, the command word 1 in FIG. 1B will be described in detail.

When the command "WRT" in this command word 1 is "1"
Indicates that data is transferred from MS2-1 to 2-4 to CM5-1 and 5-2. When "WRT" is "0", CM5-
1, 5-2 indicates that data is transferred to MS2-1 to MS2-4.

If "iNT0" is "1", the command (CMA4−
CPU 3-1 to 3-4 of the activation source that activated 1, 4-2)
Of the interrupt signal to the CPUs 3-1 to 3-4.

When "iNT1" is "1", it means that after the command execution is completed, the interrupt signal is notified to the CPUs 3-1 to 3-4 of the other system (the CPU designated by the address of the interrupt destination).

If "iNT2" is "1", all CPU3-
This means notifying an interrupt signal to 1 to 3-4.

The "INT code" is for executing the process specified by this code when an interrupt occurs due to the notification of the interrupt signal.

“BC” (byte count) represents the length of data to be transferred.

The "shared memory address" is the CM5-1 that transfers the data,
5-2 represents the address.

"Data address (main memory)" is the data transfer MS2-
It represents an address of 1 to 2-4.

The command word (CMACW) 1 with the above configuration is used by the CPU3
-1 to 3-4 stores in MS2-1 to 2-4. When the CMAs 4-1 and 4-2 are activated, the activated CMAs 4-1 and 4-2 read the command word 1 and store the control information (for example, read information) and the address information (shared). Data transfer corresponding to memory address, Data address) and BC (number of data transfer bytes) is executed. After this data transfer is completed, iNT0
Through iNT2, and CPUs 3-1 through 3-4 designated by the interrupt destination address, etc., are notified of interrupt signals to execute interrupt processing. This allows CM5-
After transferring and storing the predetermined data to 1, 5-2, it notifies the desired CPU 3-1 to 3-3 to transfer the data such as distributed processing, and between each CPU 3-1 to 3-4. Sequence control by using the shared memory.
It becomes possible to communicate between the CPUs 3-1 to 3-3.

Next, the configuration and operation of a concrete circuit example of the CMAs 4-1 and 4-2 shown in FIG. 2 will be sequentially described in detail.

First, referring to FIG. 3 and FIG. 4, the upper device (CPU) is C
The activation process for MA will be described.

In FIG. 3 (A), the figure shows a state in which a command word is prepared in the main memory. This means that the host device prepares the CMACW shown in FIG.

The figure shows the state in which the host device reads the AST (adapter status register) of the CMA. This means reading the contents of the AST shown in FIG.

In the figure, as a result of reading in the figure, ABSY (adapter
A state for determining whether or not it is busy) is shown. this is,
It means that the CMA is busy, that is, whether or not the activation from the host device can be accepted. If YES (if busy), repeat in the figure. NO
In the case of, execute in the figure.

In the figure, STKFL (Stack S
Indicates the state to determine whether TK is full). This means determining whether the STK (stack) is full. In the case of YES, the steps in the figure are repeated. If NO, execute in the figure.

The figure shows the state in which the identification number is written to STKR (stack register). This means that, as shown in FIG. 4 (a), the corresponding identification number, eg, "0", of the start addresses of the plurality of CMACWs is written to STKR.

The figure shows the state in which the address storing the command word (CMACW) is set in CAR (command address register). At this point, ABSY of AST turns ON.

The above startup process is executed by the higher-level device (CPU).

In Fig. 3 (b), the CMA micro is IDL in the figure.
Indicates the state in which the writing of data to CAR is detected by the E routine (idle routine). This is detected depending on whether the flag in CAR is "1".

In the figure, the state of writing STKR and CAR values to STK (stack) is shown.

The figure shows the state in which ABSY of AST is turned off.

By the procedure described above or in the figure, information such as the start address of the CMACW prepared by the higher-level device on the main storage device (information shown in FIG. 4B) is sequentially stored in the STK of the CMA, and the startup process is performed. Will be executed.

Next, the procedure for executing the process based on the information stored in the STK of the CMA will be described in detail with reference to FIGS.

In FIG. 5, the figure shows a state in which it is detected by the IDLE routine that a command is entered in STK. This is ST
W-ADR that stores the address to write information to K
And RA that stores the address to read information from STK
Detects whether there is a difference between the addresses stored in DR and. For example, in the figure W-ADR is "02" and R-ADR is "0".
In the case where "0" is stored, the difference is "2", so it is detected that two sets of information are included.

In the figure, the command address part of the STK buffer is set to MAR (memory address register).
This means that of the information shown in FIG. 4 (b) stored in the STK, the CMACW start address is stored in the MAR.

The figure shows the state in which the number of read bytes is set in the BC register. This means that the number of bytes for reading the CMACW shown in FIG. 1 (b) stored in the main memory is set, for example, a fixed length of 32 bytes.

The figure shows a state in which a transfer request is sent to a higher-level device (CPU).

The figure shows a state in which it is determined whether or not the transfer is permitted. YES
In the case of (when the data bus can be acquired), the procedure in the figure is executed. If NO, wait until transfer is permitted.

The figure shows a state in which data from a higher-level device is stored in an SDB (self-data buffer). This means that the command word (CMACW) is fetched into the SDB in the CMA.

The figure shows a state in which it is determined whether or not the transfer is completed. YES
In the case of, execute in the figure. If NO, repeat the process until the transfer is completed.

In the figure, the data address and byte count stored in SDB are loaded into MAR and BC, respectively. This loads the address on the main memory where the data in CMACW fetched in SDB is stored into MAR,
This means loading the byte length of the data to be transferred into the BC register. As a result, the preparation for transferring the data is completed.

The figure shows a state in which the hardware transfer circuit is activated. This means activating the flowchart of FIG.

By the above procedure, CMACW read from main memory
The data address stored in it and the number of bytes to be transferred are set in MAR and BC, and the preparation for data transfer by hardware is completed.

The procedure of data transfer will be described with reference to FIG.

In FIG. 6, the figure shows a state in which it is determined whether or not BC = 0. In the case of YES, the command in the drawing is notified to the micro that the command has been completed (data has been transferred from the main memory to the shared memory, for example). In the case of NO, the process shown in the figure is executed to transfer the data.

The figure shows a state in which a transfer request is made to the host device.

The figure shows a state in which it is determined whether or not the transfer is permitted. YES
In the case of (when the data bus can be acquired), the procedure in the figure is executed. If NO, repeat transfer permission is requested.

The figure shows a state in which data from a higher-level device is stored in the SDB.

The figure shows a state in which it is determined whether or not the transfer is completed. YES
In the case of, execute in the figure. In the case of NO, it is repeatedly executed until the series of transfer is completed.

The figure shows the state in which BC and MAR are updated.

In the figure, CMDB (common memory buffer register) is sequentially set with SDB data, and CM (shared memory)
Shows the state of writing to.

The figure shows a state in which it is determined whether or not writing has ended. YE
In the case of S, execute in the figure. In the case of NO, the process in the figure is repeated.

By the above procedure, the data in the main memory is written in the shared memory.

Next, using FIG. 7 to FIG. 9, the data transfer from the main memory device (MS2-1 to 2-4) to the shared memory (CM5-1, 5-2) is completed in the manner described above. After that, the procedure for executing the notification of the end of data transfer to the higher-level device described in the command word (CMACW) by an interrupt will be described in detail.

In FIG. 8, the figure shows a state in which it is determined whether or not the transfer is completed. This means that the end of transfer is detected by the IDLE routine. The figure shows the state of reading the interrupt control information of the SDB. This is the interrupt notification information in CMACW stored in the SDB corresponding to the data that has been transferred (Fig. 1 (b) iNT0, iNT
1, and iNT2 etc.) are meant to be read.

The figure shows a state in which it is determined whether or not iNT0 is "1". In the case of YES (when notifying the own system of the interrupt), the processing (1) in the figure notifies the own system (the activation source of the CMA) that the data transfer process has ended by the interrupt.

In the figure, the identification number of the command executed in ICR (instruction code register) #A and OIVLD
Indicates that the bit of is set to "0". Since this is determined to be an interrupt notification to the own system in the figure,
In order to generate this interrupt, the control information shown in FIG. 9 is set to the corresponding control information.

The figure shows a state in which the AiNT bit of AST # A is turned on "1". This means that, as shown in FIG. 7, this AiNT bit is turned on and an interrupt request signal is sent to the host device.

The figure shows a state in which it is determined whether or not AiNTP is "1". This means that, as shown in FIG. 7, it is determined by AiNTP of AST # A whether or not AiNT is accepted in response to the interrupt signal in the figure and the processing is started. After AiNTP becomes "1" (process start), when AiNTP becomes "0" (process end) in the figure, the process ends.

When iNT1 is determined to be "1" in the figure (when notifying to other system by interrupt), the corresponding upper device (CPU) of the other system is interrupted by the process (2) shown in or in the figure. Notify by.

In the figure, the OiVLD bit of ICR # B is set to "1", the interrupt code and the interrupt source address are set. This is “1” in the corresponding OiVLD bit in the ICR shown in FIG.
This means storing the interrupt code and the interrupt source address.

The figure shows a state in which the AiNT bit of AST # B is turned on. Then, in the same manner as in the figure, the higher order device of the other system is notified by an interrupt.

If iNT2 is determined to be "1" in the figure, process (1) in the diagram and process (2) in the diagram are sequentially executed to interrupt the host system of its own system and other systems. Notifies that the transfer process is completed.

Furthermore, in the case of another system interface in the figure,
OINT (other interrupt register) and OINRV
Use the (other interrupt receive register) to communicate the interrupt information (information shown in Fig. 1 (b)) to the interface of the other system, and notify the relevant host device by the interrupt in the same manner as described above. To

The ODR (other data register) and IFB (interface buffer) shown in FIG. 2 are used for communication with other systems. In addition, CSA (CS address register), CS, OP
(Operation register), GR (Work register)
Is for executing the above-mentioned various processes using a micro.

〔The invention's effect〕

As described above, according to the present invention, after the processing is completed in the command word, the notification destination information for notifying the fact is stored and the processing request is made, so that the data of the distributed processing etc. It is possible to easily transfer the data, and it is possible to perform sequence control between the CPUs, which are the respective host devices. Further, it is possible to have a communication function.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is an example of the circuit of the present invention, FIG. 3 is a flowchart of a startup process for a CMA from a host device, and FIG. 4 is an example of a startup process for a CMA from a host device. Figure 5 shows the CMA execution flow chart (micro processing), Figure 6 shows the CMA execution flow chart (hardware processing), Figure 7 shows the AST content example, Figure 8 shows the interrupt processing flow chart, and Figure 9 shows the ICR content example. Indicates. In the figure, 1 is a command word (CMACW), 2-1 to 2
-4 is an MS (main memory), 3-1 to 3-4 are CPUs,
4-1 and 4-2 are CMA (shared memory control device), 5-
Reference numerals 1 and 5-2 represent CMs (shared memory).

Claims (2)

[Claims] 1. A processing end control system for notifying a computer system of the processing end of a device used as a shared resource of a plurality of computer systems by an interrupt, wherein the device used as the shared resource executes reading and writing of data. Command word (1) for storing control information for controlling and interrupt control information regarding a computer system for notifying that the device used as the shared resource has finished reading and writing data. A computer system provided with a means, and a computer system receiving a processing request storing the control information in the command word (1) from a certain computer system, and when the processing is completed, the allocation stored in the command word (1) is completed. Used as a shared resource by notifying the computer system specified by the embedded control information that it has finished Processing end interrupt control system characterized by comprising a device. 2. A device used as the shared resource has at least a shared memory and a shared memory control device for writing / reading data to / from the shared memory. Is notified to the computer system designated by the command word (1) by an interrupt, The processing end interrupt control system according to claim (1).