JPH07110794A - Transmission/reception simultaneous control interface circuit for bus between processors - Google Patents

Abstract

PURPOSE:To simultaneously transmit and receive data from two buses. CONSTITUTION:A data transmission part 30 is provided with a transmission bus selecting circuit 31 for selecting a second bus 12 when a data reception part 40 receives reception data from a first bus 11 through a first interface circuit 21 and selecting the first bus 11 when the data reception part 40 receives the reception data from the second bus 12 through a second interface circuit 22. Also, the data reception part 40 is provided with a reception bus selecting circuit 41 for selecting the second bus 12 when the data transmission part 30 outputs transmission data through the first interface circuit 21 to the first bus 11 and selecting the first bus 11 when the data transmission part 30 outputs the transmission data through the second interface circuit 22 to the second bus 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transmission / reception simultaneous control interface circuit for interprocessor buses, and more particularly to a processor used in a multiprocessor system in which a plurality of processors are connected to each other by two buses for data transfer. The present invention relates to a transmission / reception simultaneous control interface circuit for an inter-bus.

[0002]

2. Description of the Related Art FIG. 2 is a block diagram showing a conventional example of a bus interface circuit used in a multiprocessor system in which a plurality of processors are connected to each other by two buses for data transfer.

The bus interface circuit 110 is provided between the processor 100 and the two buses (the first bus 101 and the second bus 102).
A first interface circuit 111 connected to 101,
A second interface circuit 112 connected to the second bus 102; a first interface circuit 111;
Of the interface circuit 112, the contention adjustment circuit 113 for adjusting the contention of transmission and reception, the memory control circuit 114 connected to the contention adjustment circuit 113, and the processor 100 connected to the memory control circuit 114.
A gate circuit 115 connected to each other and a gate circuit 115
And a memory 116 connected to each other.

Here, the first bus 101 and the second bus
Reference numeral 102 is for connecting the processor 100 and a plurality of other processors to each other to perform data transfer. The memory control circuit 114 is connected to the first bus 101.
Or for controlling writing of received data sent from another processor via the second bus 102 and reading of transmitted data sent to another processor via the first bus 101 or the second bus 102. belongs to. The gate circuit 115 writes and reads transmission data sent from the processor 100, and the memory control circuit 11
It is for controlling the writing and reading of the received data sent from 4. The memory 116 is for storing transmission data and reception data.

[0005]

However, in the above-mentioned bus interface circuit 110, for example, the first interface
When the bus 101 of the other side becomes the transmission state or the reception state, the memory control circuit 114, the gate circuit 115, and the memory 11
Since 6 and 6 are occupied by the first bus 101, there is a problem that data transmission or reception cannot be performed simultaneously using the second bus 102. Such a problem similarly occurs when the second bus 102 enters the transmitting state or the receiving state.

In order to eliminate the congestion state occurring in the inter-processor communication control device without deteriorating the economical efficiency of the multiprocessor system, the congestion detection means for detecting the congestion state of the communication between the processors and the congestion detection means. When the means detects a congestion state, it activates the inter-processor communication control unit that is on standby as a standby system and makes it available for inter-processor communication in parallel with the inter-processor communication control unit that is being used as the active system. An inter-processor communication control system provided with a system starting means is proposed in Japanese Patent Application Laid-Open No. 1-185760. This inter-processor communication control system is
It is not possible for a single inter-processor communication control device to simultaneously send and receive data.

An object of the present invention is to provide a transmission / reception simultaneous control interface circuit for an inter-processor bus, which is capable of transmitting / receiving data simultaneously from two buses.

[0008]

In the transmission / reception simultaneous control interface circuit for an inter-processor bus according to the present invention, the first processor and the second processor are mutually connected by a first bus and a second bus for data transfer. And a transmission / reception simultaneous control interface circuit for an inter-processor bus, which is used in a multiprocessor system, comprising: a first interface circuit connected to the first bus; and a second interface circuit connected to the second bus. Interface circuit, the first processor and the first and second
The first circuit provided between the first interface circuit and the first interface circuit.
A transmission data transmitted from the processor of the above to the first bus via the first interface circuit or to the first bus via the second interface circuit; A second interface circuit from the first bus via the first interface circuit or from the second bus provided between a first processor and the first and second interface circuits. And a data receiving unit for outputting received data sent via the first processor to the first processor, wherein the data transmitting unit includes the first data receiving unit.
The second bus is selected when the reception data is being received from the second bus via the first interface circuit, while the data receiving unit selects the second interface circuit from the second bus. A transmission bus selection circuit that selects the first bus when the reception data is being received via the data reception unit, and the data reception unit includes the first data transmission unit via the first interface circuit; When the transmission data is being output to the second bus, the second bus is selected, while the data transmission unit outputs the transmission data to the second bus via the second interface circuit. It is characterized in that it has a reception bus selection circuit for selecting the first bus when it is present.

Here, the data transmission unit controls a transmission memory in which the transmission data is stored, writing of the transmission data to the transmission memory, and reading of the transmission data from the transmission memory. The data receiving unit further includes a transmission memory control unit, the data reception unit stores the reception data, the reception data is written to the reception memory, and the reception data is received from the reception memory. It may further have a receiving memory control means for controlling the reading of the.

[0010]

In the transmission / reception simultaneous control interface circuit for the inter-processor bus according to the present invention, the data transmission unit is configured to operate when the data reception unit receives the reception data from the first bus via the first interface circuit. And a transmission bus selection circuit that selects the first bus when the data receiving unit receives the received data from the second bus via the second interface circuit. The receiving unit selects the second bus when the data transmitting unit outputs the transmission data to the first bus via the first interface circuit, while the data transmitting unit selects the second bus via the second interface circuit. By including a reception bus selection circuit that selects the first bus when the transmission data is being output to the second bus, the data transmission unit and the data reception unit have the same structure. Ri the first bus and the second bus may be exclusively selected.

[0011]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing a bus interface circuit which is an embodiment of a transmission / reception simultaneous control interface circuit for an interprocessor bus according to the present invention.

The bus interface circuit 20 is provided between the processor 10 and the two buses (the first bus 11 and the second bus 12) and is connected to the first bus 11. 1 interface circuit 21,
The second interface circuit 22 connected to the second bus 12, the data transmission unit 30 provided between the processor 10 and the first and second interface circuits 21 and 22, and the processor 10 and the first and second The data receiving section 40 is provided between the second interface circuits 21 and 22. The configurations of the data transmitter 30 and the data receiver 40 will be described in detail below.

(1) Data Transmission Unit 30 The data transmission unit 30 includes a transmission bus selection circuit 31, a transmission memory control circuit 32, and a transmission unit gate circuit 33.
And a transmission memory 34. Here, the transmission bus selection circuit 31 selects the second bus 12 when the data receiving unit 40 is receiving the reception data from the first bus 11 via the first interface circuit 21, while This is for selecting the first bus 11 when the receiving unit 40 is receiving the received data from the second bus 12 via the second interface circuit 22. The transmission memory control circuit 32 is for reading transmission data from the transmission memory 34 via the transmission unit gate circuit 33. The transmitter gate circuit 33 includes the processor 1
It is for writing the transmission data from 0 to the transmission memory 34. The transmission memory 34 is for storing the transmission data transmitted from the processor 10.

(2) Data Receiver 40 The data receiver 40 includes a reception bus selection circuit 41, a reception memory control circuit 42, and a reception gate circuit 43.
And a receiving memory 44. Here, the reception bus selection circuit 41 selects the second bus 12 when the data transmission unit 30 is outputting transmission data to the first bus 11 via the first interface circuit 21, while the data transmission unit 30 selects the data. This is for selecting the first bus 11 when the transmission unit 30 is outputting transmission data to the second bus 12 via the second interface circuit 22. The reception memory control circuit 42 includes the first bus 11 or the second bus 11.
Received data sent from another processor via the bus 12 of
4 for writing. Receiver gate circuit 43
Is for reading the reception data from the reception memory 44 and sending it to the processor 10.

Next, the operation of the bus interface circuit 20 will be described.

When the processor 10 is not in the receiving state,
When the transmission data is transmitted from the processor 10 to another processor, the transmission data is the processor 10
Is written in the transmission memory 34 via the transmitter gate circuit 33. This activates the transmission of the bus interface circuit 20. When the transmission is activated, the usable one of the first bus 11 and the second bus 12 is captured by the transmission bus selection circuit 31. At this time, the first bus 11 is assumed to be captured. Then, after the transmission data is read from the transmission memory 34 by the transmission memory control circuit 33, the first interface circuit 21 and the captured first bus 1 are transmitted.
1 to the other processor of the transmission destination.

During the transmission of such transmission data, when the reception data is transmitted from the other processor to the processor 10 via the second bus 12 which is not used for the transmission, the reception bus is selected. The circuit 41 selects the second bus 12 and the received data sent from the second interface circuit 22 to the reception bus selection circuit 41 is
It is written in the reception memory 44 by the reception memory control circuit 42 via the reception section gate circuit 43.
Thereafter, the received data is sent to the processor 10 via the receiver gate circuit 43.

On the other hand, when the received data is first transmitted from the other processor to the processor 10 via the first bus 11, the first bus 11 from which the received data is transmitted is received. It is captured by the bus selection circuit 41. As a result, the reception data sent from the first interface circuit 21 to the reception bus selection circuit 41 is
It is written in the reception memory 44 by the reception memory control circuit 42 via the reception section gate circuit 43.
Thereafter, the received data is sent to the processor 10 via the receiver gate circuit 43.

When it is necessary to transmit the transmission data from the processor 10 to another processor during the reception of such reception data, the transmission data is transmitted to the processor 1.
It is written from 0 to the transmission memory 34 via the transmitter gate circuit 33. This activates the transmission of the bus interface circuit 20. When the transmission is activated, the second bus 12 that is not used for reception is selected by the transmission bus selection circuit 31. After that, the transmission data is read from the transmission memory 34 by the transmission memory control circuit 33, and then transmitted to the other processor of the transmission destination via the second interface circuit 22 and the selected second bus 12. .

[0021]

Since the present invention is configured as described above, it has the following effects.

First by the data transmitting unit and the data receiving unit
The bus and the second bus can be exclusively selected, so that data can be transmitted and received at the same time.
It is possible to avoid competition between transmission and reception in data communication between processors, reduce bus congestion time,
The processing capacity of the entire system can be increased.

[Brief description of drawings]

FIG. 1 is a block diagram showing a bus interface circuit which is an embodiment of a transmission / reception simultaneous control interface circuit for an interprocessor bus according to the present invention.

FIG. 2 is a block diagram showing a conventional example of a bus interface circuit used in a multiprocessor system in which a plurality of processors are connected to each other by two buses for data transfer.

[Explanation of symbols]

 10 Processor 11 First Bus 12 Second Bus 20 Bus Interface Circuit 21 First Interface Circuit 22 Second Interface Circuit 30 Data Transmission Unit 31 Transmission Bus Selection Circuit 32 Transmission Memory Control Circuit 33 Transmission Unit Gate Circuit 34 Transmission Memory 40 Data Receiver 41 Receive Bus Selection Circuit 42 Receive Memory Control Circuit 43 Receiver Gate Circuit 44 Receive Memory

Claims (2)

[Claims] 1. A transmission / reception simultaneous control interface of an interprocessor bus used in a multiprocessor system in which a first processor and a second processor are connected to each other by a first bus and a second bus for data transfer. A first interface circuit connected to the first bus, a second interface circuit connected to the second bus, the first processor, and the first and second circuits. The transmission data sent from the first processor, which is provided between the interface circuit and the first interface circuit, is transmitted to the first bus via the first interface circuit or the second data via the second interface circuit. A data transmission unit for outputting to a first bus; the first processor; and the first and second interface circuits Received data sent from the first bus via the first interface circuit or from the second bus via the second interface circuit, which is provided in between, to the first processor. A data receiving unit for outputting, wherein the data transmitting unit connects the second bus when the data receiving unit receives the received data from the first bus via the first interface circuit. On the other hand, a transmission bus selection circuit that selects the first bus when the data receiving unit is receiving the reception data from the second bus via the second interface circuit, The data receiving unit is configured to output the transmission data to the first bus via the first interface circuit when the data transmission unit outputs the transmission data. And a reception bus selection circuit that selects the first bus when the data transmission unit is outputting the transmission data to the second bus via the second interface circuit. A transmission / reception simultaneous control interface circuit for an inter-processor bus, characterized by having. 2. The data transmission unit, a transmission memory in which the transmission data is stored, and a transmission for controlling writing of the transmission data to the transmission memory and reading of the transmission data from the transmission memory. A credit memory control means, wherein the data receiving unit stores a reception data in which the reception data is stored, writing the reception data into the reception memory, and receiving the reception data from the reception memory. 2. The transmission / reception simultaneous control interface circuit for an interprocessor bus according to claim 1, further comprising a reception memory control means for controlling reading.