JPH07106595A - Thin film mos transistor integrated circuit - Google Patents

Abstract

PURPOSE:To realize a high speed integrated circuit and stable circuit operation, by setting a preliminary period for making carriers stored in body nodes of thin film transistors escape through a body node potential control circuit part, and an estimation period for turning the body nodes into an electrically floating state. CONSTITUTION:The source of an NMOS transistor M8 is connected with body nodes of NMOS transistors M2-M5, M7. The drain of a PMOS transistor M9 is connected with body nodes of PMOS transistors M1, M6. The transistors M8, M9 set a preliminary period for making carriers stored in the body nodes of the transistors M1-M7 escape and an estimation period for turning the body nodes into an electrically floating state. Thereby the transistors can be stably operated during the preliminary period and the estimation period, and high speed operation can be ensured.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film MOS transistor integrated circuit.

[0002]

2. Description of the Related Art In a MOS transistor formed of a single crystal silicon thin film provided on an oxide film on the surface of a silicon wafer, or a polysilicon or amorphous silicon thin film on a glass substrate, the thickness of these thin films is Except when the depletion layer under the gate oxide film spreads over the entire thin film, it is very thin, for example, about 0.2 μm or less.
It has been reported that a kink is seen in the voltage-current characteristics of a MOS transistor, and a transiently large drain current flows when the MOS transistor is turned on (Veer
araghavan et al., IEEE Trans.on Computer-Aided Desi
gn vol.CAD-5, No.4, pp.653-658,1986).

Both kink and transient drain current
It is caused by the electrically floating body of the OS transistor. In the vicinity of the high electric field drain region, excess electrons and holes are generated by impact ionization by channel electrons. The electrons generated here can escape from the drain terminal, but the holes have no escape route, so they are accumulated in the body as they are and raise the potential of the body to a potential higher than the source potential.

For this reason, the threshold value of the thin film MOS transistor is lowered, and it is observed as a kink when measuring the voltage-current characteristics. When the thin film MOS transistor is turned on, the transient drain current causes the depletion layer under the gate to spread, causing holes originally existing near the substrate surface to flow into the neutral body region, causing the potential of the body to transition. It is caused by a rise in the price.

[0005]

Kinks and transient drain currents are preferable because they speed up the circuit operation, but the number of holes accumulated in the body depends on the operating state of the circuit. Since it changes, it has the drawback of lacking in stability of circuit operation.

To eliminate kinks and transient drain currents, it is common practice to connect the body to a source or ground terminal. However, with this configuration, although the circuit operation is stable, there is a drawback in that the speedup of the circuit caused by the presence of a kink or a transient drain current is lost.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to simultaneously achieve high speed and stability of circuit operation of a thin film MOS transistor integrated circuit.

[0008]

In order to solve the above-mentioned problems, the thin film MOS transistor integrated circuit of the present invention comprises:
A logic circuit section composed of thin film MOS transistors;
A body node potential control circuit section for controlling the potential of the body node of the thin film MOS transistor, and storing in the body node of the thin film MOS transistor in one cycle of a clock for driving the logic circuit section. It comprises a preparation period for allowing the generated carriers to escape through the body node potential control circuit section and an evaluation period for electrically floating the body node of the thin film MOS transistor.

Further, in the present invention, the NMO of the thin film MOS transistors forming the logic circuit section is used.
Carriers in the body node of the S transistor are released by the enhancement type NMOS transistor formed in the body node potential control circuit unit, and in the body node of the PMOS transistor of the thin film MOS transistors forming the logic circuit unit. It is preferable that the carriers of (1) are released by the enhancement type PMOS transistor formed in the body / node potential control circuit section.

Further, according to the present invention, the NMO of the thin film MOS transistors forming the logic circuit section is used.
Carriers in the body node of S transistor only,
It is preferable that the enhancement-type NMOS transistor formed in the body / node potential control circuit section is used for relief.

Further, in the present invention, it is preferable that the logic circuit section is a domino CMOS integrated circuit.

Further, in the present invention, it is preferable that the logic circuit section is a clocked CMOS type integrated circuit.

Further, in the present invention, it is preferable that the logic circuit section is a NORA type CMOS integrated circuit.

Further, in the present invention, the thin film MOS is provided.
SOI / MO in which a transistor is formed in a single crystal silicon thin film provided on an oxide film on the surface of a silicon wafer
It is preferably an S transistor.

Also, in the present invention, the thin film MOS is provided.
The transistor is preferably a thin film MOS transistor formed of polysilicon on a glass substrate or amorphous silicon.

[0016]

In the present invention, one cycle of the clock for controlling the operation of the integrated circuit has a preparation period and an evaluation period, and the carriers accumulated in the body node of the thin film MOS transistor are released during the preparation period to allow the circuit to operate. The stability is ensured and the body node of the thin film MOS transistor is floated during the evaluation period to ensure the high speed of the circuit.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a thin film MOS transistor integrated circuit of the present invention will be described below with reference to the drawings.

FIG. 1 shows, as a first embodiment of a thin film MOS transistor integrated circuit having a preparation period and an evaluation period in one cycle of a clock, a domino CMOS integrated circuit having a logical expression of (A∧B) ∨C. Is shown. All of the transistors M1 to M9 forming the circuit of FIG. 1 are thin film MOS transistors.

The terminal configuration of the NMOS transistor shown in FIG. 1 is shown in FIG. 2, and the terminal configuration of the PMOS transistor is shown in FIG. The difference between these thin film transistors and a normal bulk MOS transistor realized by using a silicon wafer is that they have a body node under a channel in addition to terminals such as a source, a gate, and a drain for performing a transistor operation. is there.

The integrated circuit of FIG. 1 includes a circuit block for performing a logical operation, which is composed of transistors M1 to M7, and M.
8 and a circuit block for controlling the potential of the body node composed of M9 transistors. The source of the NMOS transistor M8 is connected to the body nodes of the NMOS transistors M2 to M5 and M7, and the drain of the PMOS transistor M9 is P.
Connected to the body nodes of the MOS transistors M1 and M6, the transistors M8 and M9 release the carriers accumulated in the body nodes of the transistors M1 to M7 and electrically float the body nodes.

The signal of φ1 is a clock for driving a circuit block which performs a logical operation, and is a transistor M1.
And to the gate of M5.

The signals φ2 and φ3 are clocks for driving a circuit block for controlling the potential of the body node, and the clock φ2 is the transistor M8.
The clock of φ3 is supplied to the gate of
9 gates.

FIG. 4 is a timing chart showing the configuration of clocks for driving the circuit of FIG. When the clock of φ1 is “Low”, the circuit block configured by the transistors of M1 to M7 for performing the logical operation enters the preparation period, and the node of the transistor M1 having V1 supplies the power supply voltage V
It is precharged to dd, and the V1 node becomes "High". As a result, the output voltage V ₀ is dropped to the ground and put in the “Low” state.

At this time, the transistor M5 is off,
The node of V1 is isolated from the ground regardless of the state of the logic inputs A, B, C input to the gates of the transistors M2, M3, M4.

In the present embodiment, during this preparation period, extra carriers accumulated in the body nodes of the thin film MOS transistors M1 to M7 forming the logic circuit are released, and the transistor operates stably during the evaluation period. To do so.

The time when the clock φ1 becomes "High" is the evaluation period of the logic circuit, and the transistor M1 is turned off and the transistor M5 is turned on.
The potential of the V2 node is dropped to ground. The potential of the V1 node is conditionally dropped to the ground depending on the states of the inputs A, B, and C. That is, in the circuit of FIG. 1, only when the input satisfies the condition of (A∧B) ∨C = “1”, the potential of the node V1 becomes “Low”, and the output V ₀ of the circuit becomes “High”. become. That is, the entire circuit of FIG. 1 fulfills the logical function of (A∧B) ∨C.

In the present embodiment, during the evaluation period, the body nodes of the thin film MOS transistors M1 to M7 forming the logic circuit are electrically floated, and the kink effect and the transient drain current are used to increase the circuit speed. It is trying to make it.

The efficient and concrete method for escaping the carrier in the body node or electrically floating the body node will be described below.

The embodiment shown in FIG. 1 has a circuit configuration for achieving this in the simplest manner. That is, the NMOS transistors M2 to M5, M7 and PM in the logic circuit
In order to control the body nodes of the OS transistors M1 and M6, NMOS transistors M8 and P are respectively provided.
The MOS transistor M9 is assigned.

During operation of the circuit of FIG. 1, holes are stored in the body nodes of the NMOS transistors M2 to M5 and M7 and electrons are stored in the body nodes of the PMOS transistors M1 and M6. Using only one type of transistor like
Escape of carriers in body nodes is inefficient.

For example, PMOS transistors M1 and M6
When the electrons accumulated in the body node of the above are attempted to escape by the NMOS transistor, the clock φ3 has a phase opposite to the phase shown in FIG. 4 (that is, the clock φ3).
However, in order to release the accumulated electrons, the clock φ3 must be a voltage higher than the potential of Vb2. In order to make the voltage of the clock φ3 higher than the potential of Vb2, it is necessary to supply a voltage other than the power supply voltage and the ground from the outside or internally generate the voltage, and to the peripheral circuit for driving the circuit. Will increase the burden on.

In order to prevent this problem from occurring,
In order to control the body nodes of the NMOS transistors M2 to M5 and M7 and the PMOS transistors M1 and M6 in the logic circuit, N
It is preferable to allocate the MOS transistor M8 and the PMOS transistor M9. Then, the NMOS transistor M8 is driven by the clock φ2 as shown in FIG.
The clock φ3 as shown in FIG.
Drive.

By using both the transistors M8 and M9, during the preparation period, the body node control transistors M8 and M9 are turned on to release the carriers in the bodies of the transistors M1 to M7 and stabilize the circuit operation. During the evaluation period, the transistors M8 and M9 for controlling the body node are turned off to leave the body nodes of the transistors M1 to M7 in a floating state to speed up the circuit.

Then, the NMOS transistor M to be used
8, the PMOS transistor M9 is a clock "High"
Although realistic voltage of h "and" Low ", that is," High "is ideally Vdd and" Low "is ground, it is normally turned on and off with respect to the voltage in which noise is superimposed. Use a reliable enhancement type.

During the preparation period, the transistors M8 and M9 that control the connection state of the body nodes are kept on, and the NMOS transistors M2 to M5 and M7 and the PMOS transistor M that form the logic circuit, respectively.
The voltage Vb1 and the voltage Vb2 are supplied to the body nodes of M1 and M6. The voltage Vb1 may be the ground potential and the voltage Vb2 may be the power supply voltage Vdd, but any other voltage may be used.

FIG. 5 is a circuit diagram showing a second embodiment of the thin film MOS transistor integrated circuit of the present invention. This second
In this embodiment, the body of the NMOS transistors M2 to M5 and M7 is controlled by the transistor M8 of the embodiment of FIG.
Only the node control is performed, and the PMOS transistor M1
The body node of M6 is not controlled.

Generally, the amount of carriers stored in the body node of a thin film PMOS transistor is determined by the thin film NMO.
It is smaller than the amount of carriers stored in the body node of the S transistor. It is considered that this is because the rate of impact / ionization of holes that are carriers of the PMOS transistor is low and the electric field near the drain of the NMOS transistor is high. This means, for example, “M.Ka
kumu et al., IEEE Trans.on Electron Devices, vol.37,
No. 5, pp. 1334-1342, 1990 ”.

Therefore, in an actual circuit, as shown in FIG. 5, there are cases where a sufficient effect can be obtained by controlling only the body nodes of the NMOS transistors M2 to M5 and M7. Since the circuit of FIG. 5 has a smaller number of elements than the circuit of FIG. 1, the area required to fulfill the same function becomes smaller.

In the above description of the embodiments, an example in which a domino CMOS integrated circuit is used as a logic circuit has been shown, but the present invention is a clocked CMOS integrated circuit, N
It can be applied to a logic circuit such as an ORA type CMOS integrated circuit in almost the same manner.

As the above-mentioned thin film MOS transistor, an SOI / MOS transistor (including an SOI structure by SIMOX method) formed in a single crystal silicon thin film provided on an oxide film on the surface of a silicon wafer, Alternatively, it may be a thin film MOS transistor formed of polysilicon on a glass substrate or amorphous silicon.

Next, an example of a method of manufacturing the thin film MOS transistor used in the present invention will be described with reference to FIGS.

First, as shown in FIG. 6, a buried insulating film 22 made of silicon oxide and a single crystal silicon thin film (SOI) 21 are formed on a silicon substrate 23 by a SIMOX method.

In this example, the thickness of the buried insulating film 22 is 440 nm and the thickness of the single crystal silicon thin film 21 is 500.
nm, this single crystal silicon thin film 21 can be realized by implanting oxygen ions and then epitaxially growing single crystal silicon on the buried insulating film 22. In addition to the SIMOX substrate, an SOI substrate obtained by a laser recrystallization method, a solid phase epitaxial growth method, or the like can also be used.

Next, as shown in FIG. 7, a pad oxide film 24 is formed on this SOI substrate by thermal oxidation, and then a silicon nitride film 25 is deposited by a CVD method.
After that, the silicon nitride film 25 existing in a region other than the element region is removed by photolithography, and the single crystal silicon thin film 21 in the region where the silicon nitride film 25 is removed is reached by wet oxidation until the buried insulating film 22 is reached. It oxidizes completely.

By this step, the region of the single crystal silicon thin film 21 where the MOS transistor will be formed later is surrounded by silicon oxide and is electrically insulated from the surroundings. After this, by dry etching,
The silicon nitride film 25 remaining on the front surface and the back surface is removed, and then the pad oxide film 24 is formed by wet etching.
To remove.

Next, after forming the sacrificial oxide film, in order to control the impurity concentration in the single crystal silicon thin film 21, an N channel type SOI / MOS transistor and a P channel type S are formed.
Boron is ion-implanted in each region where the OI / MOS transistor is formed.

Next, as shown in FIG. 8, after removing the sacrificial oxide film by wet etching, a gate insulating film 26 is formed by dry oxidation.

Next, as shown in FIG. 9, phosphorus-doped polysilicon is deposited by LPCVD,
The polysilicon thin film 29 is processed into a predetermined shape by photolithography. By the subsequent heat treatment, a P-type polysilicon gate is formed in the N-channel element and an N-type polysilicon gate is formed in the P-channel element. Then, with self-alignment technology,
Ions are implanted into the gate and the source / drain regions 27 and 28. Then, heat treatment after implantation activates the impurities in the source / drain regions 27 and 28.

Next, as shown in FIG. 10, non-doped LTO is deposited and anisotropic etching is performed,
Spacers 30 are formed on the sidewalls of the gate.

Next, as shown in FIG. 11, Ti is deposited on the entire surface and annealed in a nitrogen atmosphere to form source / drain regions 27, 28 located on the upper portion of the polysilicon thin film 29 and outside the spacer 30. And a metal silicide region 31 made of TiSi ₂ .

Next, in a mixed solution of sulfuric acid and hydrogen peroxide,
After the TiN formed on the surface is etched, the heat treatment is performed again in a nitrogen atmosphere to make the formation of the metal silicide region 31 more reliable. The metal silicide is used to reduce the parasitic resistance associated with the gate, source and drain.

Next, as shown in FIG. 12, a non-doped LTO film 32 is deposited and photolithography is performed.
Drill the contact area. Thereafter, TiW to be a barrier metal and aluminum are deposited, and the metal wiring layer 33 is formed by photolithography. As a result, an SOI / MOS transistor is formed.

[0053]

According to the present invention, stability and high speed of a thin film MOS transistor integrated circuit can be secured at the same time.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a thin film MOS transistor integrated circuit of the present invention.

FIG. 2 is a schematic diagram showing a terminal configuration of a thin film NMOS transistor.

FIG. 3 is a schematic diagram showing a terminal configuration of a thin film PMOS transistor of the present invention.

FIG. 4 is a timing chart showing a configuration of a clock for driving the circuit of FIG.

FIG. 5 is a circuit diagram showing a second embodiment of the thin film MOS transistor integrated circuit of the present invention.

FIG. 6 is a cross-sectional view showing the manufacturing process of the thin film MOS transistor of the present invention.

FIG. 7 is a cross-sectional view showing the manufacturing process of the thin film MOS transistor of the present invention.

FIG. 8 is a cross-sectional view showing the manufacturing process of the thin film MOS transistor of the present invention.

FIG. 9 is a cross-sectional view showing the manufacturing process of the thin film MOS transistor of the present invention.

FIG. 10 is a cross-sectional view showing the manufacturing process of the thin film MOS transistor of the present invention.

FIG. 11 is a cross-sectional view showing the manufacturing process of the thin film MOS transistor of the present invention.

FIG. 12 is a cross-sectional view showing the manufacturing process of the thin film MOS transistor of the present invention.

[Explanation of symbols]

 21 single crystal silicon thin film (SOI) 22 buried insulating film 23 silicon substrate 24 pad oxide film 25 silicon nitride film 26 gate oxide film 27, 28 source / drain 29 polysilicon thin film 30 spacer 31 metal silicide region 32 LTO film 33 metal wiring Layer M1 to M9 Thin film MOS transistor

Claims (8)

[Claims] 1. A logic circuit section including a thin film MOS transistor, and a body node potential control circuit section for controlling a potential of a body node of the thin film MOS transistor, and driving the logic circuit section. In one cycle of the clock
A preparation period for allowing carriers stored in the body node of the thin film MOS transistor to escape through the body node potential control circuit section, and an evaluation period for electrically floating the body node of the thin film MOS transistor are provided. A thin film MOS transistor integrated circuit characterized by the above. 2. The thin film MO forming the logic circuit section.
Carriers in the body node of the NMOS transistor of the S transistors are released by the enhancement type NMOS transistor formed in the body node potential control circuit section, and the PMOS transistor of the thin film MOS transistors forming the logic circuit section. 2. The thin film MOS transistor integrated circuit according to claim 1, wherein the carriers in the body node are released by an enhancement type PMOS transistor formed in the body node potential control circuit section. 3. The thin film MO forming the logic circuit section.
2. The thin film MOS transistor integrated circuit according to claim 1, wherein carriers in the body node of only the NMOS transistor of the S transistors are released by the enhancement type NMOS transistor formed in the body node potential control circuit section. . 4. The thin film MOS transistor integrated circuit according to claim 1, wherein the logic circuit section is a domino CMOS integrated circuit. 5. The logic circuit section is a clocked CMOS
4. The thin film MOS transistor integrated circuit according to claim 1, wherein the thin film MOS transistor integrated circuit is a type integrated circuit. 6. The NORA type CMOS is provided in the logic circuit section.
4. The thin film MOS transistor integrated circuit according to claim 1, wherein the thin film MOS transistor integrated circuit is a type integrated circuit. 7. The thin film MOS transistor is an SOI / MOS transistor formed on a single crystal silicon thin film provided on an oxide film on a surface of a silicon wafer, according to claim 1. 2. A thin film MOS transistor integrated circuit according to item 1. 8. The thin film MOS transistor according to claim 1, wherein the thin film MOS transistor is a thin film MOS transistor formed of polysilicon on a glass substrate or amorphous silicon. Thin film M
OS transistor integrated circuit.