JP2002289850A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having a transistor enabling micro- fabrication and performance increase in a simple structure by using a bulk semiconductor. SOLUTION: A gate electrode is formed via a gate insulation film on the surface of a semiconductor substrate and source and drain diffusion layers are formed, so as to face each other across a channel region right below the gate electrode. The source and drain diffusion layers are constituted of a low-resistance region and the shallow extension region of an impurity concentration lower than the one of the low resistance region; in the channel region between the source and drain diffusion layers, the first impurity doped layer of a first conductivity type, the second impurity doped layer of a second conductivity-type, formed under the first impurity doped layer and the third impurity doped layer of the first conductivity-type, formed under the second impurity doped layer are formed; for the first impurity doped layer, the junction depth is set to be the same or shallower than the one of the extension region of the source and drain diffusion layers; and for the second impurity doped layer, the impurity concentration and thickness are set so as to be fully depleted by built-in potential generated between the first and third impurity doped layers.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device in which a transistor is miniaturized and its performance is improved by using a bulk semiconductor, and a method of manufacturing the same.

[0002]

2. Description of the Related Art At present, SOI (Silicon On Ins) is used as a transistor suitable for miniaturization and high performance.
MISFETs in which the channel region is completely depleted (Fully Depleted) using an ullator substrate have been researched and developed in various places. Hereinafter, this MISFET
Is called FD-SOIFET. This element is basically
The silicon layer on the oxide film serving as a channel region has a low impurity concentration and a thickness necessary for complete depletion.

In the FD-SOIFET, the vertical electric field from the gate electrode is partially carried by the buried oxide film at the bottom of the channel region, and the vertical electric field applied to the channel region is reduced accordingly. As a result of the relaxation of the vertical electric field in the channel region, the carrier mobility in the channel region is increased, and there is an advantage that a high current driving capability can be obtained.

However, the FD-SOIFET has many disadvantages when further miniaturization is considered. For example, in order to suppress the short channel effect, a very thin silicon layer SO
The need to use an I substrate, the use of a thin silicon layer increases the parasitic resistance, and the upper and lower portions of the channel region are surrounded by an oxide film having a lower thermal conductivity than silicon. Conduction of heat generated in the region is poor, and performance degradation is large. Others
Poor quality of SOI substrate and reliability of gate insulating film
There is also a problem that plasma damage is large. SO
One of the disadvantages is that the I substrate is expensive at present.

On the other hand, an FD using a bulk semiconductor
Attempts have been made to solve the above-mentioned disadvantages of the FD-SOIFET while exhibiting the same effects as the -SOIFET. Specifically, when the channel region is a p-type layer, ap / n ⁻ in which a low impurity concentration n ⁻ -type layer that is depleted by a built-in potential is disposed below the channel region.
It has been proposed to realize a pseudo SOIFET by using a / p structure (T. Mizuno).
et al,: 1991 Symp.on VLSI Tech.p.109 (1991),
M. Miyamoto et al ,: IEDM Tech. Dig. P.411 (1998),
Ishii, Miyamoto: JP-A-7-335837 and the like.

[0006]

However, there are still many problems to be solved in the conventionally proposed pseudo SOIFET, and it is difficult to obtain sufficient performance in the submicron range. That is, the pseudo SOIF shown in the literature
In ET, the depth (thickness) of the channel region is larger than the depth of the source / drain diffusion layers. This greatly hinders the suppression of the short channel effect when the device is further miniaturized. Further, if the semiconductor layer in the channel region is a low impurity concentration layer necessary for realizing a fully depleted element, punch-through becomes a problem when the gate length (channel length) is reduced to submicron. In order to prevent punch-through, a complicated drain structure is required as shown in the literatures.

[0007] Also, in the structure of illustrated literature, the source is formed by a counter-doping, the drain diffusion layer bottom the n ^- reach the p-type layer underneath the -type layer. Therefore, the junction capacitance between the source and the drain is large, and high-speed operation becomes difficult. Further, in the literature, only an ion implantation method is considered as a method for obtaining the p / n ⁻ / p structure of the channel region. However, if an attempt is made to actually obtain a p / n ⁻ / p structure only by the ion implantation method, there is a limit in reducing the impurity concentration of the channel region and reducing the thickness thereof.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a semiconductor device having a transistor having a simpler structure and capable of miniaturization and high performance, and a method of manufacturing the same. I have.

[0009]

A semiconductor device according to the present invention comprises a semiconductor substrate, a gate electrode formed on a surface of the semiconductor substrate via a gate insulating film, and a channel directly below the gate electrode on the semiconductor substrate. A source formed of a low-resistance region formed so as to face the region, and an extended region having a lower impurity concentration and shallower than the low-resistance region formed to extend from the low-resistance region toward the channel region; And a drain diffusion layer; a first conductivity type first impurity doped layer formed in the channel region between the source and drain diffusion layers; and a second impurity formed below the first impurity doped layer. A second impurity-doped layer of a conductivity type;
A third impurity-doped layer of a first conductivity type formed below the second impurity-doped layer, wherein the first impurity-doped layer has a junction depth extending from the source and drain diffusion layers. The impurity concentration and thickness of the second impurity-doped layer are set so as to be completely depleted by a built-in potential generated between the first and third impurity-doped layers. It is characterized by having been done.

The semiconductor device according to the present invention also includes a semiconductor substrate, a gate electrode formed on the surface of the semiconductor substrate with a gate insulating film interposed therebetween, and a semiconductor substrate with a channel region immediately below the gate electrode interposed therebetween. A first impurity-doped layer of a first conductivity type formed in the channel region between the source and drain diffusion layers; and a first impurity-doped layer formed in the channel region between the source and drain diffusion layers. A second conductivity type second impurity doped layer formed below the first conductive type second impurity doped layer; and a first impurity doped layer formed below the second impurity doped layer.
A third impurity-doped layer of a conductivity type, wherein the first impurity-doped layer has a junction depth set to be equal to or less than that of the source and drain diffusion layers, and the second impurity-doped layer has The junction depth with the third impurity-doped layer is deeper than the junction depth of the source and drain diffusion layers, and the junction is completely depleted by a built-in potential generated between the first and third impurity-doped layers. The feature is that the impurity concentration and the thickness are set as described above. In this case, preferably, the source and drain diffusion layers include a low resistance region and an extension region having a lower impurity concentration and shallower than the low resistance region formed to extend from the low resistance region to the channel region side. And

According to the present invention, there is provided an FET using a bulk semiconductor, wherein pnp (or np
n) by forming the three-layer structure such that the intermediate layer is completely depleted with a built-in potential.
An OIFET can be obtained. In particular, by forming the first semiconductor layer serving as a channel region in the three-layer structure to be extremely thin, the short channel effect when miniaturized can be suppressed and the punch-through resistance can be increased. . Further, by forming the diffusion depth of the source / drain diffusion layer shallower than the junction surface between the second semiconductor layer and the third semiconductor layer, the junction capacitance and the junction leak of the source / drain can be reduced.

In the present invention, for example, the impurity concentration and the thickness of the first semiconductor layer are set so as to be completely depleted when the channel inversion layer is formed. Thereby, a fully depleted FET is obtained. Alternatively, the impurity concentration and thickness of the first semiconductor layer can be set so as to be partially depleted when the channel inversion layer is formed, whereby a partially depleted FET is obtained.

In the present invention, the three-layer structure immediately below the gate electrode may be selectively formed only in a region immediately below the gate electrode. Further, in the present invention, a structure in which the fourth semiconductor layer of the first conductivity type is buried immediately below the extension region of the source and drain diffusion layers can be obtained, whereby higher punch-through resistance can be obtained. Further, in the present invention, it is preferable that the low resistance regions of the source and drain diffusion layers protrude above the position of the gate insulating film by selective epitaxial growth.
This makes it possible to form source and drain diffusion layers having a shallow diffusion depth.

When the pseudo SOIFET according to the present invention is a fully-depleted FET, the gate electrode is preferably formed by a metal electrode having a work function necessary to obtain a desired threshold voltage. In the case of a partially depleted FET, a polycrystalline silicon gate can be used.

The semiconductor device according to the present invention further comprises a semiconductor substrate, a gate electrode formed on a surface of the semiconductor substrate via a gate insulating film, and a semiconductor substrate with a channel region immediately below the gate electrode interposed therebetween. A source and drain diffusion layer formed of a low resistance region and an extension region having a lower impurity concentration and shallower than the low resistance region formed to extend from the low resistance region to the channel region side. A first impurity-doped layer of a first conductivity type formed in the channel region between the source and drain diffusion layers, and a second impurity-doped second layer of a second conductivity type formed under the first impurity-doped layer And a third impurity-doped layer of a first conductivity type formed below the second impurity-doped layer. The first impurity-doped layer has a junction depth of An impurity concentration and a thickness are set so as to be selectively formed in a state deeper than that of the extended region of the source and drain diffusion layers and partially depleted when forming the channel inversion layer; The layer is selectively formed such that both ends thereof are in contact with the extended regions of the source and drain diffusion layers, and is completely depleted by a built-in potential generated between the first and third impurity dopings. It is characterized in that the impurity concentration and the thickness are set. With such a structure, the first semiconductor layer is surrounded by a depletion layer formed between the source and drain extension regions and a second semiconductor layer that is completely depleted, so that the first semiconductor layer enters a floating state. Then, a partially depleted FET is obtained.

The semiconductor device according to the present invention further comprises a semiconductor substrate, a first source and drain diffusion layer formed on the semiconductor substrate so as to be separated from each other, and a first source and drain diffusion layer of the semiconductor substrate. A first transistor having a first gate electrode formed therebetween with a gate insulating film interposed therebetween, a second source and drain diffusion layer formed separately from each other on the semiconductor substrate, and a second transistor formed on the semiconductor substrate. A second transistor having a second gate electrode formed between the second source and drain diffusion layers with a gate insulating film interposed therebetween, wherein the first transistor includes the first source and drain diffusion layers. A first conductivity type first impurity-doped layer formed in a channel region between the first and second conductivity type second impurities formed below the first impurity-doped layer; And a third impurity-doped layer of a first conductivity type formed below the second impurity-doped layer, and the first impurity-doped layer has a junction depth of the third impurity-doped layer. The impurity concentration and thickness are set so as to be equal to or shallower than those of the first source and drain diffusion layers and to be completely depleted or partially depleted when the channel inversion layer is formed. Is deeper than that of the first source and drain diffusion layers, and is completely depleted by a built-in potential generated between the first and third impurity doped layers. In this case, the impurity concentration and the thickness are set such that

According to the present invention, a pseudo S which can be miniaturized and can suppress the short channel effect as the first transistor.
An LSI using the OIFET can be obtained. For example, if the second transistor is a bulk FET having a first conductivity type bulk layer which is an impurity doped layer deeper than the second source and drain diffusion layers in a portion immediately below the second gate electrode of the semiconductor substrate, An integrated structure of a pseudo SOI FET (fully depleted device or partially depleted device) and a bulk FET can be obtained. If the second transistor is a pseudo SOIFET having a structure similar to that of the first transistor, a combination in which one of the first and second transistors is a fully depleted element and the other is a partially depleted element can be obtained.

A method for manufacturing a semiconductor device according to the present invention comprises:
A semiconductor substrate having a first impurity-doped layer of at least a first conductivity type on at least a surface thereof has a first impurity not doped with an impurity.
Epitaxially growing a semiconductor layer of the second type, ion-implanting the first semiconductor layer to form a second impurity-doped layer of a second conductivity type in contact with the first impurity-doped layer, Forming a third impurity-doped layer of the first conductivity type in contact with the second impurity-doped layer by performing ion implantation on a surface portion of the semiconductor layer;
Forming a gate electrode on the impurity-doped layer with a gate insulating film interposed therebetween; and forming the third impurity-doped layer and the second impurity-doped layer on the semiconductor substrate while being self-aligned with the gate electrode. Forming a source and drain diffusion layer having a junction depth deeper than a junction surface and shallower than a junction surface between the second impurity-doped layer and the first impurity-doped layer.

The method of manufacturing a semiconductor device according to the present invention also includes a step of epitaxially growing a first semiconductor layer not doped with an impurity on a semiconductor substrate having a first impurity doped layer of a first conductivity type on at least a surface thereof. Forming a second impurity-doped layer of a second conductivity type in contact with the first impurity-doped layer by ion-implanting the first semiconductor layer; and forming an impurity on the second impurity-doped layer. Epitaxially growing an undoped second semiconductor layer; and ion-implanting the second semiconductor layer to form a third impurity-doped layer of the first conductivity type in contact with the second impurity-doped layer. A step of forming a gate electrode on the third impurity-doped layer via a gate insulating film, and a state in which the gate electrode is self-aligned with the semiconductor substrate. , The third impurity doped layer of the second
Forming a source and drain diffusion layer having a junction depth deeper than the junction surface of the impurity-doped layer and shallower than the junction surface between the second impurity-doped layer and the first impurity-doped layer. And

According to the manufacturing method of the present invention, by using the epitaxial growth and the ion implantation, the pseudo SO
A shallow channel region semiconductor layer can be formed with a low impurity concentration of the IFET. In the manufacturing method of the present invention,
The step of forming the source and drain diffusion layers is preferably performed by ion implantation using the gate electrode as a mask.
Forming an extension region deeper than the impurity diffusion layer, forming a side wall insulating film on the side wall of the gate electrode, and performing ion implantation using the gate electrode and the side wall insulating film as a mask to obtain a higher impurity concentration than the expansion region. And forming a low-resistance region deeper than the extension region and shallower than a junction surface between the second impurity diffusion layer and the first impurity diffusion layer.

In the manufacturing method of the present invention, the step of forming an element isolation insulating film may be performed prior to the step of epitaxially growing a semiconductor layer, or may be performed after forming a three-layer structure of a channel region. Good. In particular, if the latter is used, it is possible to prevent a short circuit between adjacent element regions when epitaxial growth is performed after element isolation.

[0022]

Embodiments of the present invention will be described below with reference to the drawings. Although the following embodiments all show n-channel MISFETs, it goes without saying that the present invention can be similarly applied to p-channel MISFETs in which the conductivity type of each part is reversed.

[First Embodiment] FIG. 1 shows a cross-sectional structure of a MISFET according to a first embodiment. A p-type layer 2 is formed on the surface of the silicon substrate 1 by well ion implantation or the like, and an n ⁻ -type layer 3 having a low impurity concentration is formed thereon.
Further, a p-type layer 4 serving as a channel region is formed. Of these p / n ⁻ / p junction structures, at least the upper p-type layer 4 and the lower n ⁻ -type layer 3 are formed by using both an epitaxial growth step and an ion implantation step, as described later. It was done.

A gate electrode 6 is formed on a p-type layer 4 serving as a channel region via a gate insulating film 5. The gate electrode 6 mainly includes a metal electrode 6a having a predetermined work function, and a polycrystalline silicon electrode 6b is superposed on the metal electrode 6a.

The source / drain diffusion layers 7 are formed by ion implantation using the side wall insulating film 8 provided on the side walls of the gate electrode 6 and the gate electrode 6 as a mask, and have an n ⁺ -type low resistance region 7a; Before the sidewall insulating film 8 is formed, an ion implantation using the gate electrode 6 as a mask is performed so as to extend from the n ⁺ -type low-resistance region 7a to the channel region. Type extension area 7b
It is composed of The low resistance region 7a is formed so as to protrude above the position of the gate insulating film 5.
This structure is obtained by performing selective epitaxial growth after forming the gate electrode 6 as described later.
By utilizing this structure, the low-resistance region 7a
Is positioned so as not to reach the p-type layer 2, that is, inside the n ⁻ -type layer 3.

[0026] under the gate electrode p / n ^- / p n of the joint structure ^-
The impurity concentration and thickness of the mold layer 3 are set such that the mold layer 3 is completely depleted by a built-in potential between the upper and lower p-type layers 4 and 2. As a result, the transistor according to this embodiment has a buried oxide film under the channel region.
It becomes a pseudo SOIFET similar to the OI structure. Hereinafter, this transistor will be referred to as F using silicon on the depletion layer.
ET (S ilicon O n De pletion L a
yer FET ), which means "SODELFET"
Called.

The impurity concentration and the thickness of the p-type layer 4 serving as a channel region are selected so as to be completely depleted when the channel inversion layer is formed. Thereby, a fully depleted element, that is, an FD-SODELFET is obtained. In particular, the p-type layer 4
Needs to be sufficiently thin in order to suppress the short channel effect, and the junction depth (the position of the junction surface with the n ⁻ -type layer 3) is equal to or less than that of the source and drain extension regions 7b. Make it shallower. The example of FIG. 1 shows a case where the junction depth of the p-type layer 4 is shallower than that of the source and drain extension regions 7b.

FIG. 3 shows the relationship between the thickness of the p-type layer 4 in the channel region and the roll-off value δVth of the threshold voltage (the difference between the threshold voltage in the short channel and the threshold voltage in the long channel). The impurity concentration of the p-type layer 4 is shown as a parameter. It is known that the roll-off value δVth of the threshold voltage increases as the gate length Lg (that is, the channel length) decreases, as shown in FIG. The data in FIG. 3 shows that the impurity concentration of the n ⁻ -type layer 3 is 1E16 /
cm ³ , the gate oxide film thickness is 3 nm, and the power supply is Vdd = 1.
It is a calculation result in the case of 2V. FIG. 3 shows S for comparison.
The data of the OIFET are shown, and the data surrounded by a broken line is a normal bul using a uniformly doped p-type bulk silicon.
The case of kFET is shown.

FIG. 3 shows that as the thickness of the p-type layer 4 decreases, the roll-off value δVth of the threshold voltage approaches zero, and the short channel effect is suppressed. This is the same effect as that of the SOIFET. By thinning the channel region, the two-dimensional effect of the potential distribution along the drain shape is weakened, and the threshold voltage is reduced only by the one-dimensional potential distribution in the vertical direction. This is because it will be decided.

FIG. 3 also shows that if the δVth is the same, the SODELFET according to this embodiment is
This indicates that the p-type layer 4 may be thicker. this is,
This means that the MISFET can be made without forcibly forming a thin film, and that the variation in the threshold voltage due to the variation in the thickness of the p-type layer 4 can be reduced. It shows that it is advantageous.

However, the above effects depend on the impurity concentration of the p-type layer 4. As shown in FIG. 3, when the impurity concentration of the p-type layer 4 is about 1E17 / cm ³ or more, the effect of suppressing the short channel effect by thinning is almost lost, and the effect cannot be expected unless the thinning is considerable. This is a result of the fact that the elongation of the depletion layer immediately below the channel is reduced by thinning. Therefore, it is necessary to optimize the impurity concentration and the thickness of the p-type layer 4 serving as the channel region.

Further, by selecting the impurity concentration and thickness of the p-type layer 4 serving as a channel region and the work function of the gate electrode 6, the p-type layer 4 is partially depleted when the channel inversion layer is formed. You can also. Thus, a partially-depleted (P artially D epleted) elements, PD-SODELFET is obtained.

The n ⁻ -type layer 3 which needs to be completely depleted by the built-in potential also needs to be optimized for the impurity concentration and the thickness. This is because if a part of the n ⁻ -type layer 3 remains without being depleted, the source and the drain are short-circuited and the leak current increases. On the other hand, this n ^- type layer 3
To determine the degree of relaxation of the vertical electric field in the channel region by the thickness of the channel region, and to maintain a large carrier mobility in the channel region,
It is preferable that the thickness of the n ^- type layer 3 is large to some extent.

FIG. 4 shows the relationship between the thickness of the n ⁻ -type layer 3, δVth indicating the short channel effect, and carrier mobility (electron mobility μe). As shown, as the n ⁻ -type layer 3 becomes thicker, the electron mobility μe increases, but δVt
h also increases. That is, it indicates that there is a trade-off relationship between the suppression of the short channel effect and the improvement of the carrier mobility.

N ^+, which is a low resistance region of the source and the drain,
The junction depth of the mold layer 7a, as described above, n ^- -type layer 3 and p
It is set shallower than the bonding surface of the mold layer 2. This allows
Compared to the case where the n ⁺ -type layer 7a is formed to a depth reaching the p-type layer 2, the junction capacitance and the junction leakage of the source and the drain can be suppressed small, and a high punch-through withstand voltage can be obtained even at a low threshold voltage. The effect of being able to be expected can be expected. Also,
As a result, the junction capacitance between the source and the drain is reduced, so that the transistor can operate at high speed.

As described above, in order to optimize the impurity concentration distribution and the thickness of the p / n ⁻ / p structure, it is necessary to optimize the process conditions. According to the process simulation of the present inventor, it has become clear that it is difficult to form a three-layer structure of p / n ⁻ / p only by the ion implantation process as in the related art. That is, in order to form the p-type layer 2 of FIG. 1 with an impurity concentration of about 1E18 / cm ³ by ion implantation, it must be performed with a large dose and a high acceleration energy. The hem expands greatly. Then, the n ⁻ layer 3 having a low impurity concentration is further implanted into the surface of the formed p-type layer 2 by ion implantation.
And the formation of the p-type layer 4 is far from the desired impurity profile.

Therefore, in the manufacturing process of the present invention, an epitaxial growth layer is used for the p-type layer 4 to be a channel region in FIG. 1 and the n ⁻ -type layer 3 thereunder. Specifically, an example of a manufacturing process for obtaining the p / n ⁻ / p junction structure of FIG. 1 will be described below.

FIGS. 5A to 5D show an example of a manufacturing process for obtaining a p / n ⁻ / p junction structure including an element isolation process in consideration of a specific application to an LSI. First, as shown in FIG. 5A, a laminated mask of the buffer oxide film 21 and the silicon nitride film 22 is formed on the surface of the silicon substrate 1, a groove is formed in the element isolation region by RIE, and the element isolation insulating film is formed in the groove. Embed 23.

Thereafter, the silicon nitride film 22 and the buffer oxide film 21 are removed, and boron (B) ions are implanted to form the p-type layer 2 as shown in FIG. 5B. Specifically, boron (B) is accelerated at an acceleration voltage of 20 keV and a dose of 5 ×.
Ion implantation is performed at 10 ¹³ / cm ² . And this p-type layer 2
An undoped silicon layer 10 of, for example, 80 nm
Epitaxially grown to a thickness of

Next, as shown in FIG.
Arsenic (As) ion implantation is performed on the^-Type
The layer 3 is formed. As ion implantation conditions are, for example,
Pressure 20 keV, dose 5 × 10¹¹/ Cm^TwoAnd Continued
Then, as shown in FIG. 5D, B ion implantation is performed to
^-Forming p-type layer 4 serving as a channel region on the surface of mold layer 3
I do. This B ion implantation condition is, for example, an acceleration voltage of 5 ke.
V, dose 6 × 10 ¹¹/ Cm^TwoAnd

FIGS. 6A to 6E show an example in which two-stage epitaxial growth is used to form a p / n ⁻ / p junction structure. FIG. 6A shows the same element isolation process as FIG. 5A. After the element isolation, as shown in FIG. 6B, a p-type layer 2 is formed on the surface of the silicon substrate 1 by B ion implantation, and an undoped silicon layer 10 is epitaxially grown thereon. And as shown in FIG. 6C,
As ions are implanted into the silicon layer 10 to obtain n ⁻
The mold layer 3 is formed. Subsequently, as shown in FIG. 6D, epitaxial growth is performed again to form an undoped silicon layer 11 on the n ⁻ -type layer 3. Subsequently, as shown in FIG. 6E, B ions are implanted into the silicon layer 11 to form the p-type layer 4 serving as a channel region.

FIG. 2 shows an impurity profile of the p / n ⁻ / p junction structure formed by the above steps. By combining the epitaxial growth steps, it becomes possible to form the n ⁻ -type layer 3 and the p-type layer 4 having a low impurity concentration and a thickness necessary for complete depletion.

As described above, the element isolation step is performed by p / n ⁻ /
It is preferable to perform the step before forming the p-type structure in order to prevent re-diffusion of the p / n ⁻ / p-type impurity due to heat in the element isolation step. However, in this step, when the element isolation region is narrow, there is a possibility that the silicon layers of the adjacent element regions are connected on the element isolation region in the epitaxial growth step of the silicon layer. In order to reliably prevent such a situation, an element isolation step may be performed after forming the p / n ⁻ / p structure.

In the case where such an element isolation step is provided, a specific SODELFET integration step is shown in FIG.
This will be described with reference to FIG. The p-type layer 2, the n ⁻ -type layer 3 and the p-type layer 4 on the silicon substrate 1 shown in FIG. 7 are subjected to the epitaxial growth step described with reference to FIGS. 5A to 5D or 6A to 6E before the element separation step. And an ion implantation process. Such p / n ^-
As shown in FIG. 7, a mask made of a buffer oxide film 21 and a silicon nitride film 22 is formed in the transistor region on the substrate on which the / p structure is formed, and an element isolation groove is formed to a depth reaching the p-type layer 2 by RIE. Is formed, and the element isolation insulating film 23 is buried therein.

Next, as shown in FIG. 8, a gate oxide film 5 is formed, and a gate electrode 6 is formed. Gate electrode 6
Is a laminated electrode of a metal electrode 6a and a polycrystalline silicon electrode 6b having a work function required to obtain a predetermined threshold voltage. This stacked electrode is patterned using the silicon nitride film 24 as a mask. Then, As ions are implanted using the gate electrode 6 as a mask to form an n-type layer to be the source and drain extension regions 7b. The extension region 7 b has a junction depth greater than that of the p-type layer 4. However, the junction depth of the extension region 7b may be approximately the same as that of the p-type layer 4.

Next, as shown in FIG. 9, a sidewall insulating film made of a silicon nitride film 25 is formed on the sidewall of the gate electrode 6. Then, as shown in FIG. 10, the silicon surfaces of the source and drain regions are exposed, and a silicon layer 26 is formed thereon by selective epitaxial growth. This is for keeping the junction surface position between the p-type layer 2 and the n ⁻ -type layer 3 deeper than the diffusion depth of the high-concentration source and drain regions to be formed next.

Thereafter, as shown in FIG. 11, As ion implantation is performed to form n ⁺ -type low-resistance regions 7 of source and drain.
a is formed. As described above, the diffusion depth of the low-resistance region 7a is set so as not to reach the p-type layer 2. From the above, S
ODELFET is completed. Thereafter, as shown in FIG. 12, an interlayer insulating film 27 is deposited, a necessary contact hole is formed therein, and a contact plug 28 such as W is buried. Although not shown thereafter, a metal wiring is formed on the interlayer insulating film 27.

As described above, the SOD according to this embodiment
In the ELFET, the junction depth of the p-type layer 4 in the channel region is
The source / drain extension region 7b is formed shallower than that of the source / drain extension region 7b, and the bottom surface of the source / drain low resistance region 7a is n
^- have relatively large thickness of the mold layer 3 ^- n to lie within mold 3. Thereby, high carrier mobility in the channel region is ensured by the effect of relaxation of the vertical electric field, and the short channel effect can be sufficiently suppressed even in the submicron region. And these effects are p / n ⁻ / p
It can be obtained only by combining an epitaxial growth step to obtain a junction structure. In addition, the bottom surface of the low resistance region 7a of the source and the drain is in the n ⁻ -type layer 3 which is completely depleted by the built-in potential and is not in contact with the p-type layer 2, so that the junction capacitance is small. High-speed operation is possible, and a high punch-through withstand voltage is obtained.

In the case of this embodiment, it is also important to use a metal electrode 6a for the gate electrode 6 in order to realize a fully depleted element and to set the threshold voltage to an optimum condition. Specifically, as the metal electrode 6a, TiN,
WN or the like is used. The metal electrode 6a having two work functions is a combination of two materials (T
iN, WN) and (W, WN). That is, a desired threshold voltage can be obtained by using the metal electrode 6a having an appropriate work function according to a required threshold voltage.

On the other hand, when forming a partially depleted element, a polycrystalline silicon electrode is used as the gate electrode 6,
A desired threshold can be obtained.

In the above embodiment, in order to further improve the carrier mobility in the channel region, as the p-type layer 4, a SiGe strained alloy layer or Si / SiGe
It is also effective to use a strained alloy layer. As a result, a SODELFET having higher current driving capability can be obtained. The same applies to the following embodiments.

[0052] [Second Embodiment] mode of the first embodiment, p ^/ n - / p be the impurity concentration and thickness of the bonding structure as to optimize the gate length Lg to 50nm or less generations Then, the punch-through phenomenon between the source and the drain cannot be ignored.

FIG. 14 shows the SO 2 according to the second embodiment which can reliably prevent punch-through in consideration of such circumstances.
The DELFET structure is shown corresponding to FIG. The difference from FIG. 1 is that the p-type layer 9 as a halo region is buried immediately below the source and drain extension regions 7b. The other features are the same as in the first embodiment. By setting the impurity concentration and the thickness of the p-type layer 4, an FD-SODELFET can be obtained. If the impurity concentration of the p-type layer 4 is set higher, a PD-SODELFET can be obtained.

Conventionally, a method has been proposed in which oblique ion implantation is used to increase the impurity concentration at the center of the channel region for the purpose of preventing punch-through. However, in the case of the present invention, increasing the impurity concentration in the central portion of the channel region is an obstacle to reducing the electric field in the direction perpendicular to the substrate and realizing high carrier mobility. Therefore, in order to obtain the structure of FIG. 14, the p-type layer 9 is formed immediately below the extension region 7b by ion implantation in the vertical direction using the gate electrode 6 as a mask.
To form

In the method of forming a halo region by oblique ion implantation, an LSI in which gate electrodes are arranged at a fine pitch is used.
In the case of (1), an element in which the adjacent gate electrode is shaded and cannot be ion-implanted, that is, an element in which the short channel effect is not improved partially appears. On the other hand, if the p-type layer 9 which is a halo region is formed by ion implantation in the vertical direction as described above, there is no problem even when the gate electrodes are formed at a fine pitch, and the device structure of FIG. 14 is obtained. be able to. That is, it is possible to suppress the short channel effect when miniaturized and to guarantee the punch-through breakdown voltage.

In the embodiments described so far, the description has been made focusing on only one element region. SOD of the same element structure
When manufacturing an LSI in which ELFETs are integrated, the above-described p / n ⁻ / p structure may be formed uniformly by epitaxial growth and ion implantation over the entire surface of the substrate. However, by using selective ion implantation, a p / n ⁻ / p junction structure can be formed for each channel region of each element.

[Third Embodiment] FIG. 15 shows a SODELFE according to an embodiment in which a p / n ⁻ / p junction structure is selectively formed in a region immediately below a gate electrode by selective ion implantation.
The structure of T is shown corresponding to FIG. Unlike FIG. 1, the undoped silicon layer 10 grown epitaxially has a selective A
The n ⁻ -type layer 3 is formed by performing s ion implantation. Therefore, the extension region 7b of the source and drain diffusion layers 7
The bottom surface is in contact with n ⁻ type layer 3, and low resistance region 7 a has its bottom surface located inside undoped silicon layer 10.

The p-type layer 4 serving as a channel region is also
Similarly, it can be formed by selective B ion implantation. In this manner, by forming the n ⁻ -type layer 3 only immediately below the channel region, the source and drain low-resistance regions 7a are formed.
Is located inside the undoped (i) silicon layer 10, and the junction capacitance of the source and drain can be further reduced.

The above embodiments have mainly described the FD-SODELFET which is a fully depleted element. Therefore, the threshold voltage is determined by the work function of the gate electrode, and the degree of freedom in adjustment is small. However, in the case of LSI, generally, it is desired to improve circuit performance by mixing MISFETs having different threshold voltages to achieve higher performance.
For that purpose, it may be inconvenient to use only the fully depleted element.

On the other hand, if the selective ion implantation method described in the third embodiment is used, a plurality of MISFETs having different threshold voltages by changing the impurity concentration and thickness of the channel region can be used. Can be integrated. Such an embodiment will now be described.

[Fourth Embodiment] FIG. 16 shows an FD-SO
1 shows a structure in which a DELFET and a bulkFET are integrated. The FD-SODELFET has the structure described in the third embodiment. If this is described according to the manufacturing process, as in the manufacturing process of the first embodiment, first, an undoped silicon layer 10 is epitaxially grown on the silicon substrate 1 on which the p-type layer 2 is formed. After that, the element isolation insulating film 30 is formed in the element isolation region by STI.
Embed However, the p-type layer 2 may be formed by selectively ion-implanting only the SODELFET region without forming the entire surface of the substrate.

Thereafter, in the region of the FD-SODELFET, before forming the gate electrode 6, the n ⁻ -type layer 3 and the p-type layer 4 are sequentially formed by the same selective ion implantation as described in the fourth embodiment. . In the bulkFET region, the p-type layer 2 is formed by another selective ion implantation process into the undoped silicon layer 10 formed by epitaxial growth.
The p-type layer 31 is formed to a depth that reaches. Further, channel ion implantation is performed as needed. Thereafter, a gate electrode 6 is formed in each element region, and a source / drain extension region 7b and a low resistance region 7a are simultaneously formed. Thereby, FD-SODELFETs having different threshold voltages and b
UlkFETs can be integrated.

[Fifth Embodiment] FIG. 17 shows an FD-SO
Along with the DELFET, the channel region is not completely depleted even when the channel inversion layer is formed.
2 shows a structure in which T is integrated. FD-SODELFE
T is formed by a process similar to that of FIG. PD-S
For the ODELFET, under the ion implantation conditions different from those of the FD-SODELFET, the n ⁻ -type layer 3a and the p-type layer 4a
Are sequentially formed. However, the PD-SODELFET n ^-
The same conditions may be applied to the mold layer 3a and the n ⁻ -type layer 3 on the FD-SODELFET side. At least, PD-SODELF
The p-type layer 4a of ET is formed with a higher impurity concentration and thicker than the p-type layer 4 of FD-SODELFET.

In the case of FIG. 17, the p-type layer 4a is formed to be deeper than the diffusion depth of the source / drain extension region 7b and shallower than the low resistance region 7a. Further, the p-type layers 4a and n
^{The −} type layer 3 a is selectively formed immediately below the channel region, and both ends of the n ⁻ type layer 3 a are in contact with the extension region 7 b.

FIG. 18 shows the impurity concentration distribution of the p / n ⁻ / p structure portion of the PD-SODELFET in comparison with FIG. 2 of the FD-SODEL. p-type layer 4a
Is higher by about one digit than that of FIG. Thus, a PD-SODELFET having a higher threshold voltage than that of the FD-SODELFET and in which the p-type layer 4a is partially depleted when the channel inversion layer is formed can be obtained. At this time, the p-type layer 4a is surrounded by the depletion layer between the extension region 7b and the fully depleted n ⁻ -type layer 3a.
It becomes a floating p-type layer.

FIG. 19 shows the above-mentioned PD-SODELFE.
The graph shows the result obtained by calculating the drain voltage Vd-drain current Id characteristic of T by using the gate voltage Vg as a parameter. The gate length is Lg = 70 nm, and the power supply voltage is V
dd = 1 V, OFF current Ioff = 22.5 nA / μm
And As is apparent from the figure, the drain voltage Vd
A kink characteristic in which the drain current Id sharply rises in the middle of the process is obtained. This kink characteristic is a characteristic peculiar to PD-SODELFET obtained by apparently lowering the threshold voltage as a result of the partial depletion of the p-type layer 4a. Specifically, the kink characteristic is such that when a certain drain voltage is exceeded, holes generated by impact ionization become p-type.
It is obtained by accumulating in the mold layer 4a and apparently lowering the threshold voltage.

FIG. 20 shows a PD-SODELFET.
The change of the potential Vb of the body region (p-type layer 4a) when the gate voltage is fixed to Vg = 1V and the drain voltage Vd is time-varied in a pulsed manner as indicated by a broken line is shown in FIG. The thickness of 10 is shown as a parameter. The body potential Vb changes following the drain voltage Vd, and this changes with the p-type layer 4a.
Indicates that it is substantially floating.

[Sixth Embodiment] FIG. 21 shows a PD-SO
1 shows a structure in which a DELFET and a bulkFET are integrated. The channel body structure of the PD-SODELFET and the bulkFET is the same as that of the embodiment shown in FIG. 16, except that the impurity concentration of the p-type
DELFET is formed. PD-SODELFET
In this case, a polycrystalline silicon electrode can be used as the gate electrode 6. In FIG. 21, the PD-SODELFET
And the bulkFET are polycrystalline silicon gates. In general, when a bulk FET uses a metal electrode, the threshold becomes too high. According to this embodiment, it is possible to obtain a high current driving capability by setting the bulk FET to a low threshold.

In the FD-SODELFET and PD-SODELFET in FIGS. 16, 17 and 21, the p-type layer 9 is formed as a halo region immediately below the source / drain extension region 7b as in the embodiment of FIG. An embedded structure may be used.

Next, the FD-SODELF according to the present invention
A preferred circuit example combining an ET or PD-SODELFET and a bulkFET will be described.

[Seventh Embodiment] FIG. 22 shows a NAND gate constituted by n-channel transistors QN1 to QN3 connected in series and p-channel transistors QP1 to QP3 connected in parallel. Each of the n-channel transistors QN1 to QN3 has a gate connected to the input terminal and is connected in series between the output terminal and the reference potential terminal. The p-channel transistors QP1 to QP3 are connected in parallel between a power supply terminal and an output terminal, and each gate is connected to a corresponding input terminal. In such a circuit, when a normal MISFET is used, different substrate biases are applied to the vertically stacked transistors QN1 to QN3, and the threshold voltages are apparently different.

Therefore, n-channel transistors QN1-QN1
In the QN3 part, the influence of the substrate bias is smaller than that of the bulk FET, and the FD-SODE of the structure shown in FIG.
An LFET, a PD-SODELFET, or the PD-SODELFET shown in FIG. 17 is used. On the other hand, the p-channel transistors QP1 to QP3 have a p-channel bulkFQ having a structure similar to that of the bulkFET shown in FIG.
Use ET. As a result, operation stability and a high noise margin can be obtained.

[Eighth Embodiment] FIG. 23 shows a dynamic domino circuit. The n-channel transistors QN11 to QN13 connected in parallel between the nodes N1 and N2 are:
Switching elements whose gates are input terminals A, B, and C, respectively. A precharge p-channel transistor QP11 whose gate is controlled by a precharge signal PRE is provided between the node N1 and the power supply terminal. The clock CK is provided between the node N2 and the reference potential terminal.
N-channel transistor Q for activation driven by
N14 is provided. Node N1 is connected to inverter I
It is connected to the output terminal OUT via NV. A p-channel transistor QP12 controlled by the voltage of the output terminal OUT is further provided between the node N1 and the power supply terminal Vdd.

In such a dynamic circuit driven by a clock, high-speed operation becomes difficult if the capacitance of the node N1 is large. Also, the transistor QN11
When the junction capacitance of the source and drain of QN13 is large,
When the precharge transistor QP11 and the clock transistor QN14 are off and the inputs of A, B, and C are at "H", the accumulated charge at the node N1 is distributed, and the "H" level = Vdd is maintained. The potential of the power node N1 drops significantly below Vdd. Conversely, when the capacitance is small, the noise margin decreases. Therefore, it is necessary to optimize the capacitance of the node N1 in relation to the driving capability of the transistors QN11 to QN13.

Therefore, for example, transistors QN11-QN
In the portion of N13, the FD-S having the structure shown in FIG. 1 can keep the capacitance of the node N1 relatively small.
ODELFET or PD-SODELFET is used.
The transistors QN14, QP11, and QP12 have a bul having the same structure as the bulk FET shown in FIG.
A kFET is used.

Thus, it is possible to obtain a circuit capable of high-speed operation without lowering the noise margin.
That is, when the dynamic circuit of FIG. 23 is configured using only the bulk FET, the capacitance of the node N1 becomes large and it is difficult to charge and discharge the node N1 at high speed. However, the node N1 is connected to the transistors QN11 to QN13. By using a SODELFET that can keep the capacitance of the SODEL FET relatively small, high-speed operation can be achieved. Further, it is possible to reliably hold the potential to be held at the node N1.

On the other hand, all the dynamic circuits of FIG.
With the SODELFET, since the body region is in a floating state, a parasitic bipolar transistor effect occurs, and the amount of charge that can be stored in the node N1 decreases, so that the noise resistance deteriorates. Therefore, SODELFE is added to the transistors QN11 to QN13.
By using T and using a bulkFET in other portions, it is possible to optimize the noise margin and the high-speed performance, which are in a trade-off relationship.

Further, differential amplifiers are often used for analog circuits, memory sense amplifier circuits, and the like. For example, a differential amplifier composed of two CMOS circuits has two C
It is important that the threshold values of the MOS circuits are uniform.
However, in the case of the SODELFET according to the present invention, since the channel body region is floating, the threshold value may be deviated due to the past history, and the threshold values of the two CMOS circuits must always be aligned. It is not easy. Therefore, even in the LSI using the SODELFET according to the present invention, the difference amplifier
It is preferable to selectively use such as using a kFET.

The FD-SODELF according to the present invention
In an LSI using ET, when a p / n ⁻ / p structure is provided separately for each element, a substrate bias for selectively applying a substrate bias for adjusting a threshold voltage to a lower p-type layer is provided. It is also effective to provide an application circuit. In particular,
As shown in FIG. 14, the source and drain extension regions 7
FD-SO in which a p-type layer 9 which is a halo region is formed below
It has been confirmed that the threshold value of the DELFET can be adjusted by applying a bias to the p-type layer 2. FIG. 24 shows the FD-SODELFET shown in FIG.
The substrate bias voltage Vsu applied to the p-type layer 2
The graph shows a drain current Id-gate voltage Vg characteristic when b is changed. From this characteristic, if the p-type layer 2 is provided separately for each element and a substrate bias applying circuit is connected thereto, an LSI in which FD-SODELFETs having different threshold voltages are integrated can be obtained.

Ninth Embodiment The NAND gate circuit shown in FIG. 22 and the dynamic domino circuit shown in FIG.
It can be configured by a combination of SOIFET and bulkFET using an OI substrate. FIG.
1 shows an integrated structure of an SOIFET and a bulkFET using an OI substrate. The partial SOI substrate has an SOI region in which an insulating film 102 such as a silicon oxide film is buried under a thin silicon layer 103 on a silicon substrate 101, and a bulk region in which an insulating film is not buried.

An SOIFET is formed on the silicon layer 103 in the SOI region of such a partial SOI substrate. SOI
The FET has a gate electrode 202 formed on a silicon layer 103 with a gate insulating film 201 interposed therebetween. Source,
The drain diffusion layer 203 is formed at a depth reaching the insulating film 102. When the silicon layer 103 is thin, the SOI
The FET becomes a fully depleted element.

In the bulk region, an n-type (or p-type) well 301 is formed, a gate electrode 303 is formed on the well 301 via a gate insulating film 302, and a source / drain diffusion layer 304 is formed. .

The n-channel transistors QN1-Q3 of the NAND gate circuit of FIG. 22 are formed by the SOIFET of FIG. P-channel transistors QP1-QP3
Is formed by the bulk FET of FIG. As a result, high stability and a high noise margin can be obtained for the same reasons as described in the seventh and eighth embodiments.

The n-channel transistors QN11 to QN13 of the dynamic domino circuit of FIG.
It is formed by an IFET. p-channel transistor QP
11, QP12 and n-channel transistor QN14
Is formed by the bulk FET of FIG. Thus, high-speed operation can be performed without reducing the noise margin for the same reason as described in the eighth embodiment.

[0085]

As described above, according to the present invention, it is possible to provide a semiconductor device having a transistor capable of miniaturization and high performance with a simpler structure using a bulk semiconductor.

[Brief description of the drawings]

FIG. 1 shows a SODELFET according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view showing the structure of FIG.

FIG. 2 is a diagram showing an impurity concentration distribution in a depth direction of a channel region of the SODELFET.

FIG. 3 is a graph showing the relationship between the threshold voltage roll-off value δVth of a SODELFET according to the present invention and the thickness of a p-type layer;
It is a figure shown in comparison with ET.

FIG. 4 is a diagram showing a relationship between a threshold voltage roll-off value δVth and an electron mobility μe of an SODELFET according to the present invention and an n ⁻ -type layer thickness.

FIG. 5A is a diagram showing p / n ⁻ of the SODELFET of the embodiment.
FIG. 14 is a cross-sectional view showing an element isolation step in a manufacturing step for obtaining a / p structure.

FIG. 5B is a cross-sectional view showing a p-type layer ion implantation step and a silicon layer epitaxial growth step in the same manufacturing process.

FIG. 5C is a sectional view showing an n ⁻ -type layer ion implantation step in the same manufacturing step.

FIG. 5D is a sectional view showing a p-type layer ion implantation step in the same manufacturing step.

FIG. 6A is a diagram showing p / n ⁻ of the SODELFET of the embodiment.
FIG. 10 is a cross-sectional view showing an element isolation step in another manufacturing step for obtaining a / p structure.

FIG. 6B is a sectional view showing a first silicon layer epitaxial step in the manufacturing process.

FIG. 6C is a sectional view showing an n ⁻ layer ion implantation step in the same manufacturing step.

FIG. 6D is a sectional view showing a second silicon layer epitaxial step in the manufacturing process.

FIG. 6E is a sectional view showing the p-layer ion implantation step in the same manufacturing step.

FIG. 7 integrates the SODELFET of the embodiment.
/ N in the manufacturing process for ^-/ P structure forming step;
It is sectional drawing which shows an element isolation process.

FIG. 8 shows a gate electrode forming step and a source in the same manufacturing step.
It is sectional drawing which shows a drain extension region formation process.

FIG. 9 is a cross-sectional view showing a step of forming a gate sidewall insulating film in the same manufacturing process.

FIG. 10 is a cross-sectional view showing a step of selectively epitaxially growing source and drain regions in the same manufacturing process.

FIG. 11 is a cross-sectional view showing a step of forming source and drain low-resistance regions in the same manufacturing process.

FIG. 12 is a cross-sectional view showing a step of forming an interlayer insulating film and a contact plug in the same manufacturing process.

FIG. 13 is a diagram showing a relationship between a gate length and a threshold voltage roll-off value.

FIG. 14 is a cross-sectional view showing a structure of a SODELFET according to another embodiment.

FIG. 15 is a sectional view showing a structure of a SODELFET according to another embodiment.

FIG. 16 is a cross-sectional view showing an integrated structure of an FD-SODELFET and a bulk FET.

FIG. 17: FD-SODELFET and PD-SODEL
FIG. 3 is a cross-sectional view showing an integrated structure of the FET.

18 is a diagram showing a channel region impurity concentration distribution of the PD-SODELFET of FIG. 17;

19 is a diagram showing drain voltage-drain current characteristics of the PD-SODELFET of FIG.

20 is a diagram showing the drain voltage dependence of the body potential of the PD-SODELFET of FIG.

FIG. 21 is a PD-SODELFE according to another embodiment.
It is sectional drawing which shows the integrated structure of T and bulk FET.

FIG. 22 is a diagram showing a preferred circuit example to which the present invention is applied.

FIG. 23 is a diagram showing another preferred circuit example to which the present invention is applied.

FIG. 24 is a diagram showing the effect of applying a substrate bias to the FD-SODELFET according to the present invention.

FIG. 25 is a diagram showing an integrated structure of an SOIFET and a bulk FET according to another embodiment.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... p-type layer, 3 ... n ^- type layer, 4 ... p
Mold layer (channel region), 5: gate insulating film, 6: gate electrode, 6a: metal electrode, 6b: polycrystalline silicon electrode,
7: source and drain diffusion layers, 7a: low resistance region, 7b
... Extended region, 8... Sidewall insulating film, 10, 11... Silicon layer (epitaxially grown layer).

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification code FI Theme coat ゛ (Reference) H01L 27/092 F-term (Reference) 5F048 AA00 AA01 AA05 AA08 AB03 AC00 AC01 AC03 BA02 BA03 BA05 BA07 BA09 BB05 BB09 BB12 BB14 BB19 BC06 BD04 BD09 BE04 BF07 BG14 5F140 AA21 AA39 AB01 AB03 AC16 AC28 BA01 BA16 BA17 BB13 BC06 BC12 BF07 BF10 BF11 BF14 BF17 BF20 BF21 BF24 BG08 BG14 BH06 BH15 BH36 BH38 BH40 BJ17BK

Claims (46)

[Claims] A semiconductor substrate; a gate electrode formed on a surface of the semiconductor substrate via a gate insulating film; and a semiconductor substrate formed to face the semiconductor substrate with a channel region immediately below the gate electrode interposed therebetween. A source and drain diffusion layer comprising a low resistance region, an extension region having a lower impurity concentration and shallower than the low resistance region formed to extend from the low resistance region to the channel region side; and the source and drain diffusion layers A first impurity-doped layer of a first conductivity type formed in the channel region between the first and second impurity-doped layers of a second conductivity type formed below the first impurity-doped layer; A third impurity-doped layer of a first conductivity type formed below the second impurity-doped layer; and a junction depth of the first impurity-doped layer is larger than that of the source and drain diffusion layers. The second impurity-doped layer has an impurity concentration and a thickness such that the second impurity-doped layer is completely depleted by a built-in potential generated between the first and third impurity-doped layers. A semiconductor device characterized by being set. 2. The semiconductor device according to claim 1, wherein the first impurity-doped layer has an impurity concentration and a thickness set so as to be completely depleted when a channel inversion layer is formed. 3. The semiconductor device according to claim 1, wherein the first impurity-doped layer has an impurity concentration and a thickness set so as to be partially depleted when a channel inversion layer is formed. 4. The first and second impurity doped layers,
2. The semiconductor device according to claim 1, wherein an impurity is ion-implanted into an undoped semiconductor layer epitaxially grown on the semiconductor substrate on which the third impurity-doped layer is formed. 5. The semiconductor device according to claim 1, wherein said second impurity-doped layer is selectively formed in a region immediately below said gate electrode. 6. The second impurity-doped layer is selectively formed in a region directly below the gate electrode in the undoped semiconductor layer, and the source and drain diffusion layers have a bottom surface of the low-resistance region, 5. The semiconductor device according to claim 4, wherein the semiconductor device is located in the undoped semiconductor layer, and a bottom surface of the extension region is formed so as to be in contact with the second impurity doped layer. 7. The semiconductor device according to claim 1, wherein a fourth impurity-doped layer of a first conductivity type is buried in contact with an extended region of said source and drain diffusion layers. 8. The semiconductor device according to claim 1, wherein the low resistance regions of the source and drain diffusion layers are formed to protrude above the position of the gate insulating film. 9. The semiconductor device according to claim 1, wherein said gate electrode has a metal film in contact with a gate insulating film. 10. The semiconductor device according to claim 2, wherein said gate electrode is a metal electrode. 11. The semiconductor device according to claim 3, wherein said gate electrode is a polycrystalline silicon electrode. 12. A source formed to face a semiconductor substrate, a gate electrode formed on a surface of the semiconductor substrate via a gate insulating film, and a channel region immediately below the gate electrode on the semiconductor substrate. And a drain diffusion layer; a first conductivity type first impurity doped layer formed in the channel region between the source and drain diffusion layers; and a second impurity layer formed below the first impurity doped layer. A second impurity-doped layer of a conductivity type; and a third impurity-doped layer of a first conductivity type formed below the second impurity-doped layer; The depth is set to be the same as or shallower than that of the source and drain diffusion layers. The second impurity-doped layer has a junction depth with the third impurity-doped layer that is in contact with the source and drain diffusion layers. Deeper than the depth and semiconductor device characterized by being set the impurity concentration and thickness so as to fully depleted by a built-in potential occurring between the first and third impurity doped layer of. 13. The source and drain diffusion layers include a low resistance region and an extension region having a lower impurity concentration and shallower than the low resistance region formed to extend from the low resistance region to the channel region side. 13. The semiconductor device according to claim 12, wherein a bottom surface of said low-resistance region is located inside said second impurity-doped layer. 14. The semiconductor device according to claim 12, wherein the first impurity-doped layer has an impurity concentration and a thickness set so as to be completely depleted when a channel inversion layer is formed. 15. An impurity concentration and a thickness of the first impurity-doped layer are set so as to be partially depleted when a channel inversion layer is formed.
13. The semiconductor device according to claim 1. 16. The first and second impurity-doped layers are formed by ion-implanting impurities into an undoped semiconductor layer epitaxially grown on a semiconductor substrate on which the third impurity-doped layer has been formed. The semiconductor device according to claim 12, wherein: 17. The semiconductor device according to claim 12, wherein said second impurity-doped layer is selectively formed in a region immediately below said gate electrode. 18. The undoped semiconductor layer, wherein the second impurity-doped layer is selectively formed in a region directly below the gate electrode of the undoped semiconductor layer, and the source and drain diffusion layers have a bottom surface in the undoped semiconductor layer. A low-resistance region, and an extended region formed to extend from the low-resistance region toward the channel region and having a bottom surface in contact with the second impurity-doped layer and having a lower impurity concentration and shallower than the low-resistance region. 17. The semiconductor device according to claim 16, wherein the semiconductor device is configured. 19. The semiconductor device according to claim 13, wherein a fourth impurity-doped layer of a first conductivity type is buried in contact with the extended region of said source and drain diffusion layers. 20. The semiconductor device according to claim 13, wherein the low resistance regions of the source and drain diffusion layers are formed to protrude above the position of the gate insulating film. 21. The semiconductor device according to claim 12, wherein said gate electrode has a metal film in contact with a gate insulating film. 22. The semiconductor device according to claim 14, wherein said gate electrode is a metal electrode. 23. The semiconductor device according to claim 15, wherein said gate electrode is a polycrystalline silicon electrode. 24. A semiconductor substrate, a gate electrode formed on a surface of the semiconductor substrate via a gate insulating film, and formed so as to face the semiconductor substrate with a channel region immediately below the gate electrode interposed therebetween. A source and drain diffusion layer comprising a low resistance region, an extension region having a lower impurity concentration and shallower than the low resistance region formed to extend from the low resistance region to the channel region side; and the source and drain diffusion layers A first impurity-doped layer of a first conductivity type formed in the channel region between the first and second impurity-doped layers of a second conductivity type formed below the first impurity-doped layer; A third impurity-doped layer of a first conductivity type formed below the second impurity-doped layer, wherein the first impurity-doped layer has a junction depth of the source and drain diffusion layers. The impurity concentration and the thickness are set so as to be selectively formed in a state deeper than that of the extension region and to be partially depleted when forming the channel inversion layer. The impurity concentration and the thickness are selectively formed so as to be in contact with the extended regions of the source and drain diffusion layers, and are set to be completely depleted by a built-in potential generated between the first and third impurity dopings. A semiconductor device characterized by being performed. 25. The first impurity-doped layer is surrounded by a depletion layer formed between the extended region of the source and drain diffusion layers and the second impurity-doped layer that is completely depleted, and floats. 3. The state of claim 2
5. The semiconductor device according to 4. 26. A gate insulating film interposed between a semiconductor substrate, a first source and drain diffusion layer formed apart from each other on the semiconductor substrate, and the first source and drain diffusion layer of the semiconductor substrate. A first transistor having a first gate electrode formed thereon, a second source and drain diffusion layer formed apart from the semiconductor substrate and the second source and drain diffusion layer of the semiconductor substrate The second formed between the gate insulating film
A second transistor having a gate electrode of the first type, wherein the first transistor has a first impurity-doped layer of a first conductivity type formed in a channel region between the first source and drain diffusion layers; A second conductivity type second impurity doped layer formed below the first impurity doped layer; and a first conductivity type third impurity doped layer formed below the second impurity doped layer. And the first impurity-doped layer has a junction depth equal to or smaller than that of the first source and drain diffusion layers, and is completely depleted or partially depleted when a channel inversion layer is formed. The second impurity-doped layer has a junction depth between the second impurity-doped layer and the third impurity-doped layer that is deeper than that of the first source and drain diffusion layers. , The first and 3 wherein a impurity concentration and thickness are set to fully depleted by a built-in potential created between the impurity-doped layer. 27. The semiconductor device according to claim 27, wherein the second transistor is provided on a portion of the semiconductor substrate immediately below the second gate electrode.
27. The semiconductor device according to claim 26, further comprising a first conductivity type bulk layer that is an impurity doped layer deeper than the source and drain diffusion layers. 28. The second transistor, wherein: a fourth impurity-doped layer of a first conductivity type formed in the channel region between the second source and drain diffusion layers; and a fourth impurity-doped layer. A fifth impurity-doped layer of the second conductivity type formed below the layer; and a sixth impurity-doped layer of the first conductivity type formed below the fifth impurity-doped layer. 4 has a junction depth of the first impurity doped layer.
The impurity concentration and the thickness are set so as to be deeper than that of the first impurity-doped layer of the transistor and to be partially depleted when the channel inversion layer is formed, and the fifth impurity-doped layer is The junction depth with the impurity-doped layer is deeper than the junction depth of the second source and drain diffusion layers, and is completely depleted by a built-in potential generated between the fourth and sixth impurity-doped layers. 27. The semiconductor device according to claim 26, wherein an impurity concentration and a thickness are set in the semiconductor device. 29. A NAND gate circuit formed on a semiconductor substrate, comprising: a plurality of n-channel transistors connected in series between a reference terminal and an output terminal, each gate being connected to an input terminal; A plurality of p-channel transistors connected in parallel between power supply terminals and having respective gates connected to corresponding input terminals, wherein the n-channel transistor is formed on a surface of the semiconductor substrate via a gate insulating film. A first gate electrode, a first source and drain diffusion layer formed so as to face the semiconductor substrate with a channel region immediately below the first gate electrode interposed therebetween, and a first source and drain diffusion layer. A first p-type impurity-doped layer formed in the channel region between the layers, and an n-type impurity layer formed under the first p-type impurity-doped layer. And a second p-type impurity-doped layer formed below the n-type impurity-doped layer, wherein the first p-type impurity-doped layer has a junction depth of the first source. The n-type impurity-doped layer has a junction depth with the second p-type impurity-doped layer greater than a junction depth of the first source and drain diffusion layers. The impurity concentration and the thickness are set to be deep and completely depleted by a built-in potential generated between the first and second p-type impurity-doped layers. A second gate electrode formed on the surface via a gate insulating film, a second source and a second source electrode formed on the semiconductor substrate so as to face each other with a channel region immediately below the second gate electrode interposed therebetween; NA to the drain diffusion layer, characterized in that it has a second source and drain diffusion layers bulk layer of the second source and the deep p-type than the drain diffusion layer formed in the channel region between the
ND gate circuit. 30. A dynamic circuit formed on a semiconductor substrate, comprising: a plurality of switching transistors provided between a first node and a second node, the gates receiving an input signal; A transistor for precharging the node to a predetermined potential;
An activation transistor whose gate is controlled by a clock signal to connect the second node to a reference terminal; wherein the switching transistor is formed on a surface of the semiconductor substrate via a gate insulating film. A first source and drain diffusion layer formed so as to oppose the semiconductor substrate with a channel region immediately below the first gate electrode interposed therebetween; and a first source and drain diffusion layer. A first impurity-doped layer of a first conductivity type formed in the channel region, a second impurity-doped layer of a second conductivity type formed under the first impurity-doped layer, And a third impurity-doped layer of a first conductivity type formed below the impurity-doped layer of (i).
The second impurity-doped layer has a junction depth with the third impurity-doped layer that is equal to or smaller than that of the source and drain diffusion layers. The impurity concentration and the thickness are set so as to be completely depleted by a built-in potential generated between the first and third impurity-doped layers. A second gate electrode formed on the surface of the semiconductor substrate with a gate insulating film interposed therebetween, and a second gate electrode formed to face the semiconductor substrate with a channel region immediately below the second gate electrode interposed therebetween. Source and drain diffusion layers, and second source and drain formed in the channel region between the second source and drain diffusion layers Dynamic circuit, characterized in that it comprises a deeper bulk layer goldenrod. 31. A NAND gate circuit formed on a semiconductor substrate, comprising: a plurality of n-channel transistors connected in series between a reference terminal and an output terminal, each gate being connected to an input terminal; A plurality of p-channel transistors connected in parallel between power supply terminals and having respective gates connected to corresponding input terminals, wherein the semiconductor substrate has an SOI structure region in which an insulating film is embedded at a predetermined depth position; A bulk region, wherein the n-channel transistor is formed as a SOIFET in the SOI structure region, and the p-channel transistor is formed as a bulk FET in the bulk region.
D gate circuit. 32. A dynamic circuit formed on a semiconductor substrate, comprising: a plurality of switching transistors provided between a first node and a second node, the gates receiving an input signal; A transistor for precharging the node to a predetermined potential;
An activation transistor whose gate is controlled by a clock signal to connect the second node to a reference terminal, wherein the semiconductor substrate has an SOI structure region in which an insulating film is buried at a predetermined depth position and a bulk region Wherein the switching transistor is formed as an SOIFET in the SOI structure region, and the precharge transistor and the activation transistor are formed as a bulk FET in the bulk region. . 33. A step of epitaxially growing a first semiconductor layer not doped with an impurity on a semiconductor substrate having a first impurity-doped layer of a first conductivity type on at least a surface thereof; Implanting a second impurity-doped layer of a second conductivity type in contact with the first impurity-doped layer; and ion-implanting a surface portion of the first semiconductor layer to form the second impurity-doped layer. Forming a first conductivity type third impurity doped layer in contact with the doped layer; forming a gate electrode on the third impurity doped layer via a gate insulating film; and forming the gate on the semiconductor substrate. In a state of being self-aligned with the electrode, it is deeper than the junction surface between the third impurity-doped layer and the second impurity-doped layer and from the junction surface between the second impurity-doped layer and the first impurity-doped layer. The method of manufacturing a semiconductor device characterized by a step of forming source and drain diffusion layers having had junction depth. 34. The step of forming the source and drain diffusion layers comprises: ion-implanting the third impurity-doped layer using the gate electrode as a mask to make the source and drain extension deeper than the third impurity-doped layer. Forming a fourth impurity-doped layer to be a region, forming a sidewall insulating film on a sidewall of the gate electrode, and selectively epitaxially growing a second semiconductor layer on the fourth impurity-doped layer; Using the gate electrode and the sidewall insulating film as a mask,
Forming a fifth impurity-doped layer that is deeper with a higher impurity concentration than the fourth impurity-doped layer and that becomes a source and drain low-resistance region by performing ion implantation into the semiconductor layer. A method for manufacturing a semiconductor device according to claim 33. 35. The method according to claim 33, further comprising a step of forming an element isolation insulating film on the semiconductor substrate prior to the step of epitaxially growing the first semiconductor layer. 36. The method according to claim 33, further comprising a step of forming an element isolation insulating film on the semiconductor substrate after the step of forming the third impurity-doped layer. 37. The semiconductor device according to claim 37, wherein the second impurity-doped layer has an impurity concentration and a thickness that are completely depleted by a built-in potential between the first and third impurity-doped layers. 34. The method for manufacturing a semiconductor device according to claim 33. 38. The method according to claim 33, wherein the third impurity-doped layer is formed with an impurity concentration and a thickness necessary for complete depletion when forming the channel inversion layer. 39. The method according to claim 33, wherein the third impurity-doped layer is formed with an impurity concentration and a thickness necessary for partially depleting the channel inversion layer.
The manufacturing method of the semiconductor device described in the above. 40. A step of epitaxially growing a first semiconductor layer not doped with an impurity on a semiconductor substrate having a first impurity-doped layer of a first conductivity type on at least a surface thereof; Implanting to form a second impurity-doped layer of a second conductivity type in contact with the first impurity-doped layer; and a second semiconductor layer having no impurity doped on the second impurity-doped layer Epitaxially growing, a step of performing ion implantation into the second semiconductor layer to form a third impurity doped layer of a first conductivity type in contact with the second impurity doped layer, and a step of performing the third impurity doping. Forming a gate electrode on the layer with a gate insulating film interposed therebetween; and forming the third impurity-doped layer and the second Forming source and drain diffusion layers deeper than the junction surface of the pure doped layer and shallower than the junction surface between the second impurity-doped layer and the first impurity-doped layer. Manufacturing method of a semiconductor device. 41. The step of forming the source and drain diffusion layers comprises: ion-implanting the third impurity-doped layer using the gate electrode as a mask, so that the source and drain extensions are deeper than the third impurity-doped layer. Forming a fourth impurity-doped layer to be a region, forming a sidewall insulating film on a sidewall of the gate electrode, and selectively epitaxially growing a third semiconductor layer on the fourth impurity-doped layer; Using the gate electrode and the sidewall insulating film as a mask,
Forming a fifth impurity-doped layer that is deeper with a higher impurity concentration than the fourth impurity-doped layer and that becomes a source and drain low-resistance region by performing ion implantation into the semiconductor layer. A method for manufacturing a semiconductor device according to claim 40. 42. The method according to claim 40, further comprising a step of forming an element isolation insulating film on the semiconductor substrate prior to the step of epitaxially growing the first semiconductor layer. 43. The method according to claim 40, further comprising a step of forming an element isolation insulating film on the semiconductor substrate after the step of forming the third impurity-doped layer. 44. The semiconductor device according to claim 44, wherein the second impurity-doped layer is formed with an impurity concentration and a thickness that are completely depleted by a built-in potential between the first and third impurity-doped layers. 40. The method for manufacturing a semiconductor device according to 40. 45. The method according to claim 40, wherein the third impurity-doped layer is formed with an impurity concentration and a thickness necessary for complete depletion when forming a channel inversion layer. 46. The semiconductor device according to claim 40, wherein the third impurity-doped layer is formed with an impurity concentration and a thickness necessary to partially deplete the channel inversion layer.
The manufacturing method of the semiconductor device described in the above.