JPH07105710B2 - Logic circuit - Google Patents

Description

The present invention relates to a logic circuit based on a differential amplifier, and is particularly suitable for use in a change point detection circuit of a parallel comparison type A / D converter. Regarding logic circuits.

(Prior Art) Conventionally, as a logic circuit of this type, NOR (O
There is an R) type circuit, and a circuit in which differential switches are vertically stacked as shown in FIG.

The logic circuit of FIG. 2 includes transistors Q ₅ to Q ₇ forming a differential pair, load resistors R ₃ and R ₄ , a constant current source 10, a bias circuit.
11 (internal structure is shown as an example). Now, the input voltages of the digital input terminals 7 and 8 are both
High level state "H" for the threshold voltage obtained by the bias circuit 11 and applied to the base of the transistor Q _7.
(Hereinafter, simply referred to as “H”), the transistors Q ₅ and Q ₆ are both conductive, the transistor Q ₇ is turned on and off, and the current I of the constant current source 10 is the power line 12 and the load. resistance
It flows in the path of R ₃ , the transistors Q ₅ and Q ₆ , and the power supply line 13. Therefore, assuming that the potential of the power supply line 12 is V _CC and the resistance values of the load resistors R ₃ and R ₄ are R, the potentials of the output terminals 9a and 9b become V _CC and V _CC -RI, respectively. Where output terminal 9a
When the potentials of 9 and 9b are V _CC , it is "H", and when V _CC -RI is the low level state "L" (hereinafter simply referred to as "L"), the input terminals 7 and 8 and the output terminals 9a and 9a Between 9b, following the same considerations as above, the relationship shown in Table 1 is established.

By the way, in the change point detection circuit of the parallel comparison type A / D converter, there is a logical operation that the output state in the case of a combination of certain input states is different from the output state in the case of all other combinations. This is necessary, and in the conventional example shown in FIG. 2, the above logical operation is executed as can be seen from the input / output relationship in Table 1.

Further, another conventional logic circuit shown in FIG. 3 is provided with transistors Q ₈ and Q ₉ , transistors Q ₁₀ and Q ₁₁ , load resistors R ₅ and R ₆ , and a constant current source 17, which form a differential pair, respectively. It is a circuit in which differential pairs are vertically stacked. Here, the digital input terminals 14b and 15b are opposite phase input terminals to the digital input terminals 14a and 15a, respectively.

Now, when both the digital input terminals 14a and 15a are "L" and both the digital input terminals 14b and 15b are "H",
Transistors Q ₈ and Q _{10 in} broken or open state, transistor Q
₉ and Q ₁₁ become conductive, and the current I of the constant current source 17 is
Power line 19, load resistance R ₆ , transistor Q ₉ , transistor
It flows in the route of Q ₁₁ and power line 20. Therefore, the states of the output terminals 16a and 16b are "L" and "H", respectively. Considering all digital input combinations below, digital input terminals 14a, 14b, 15a and 15b and output terminals 16a and 1
The relationship shown in Table 2 is established between 6b, and the same logical operation as in the example of FIG. 2 is performed.

(Problems to be Solved by the Invention) In the above-described conventional logic circuit, a bias circuit for generating a threshold voltage applied to the logic circuit is required, which causes an increase in the number of elements in consideration of integration, Furthermore, if the above threshold voltage fluctuates due to temperature characteristics, etc., "H"
There is a problem that the voltage margin is different between the level and the “L” level, and thus incorrect calculation may be performed (see FIG. 2). Further, in the conventional logic circuit as shown in FIG. 3, it is necessary to provide a potential difference between the potentials of the input terminals 14a and 14b and the input terminals 15a and 15b in order to prevent the calculation speed from deteriorating. A level shift circuit as shown as an example is required. That is, the circuit of FIG. 3 has a problem that the number of elements and power consumption increase when integrated into an integrated circuit.

(Means for Solving Problems) A logic circuit provided by the present invention in order to solve the above problems includes a first differential amplifier having first and second transistors as active elements, and a third differential amplifier. And a second differential amplifier having a fourth transistor as an active element, wherein the first and fourth transistors share a first load, and the second and third transistors include a second load. , The first to fourth transistors share a constant current source, a first complementary signal is input to the first and second transistors, and a second complementary signal is input to the third and fourth transistors. Complementary signals are input, and at least one of a connection point between the first and fourth transistors and the first load or a connection point between the second and third transistors and the second load is input. The threshold voltage can be changed to the connection point It is characterized in that another logic circuit is connected.

(Operation) In the present invention, the two differential amplifiers share the load and the constant current source, and the operating currents of the respective differential amplifiers are used in the addition form to provide a logical output.

(Example) Next, this invention is demonstrated with reference to drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention. In this embodiment, the digital input terminals 1a and 2a are input terminals of opposite phases to the digital input terminals 1b and 2b, respectively, and outputs are taken out from the output terminals 3a and 3b.

Now, when both digital input terminals 1a and 2a are "H" (that is, both digital input terminals 1b and 2b are "L")
In this case, the transistors Q ₁ and Q ₄ are both conductive, the transistors Q ₂ and Q ₃ are both on and off, and the current 2I of the constant current source 4 flows through the power supply line 5 and the load resistance R ₁ After the current I is shunted to Q ₁ and Q ₄ , respectively, the current 2 I flows to the power supply line 6 again. That is, the operating currents of the first differential amplifier composed of the transistors Q ₁ and Q ₂ and the _second differential amplifier composed of the transistors Q ₃ and Q ₄ are added at the common load resistor R ₁ . Accordance connexion, the value of the load resistor R ₁ and R ₂ R, when the potential of the power supply line 5 and V _CC, the potential of the output terminal 3a becomes V _CC, the potential of the output terminal 3b becomes V _CC -2RI. Set the output voltage threshold voltage to V _CC −R
If the potential of the output terminals is high, it is expressed as “H”, and if the potential of the output terminals is small, it is expressed as “L” according to the magnitude relation with the potentials of the output terminals 3a and 3b. It becomes H "and" L ". Similarly, considering the relationship between the digital input and output in all cases, the relationship shown in Table 3 is established between the digital input terminals 1a, 1b, 2a and 2b and the output terminals 3a and 3b.

Therefore, as can be seen from Table 3, the calculation is performed that the output state in the case of one input state is different from the output state in the case of all other input states.

Further, a logic circuit having a variable threshold voltage is connected to the output of this embodiment. That is, assuming that the threshold voltage of the output voltage in the above embodiment is V _CC −3RI / 2, when both the digital input terminals 1a and 2a are “H”, the states of the output terminals 3a and 3b are respectively “ H "and" L ", digital input terminal 1a is" H ", digital input terminal 2a is" L ",
The states of the output terminals 3a and 3b are both "H". Similarly, if all cases are taken into consideration, Table 4 holds.

From Table 3, the relationship between digital input terminal and output terminal is 1
AND operation for a, 2a and 3a, NOR operation for 1a, 2a and 3b, OR operation for 1a, 2a and 3a, NA for 1a, 2a and 3b from Table 4
This means that each ND operation is being performed. That is,
By connecting a logic circuit whose threshold value is variable to the output terminal in FIG. 1, the above logic circuit is AND, NOR, OR
Each logical operation of NAND and NAND can be executed.

As described above, according to the present invention, the parallel comparison type A / D
In the logical operation circuit such as the change point detection circuit of the converter, the bias circuit or the level shift circuit which is conventionally required is unnecessary, and when considering the integrated circuit, it is possible to reduce the number of elements and the power consumption. There is.

In addition, the logic circuit of the present invention can perform various logic operations such as AND, NOR, OR, and NAND operations by including another logic circuit whose threshold value can be changed. This has the effect of making selections possible.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 and FIG.
The figure is a circuit diagram of a conventional logic circuit example. 1a, 1b to 3a, 3b, 7,8,14a, 14b, 15a, 15b …… Digital input terminal, 3a, 3b, 9a, 9b, 16a, 16b …… Output terminal, 4,10,17 ……
A constant current source, 5,6,12,13,19,20 ...... power supply line, 11 ...... bias circuit, 18 ...... level shift circuit, Q ₁ to Q ₁₁ ...... transistor, R ₁ to R ₆ ...... resistance .

Claims (1)

[Claims] 1. A first differential amplifier including first and second transistors as active elements, and a second differential amplifier including third and fourth transistors as active elements.
And the fourth transistor share a first load, the second and third transistors share a second load, the first to fourth transistors share a constant current source, and the first And the second complementary signal is input to the second transistor, the second complementary signal is input to the third and fourth transistors, and the first and fourth transistors are connected to the first load. Another logic circuit whose threshold voltage can be changed is connected to a connection point or at least one of the connection points of the second and third transistors and the second load. Logic circuit.