JP2785943B2 - Emitter-coupled logic circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an emitter-coupled logic circuit.

[Conventional technology]

 FIG. 2 is a circuit diagram showing an example of the related art.

In FIG. 3, Q1 to Q10 are transistors, and R1 to R6 are resistors.
V _DD is the positive power supply, V _SS is the negative power supply, OUT is the output terminal, IN−A, IN−
B indicates an input terminal.

The constant voltage base bias voltage V _REF of the transistor Q3 is
The collector current I ₂ and the resistor R5 of the transistor Q5, VDD
Set by-(I ₂ × R5). Incidentally, controlled by I _S is a constant current I ₁ obtained by dividing the base-emitter voltage difference between the transistors Q6, Q7 with resistance 4 (collector current ie transistors Q4) common emitter to flow a constant current of the current and the differential circuit .

When a signal equal to or higher than the constant voltage _VREF is input to the input terminal IN-A or IN-B, the transistor Q1 or Q2 is turned on, a signal having the same level as _VDD is output to the output terminal, and the input terminal IN When a signal equal to or lower than the constant voltage V _REF is input to −A and IN−B, both the transistors Q1 and Q2 are turned off, and the output terminal OUT has V _DD
This is a logical sum (OR) circuit that outputs a voltage of − (I _S × R1).

[Problems to be solved by the invention]

The conventional emitter-coupled logic circuit described above
It was primarily determined the constant current I ₁ so as to increase the value of constant current I _S of the differential circuit to operate at high speed. Therefore, there is a drawback that the current consumption is always large even when no signal is input to the emitter-coupled logic circuit or when the circuit is used at a low speed operation.

[Means for solving the problem]

An emitter-coupled logic circuit according to the present invention includes a first resistor (R4) for setting a constant current value of a constant current generator.
A second resistor (R5) for generating a comparison reference voltage of the differential amplifier (Q2, Q3, Q4) with respect to a signal input terminal based on the constant current value; and a load of the differential amplifier. An emitter-coupled logic circuit including a third resistor (R2), wherein the first resistor, the second resistor, and the third resistor have the first resistor and the third resistor for increasing resistance values of the third resistor at the same time. A fourth resistor (R102), a fifth resistor (R101), and a sixth resistor (R10) added to the second resistor and the third resistor.
0), the first transistor (104), the second transistor (Q103), and the third transistor (Q1) that perform ON / OFF operation based on the voltage supplied to the current consumption adjustment terminal POWER SAVE.
02) is connected to a common base, a circuit that short-circuits or opens both ends of the fourth resistor in response to a change in the internal resistance of the first transistor, A fourth transistor (Q1) that short-circuits or opens both ends of the fifth resistor and the sixth resistor based on the output signal of the transistor
01) and the fifth transistor (Q100).

〔Example〕

 Next, the present invention will be described with reference to the drawings.

 FIG. 1 is a circuit diagram of one embodiment of the present invention.

Resistance R100, R101, R102 are connected in series between the resistors R1, R5, R4 and V _DD, resistance for varying the combined resistance value, the transistors Q100, Q102 differential output V _OUT variable switch, transistor Q101 , Q103 is a constant current V _REF variable switch, transistor Q104 is a constant current I ₁ variable switch, Is a current consumption adjustment terminal.

Current consumption adjustment terminal Is connected to V _DD , the transistors Q102, Q103, Q104 conduct and the transistors Q100, Q101 conduct. In this case, the impedance of the continuity diagram of each transistor is represented by resistors R100, R101,
R102 Since current I ₁ sufficiently small in comparison with, determined by the voltage V _REF, As described earlier resistance values of V _OUT R1, R5, R4.

Next, the current consumption adjustment terminal If the connected to the V _SS terminal, the transistors Q102, Q103, Q104
Is turned off, and the transistors Q100 and Q101 are turned off. Where Q10
4 constant current I ₁ flowing through the transistor Q6 by the series connected resistors R102 to the resistor R4 by turns OFF the the difference voltage between the base-emitter voltage V _BEQ6 the base-emitter voltage V _BEQ7 the transistor Q6 of the transistor Q7 resistors R4, R102 and by reducing the _{I 1 = (V BEQ7 -V BEQ6} ) / (R4 + R102) approximately R4 / relative current consumption next normal operation (R4 + R102).

At the same time the transistor Q102, Q103 also OFF, further transistors Q100, Q101 also Tamejo current I ₁ is OFF, I _2, I _S voltage is decreased V _REF, the voltage value of V _OUT is as unchanged It has become.

Next, the operation will be described in detail. In FIG.
In a normal operation state, a voltage that allows the transistors Q102 to Q104 to operate sufficiently is applied to the power consumption adjusting terminal POWER SAVE. At this time, the transistor Q104 is in a saturated state, and the collector and the emitter are almost at the same potential.
Are short-circuited, and the only resistor connected between the emitter of the transistor Q6 and the power supply VSS is R4.
Since the transistors Q102 and Q103 also become saturated at the same time, the transistors Q100 and Q101 are turned on and the resistors R100 and R101 are also short-circuited.

To shift to the power consumption reduction state, use the current consumption adjustment terminal.
Set POWER SAVE to VSS potential. Then transistor Q102
To 104 are turned off, and the resistors R100, 101, and 102 that have been short-circuited in the normal operation state are opened. Now, if the area of the transistor Q8 is the same as the area of the transistor Q9, and if the area of the transistor Q7 is smaller than that of the transistor Q6, the current flowing through the transistor Q7 becomes equal and the current density of the transistor Q7 increases, The base-emitter voltage becomes higher than the base-emitter voltage of the transistor Q6, and a potential difference occurs as described in the description of the conventional example.

The collector voltage of the transistor Q5 when the resistors R2 and R3 are provided so that the same current value as the transistor Q7 is generated in the transistors Q4 and Q5, that is, the signal input terminals IN-A and IN-B
, The minimum output voltage of the signal output terminal OUT, and the value of the current flowing through the transistor Q7 are given by Expressions 1, 2, and 3.

Reference voltage = VDD-(Q7 current x R5 + R101) ... (1) Minimum output voltage = VDD-(Q7 current x R1 + R100) ... (2) Q7 current = [(Q7 base-emitter voltage)-( Q6 base-emitter voltage)] / (R4 + R102) ... (3) Under normal conditions, the resistors R100, R101 and R102 are
When it is almost 0 ohm and you want to reduce the current consumption,
As shown in Equation 3, R102 is loaded, and the current of the transistor Q7 decreases. At this time, R100 and R101 in Equations (1) and (2) are added at the same time. Therefore, by setting the respective resistance values so as to cancel the decrease in the current of the transistor Q7, either the normal state or the decrease state of the current consumption can be achieved. In the state described above, the fluctuation of the reference voltage with respect to the input and the output voltage at the signal output terminal can be avoided.

The transistors Q2, Q3, Q4 are connected to the signal input terminal IN-B
, The signal input terminals IN-A,
A transistor Q1 is added to the transistor Q2 so as to cope with a case where a logical sum of IN-B is required.

〔The invention's effect〕

As described above, the emitter-coupled logic circuit of the present invention has a circuit with a current consumption corresponding to the required operation speed without changing the reference voltage V _{REF and the} output voltage V _OUT by adding the current consumption adjusting circuit. There is an effect that can be driven.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of the present invention, and FIG. 2 is a circuit diagram showing one example of the prior art. Q1, Q2, Q3 ... transistors, Q4, Q5, Q6, Q7, Q8, Q9, Q10 ... transistors, Q100, Q101, Q102, Q103, Q104 ... transistors, R1, R100 ... differential load resistance, R4, R102 ... fixed Current setting resistor, R5, R101: Reference voltage setting resistor, IN-A: Signal input terminal, OUT: Signal output terminal, ... Current consumption adjustment terminal.

Claims (1)

(57) [Claims] 1. A reference for comparing a first resistor (R4) for setting a constant current value of a constant current generator with a differential amplifier (Q2, Q3, Q4) for a signal input terminal based on the constant current. An emitter-coupled logic circuit including a second resistor (R5) for generating a voltage and a third resistor (R2) serving as a load of the differential amplifier, wherein the first resistor and the second resistor A fourth resistor (R102) and a fifth resistor added to the first resistor, the second resistor, and the third resistor, respectively, to simultaneously increase the resistance values of the first resistor, the third resistor, and the third resistor. (R101) and the sixth resistor (R100)
And a first transistor (104), a second transistor (Q103), and a third transistor (Q10) that perform ON / OFF operation based on a voltage supplied to a current consumption adjustment terminal POWER SAVE.
2) a common base-connected switch circuit; a circuit for short-circuiting or opening both ends of the fourth resistor in response to a change in the internal resistance of the first transistor; A fourth transistor (Q10) that shorts or opens both ends of the fifth resistor and the sixth resistor based on the output signal of the transistor
An emitter-coupled logic circuit comprising: 1) a fifth transistor (Q100).