JPH07105081A - Method for controlling access of synchronous dram and device therefor - Google Patents

Abstract

PURPOSE:To make an access efficiently suit the system performance of a peripheral equipment by make it possible to access synchronous DRAM in descending order at the time of using synchronous DRAM as a picture memory. CONSTITUTION:When an address inputted at first, synchronous DRAM being the picture memory 106 executes accessing in one of a sequential mode or an interleaving mode which are generated by synchronous DRAM during burst accessing. Then, picture data is written in the sequential mode so as to permit last picture data of whole picture data to be written in the max. address in the block of synchronous DRAM, picture data is read from the max. address in the block by the interleaving mode so that access is executed in descending order. That is, access is executed in an opposite direction (descending order) by using the characteristic of address generation in the interleaving mode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image memory control method of a printer controller and an image memory control method of a scanner controller using a synchronous DRAM as an image memory, and more specifically, to a synchronous DRAM as an image memory. Using DMA or shadow DMA
The present invention relates to an image memory control method for a printer control device and an image memory control method for a scanner control device for controlling writing / reading of image data.

[0002]

2. Description of the Related Art A conventional image data storage device has a high-speed page mode, static column mode, and nibble mode DRAM in order to realize large capacity and low cost.
It is common to configure using.

The fast page mode DRAM is / RA
By inputting / CAS and a column address while S is asserted, the same row address can be randomly accessed at high speed.

In addition, static column mode DR
The AM allows high-speed access to the same row address as in the high-speed page mode by changing the column address while / RAS is asserted. Since it is not necessary to strobe the address, the speed can be further increased.

Further, in the nibble mode DRAM, after the normal access, the data of the address whose lower 2 bits are incremented is sequentially due to the toggle operation of / CAS while / RAS is still asserted. Is accessed. Note that the nibble mode can perform burst access for only 4 words, but is characterized by being faster than other modes.

The above-mentioned DRAMs of various modes can be accessed at high speed only when the adjacent space is continuously accessed. Especially when sending out image data to a printer which requires high-speed operation and image data read by a scanner. When writing, the above-mentioned characteristics can be effectively utilized because the sequential access is performed.

Further, it is often practiced to share the work memory and instruction memory of the CPU that performs image processing and control of the entire system with the image memory to effectively use the resources. At this time, instruction reading is often performed sequentially, so high-speed access is possible. Further, since the refill operation of the cache memory is often configured to be performed in block units, high speed access is possible in this case as well.

However, even if high speed access can be realized, the cycle time is 40 nsec (25 M
However, in order to realize access at a higher speed, it is necessary to use SRAM or a bank interleave method. However, since the SRAM is expensive, there is a disadvantage that the use of the SRAM causes an increase in cost, and in the bank interleave, the sequential address can be accessed at the same time by accessing the previous address at the same time. However, since the bus width for the bank is required, the minimum configuration unit of the system becomes large, which again causes the cost increase.

Therefore, conventionally, in order to solve the above-mentioned inconvenience, a synchronous DRAM is used as a memory to write / read data.
A RAM access control method and apparatus are provided. The synchronous DRAM is a fully synchronous type of DRAM, and can input / output data at a maximum of 100 MHz. Since it is a synchronous type, it is possible to access the synchronous DRAM by giving a row address, a column address entry, a refresh, etc. as a command in synchronization with the rising edge of the clock.

Regarding reading, the time required for reading the first data is the same as that of a general DRAM, but subsequent data is output in synchronization with the clock cycle. Since the order of access at this time is set by mode setting, it is not necessary to input the column address for each clock. As for writing, it is possible to write from the first data in synchronization with the clock cycle. As described above, the synchronous DRAM is accessed in accordance with the clock cycle. However, since the clock cycle is high speed (100 MHz), the synchronous DRAM is accessed at high speed.

On the other hand, in the burst access, it is possible to set two kinds of access modes, that is, a sequential mode and an interleave mode.
Here, in the sequential mode, access is performed while incrementing the burst length from the start address. When the maximum address in the block is reached, the minimum address in the block is returned to.

Further, in the interleave mode, when the burst length is L, an exclusive OR operation with the start address is performed in order from 0 to L-1, and the address of the operation result is used in the operation order. It is something you access.

The block means a break for each burst length. Therefore, for example, in a 16M-bit synchronous DRAM having a 2M × 8 bit structure, assuming that the burst length is 4, there are 2 × 1024 × 1024 ÷ 4 = 512 × 1024 blocks per one.

By using the above-mentioned synchronous DRAM, forward sequential access can be realized at extremely high speed. Further, when the CPU refills the cache memory, it is often performed as an interleave, a sequential, or a 1-word access, but when a synchronous DRAM is used, all of these can be dealt with.

[0015]

However, according to the conventional synchronous DRAM access control method and apparatus described above, by using the synchronous DRAM, a large-capacity and high-speed image memory can be manufactured at low cost. Although it can be realized, when accessing the synchronous DRAM in the sequential mode, it is not possible to access in the direction of the smaller address (that is, in descending order). Therefore, when the synchronous DRAM is used as the image memory, There is a problem that it is not always possible to efficiently adapt to the system performance.

Here, the problems when the synchronous DRAM is used as an image memory will be specifically described. For example, in a printer, it may be necessary to send data in the image memory in a form rotated by 180 degrees, such as back-side image data in double-sided printing. In some cases, the read data of the scanner may be stored in the image memory in a form rotated by 180 degrees. In this case, it suffices to access in the direction with the smaller address (descending order), but with the sequential mode, the access is in the direction with larger address (ascending order), and the cache refill is easy in the interleave mode. It is difficult to access in descending order by using the synchronous DRAM because it is the mode for performing.

The present invention has been made in view of the above, and when a synchronous DRAM is used as an image memory, the synchronous DRAM can be accessed in descending order so that the synchronous DRAM can be accessed by a scanner, a printer, or the like. The objective is to efficiently match the system performance of the peripheral equipment of.

[0018]

In order to achieve the above object, the present invention provides a synchronous DRAM as an image memory.
In the access control method of the synchronous DRAM which writes / reads the image data by DMA by using, the last image data of all the image data to be written is written to the maximum address in the block of the synchronous DRAM. , Write image data in sequential mode, Synchronous D in interleave mode
The present invention provides an access control method for a synchronous DRAM that reads image data from the maximum address in a RAM block.

In order to achieve the above object, the present invention uses a synchronous DRAM as an image memory,
In the access control method of the synchronous DRAM that writes / reads the image data by the shadow DMA, the sequential image is written so that the last image data of all the image data to be written is written to the maximum address in the block of the synchronous DRAM. Image data is written in mode and synchronous D in interleaved mode
The present invention provides an access control method for a synchronous DRAM that reads image data from the maximum address in a RAM block.

In order to achieve the above object, the present invention uses a synchronous DRAM as an image memory,
In the access control method of the synchronous DRAM which writes / reads the image data by the DMA, the interleave mode is set so that the first image data of all the image data to be written is written to the maximum address in the block of the synchronous DRAM. The present invention provides an access control method for a synchronous DRAM in which image data is written in and the image data is read out from the maximum address in a block of the synchronous DRAM in a sequential mode.

In order to achieve the above object, the present invention uses a synchronous DRAM as an image memory,
In the access control method of the synchronous DRAM which writes / reads the image data by the shadow DMA, the interleaved so that the first image data of all the image data to be written is written to the maximum address in the block of the synchronous DRAM. Image data is written in the mode and synchronous D in the sequential mode
The present invention provides an access control method for a synchronous DRAM that reads image data from the maximum address in a RAM block.

In order to achieve the above object, the present invention uses a synchronous DRAM as an image memory,
In the access control method of the synchronous DRAM that writes / reads the image data by DMA, the last image data of all the image data to be written is the (2 ⁿ -1) th (n is an integer) in the block of the synchronous DRAM. )
Image data is written in the sequential mode so that the image data is written in the address of the synchronous D, and the image data is read from the (2 ⁿ -1) th address in the block of the synchronous DRAM in the interleave mode.
A RAM access control method is provided.

In order to achieve the above object, the present invention uses a synchronous DRAM as an image memory,
In the access control method of the synchronous DRAM which writes / reads the image data by the shadow DMA, the last image data of all the image data to be written is the (2 ⁿ -1) th (n is the Access control of the synchronous DRAM for writing the image data in the sequential mode so as to be written to the address of (integer) and reading the image data from the (2 ⁿ -1) th address in the block of the synchronous DRAM in the interleave mode. It provides a method.

In order to achieve the above object, the present invention uses a synchronous DRAM as an image memory,
In the access control method of the synchronous DRAM which writes / reads the image data by DMA, the first image data of all the image data to be written is the (2 ⁿ -1) th (n is an integer) in the block of the synchronous DRAM. )
The present invention provides an access control method for a synchronous DRAM in which image data is written in the interleaved mode so that the image data is written in the address, and the image data is read from the address of the last written image data in the sequential mode.

In order to achieve the above object, the present invention uses a synchronous DRAM as an image memory,
In the synchronous DRAM access control method for writing / reading image data by shadow DMA, the first image data of all image data to be written is the (2 ⁿ -1) th (n is The present invention provides an access control method for a synchronous DRAM in which image data is written in the interleave mode so that the image data is written to the address of (integer) and the image data is read from the address of the image data written last in the sequential mode.

In order to achieve the above object, the present invention uses a synchronous DRAM as an image memory,
In the access control method of the synchronous DRAM which writes / reads the image data by DMA, when the image data is written in the sequential mode and the image data is read, the read start address is set in the block of the synchronous DRAM (2 ^{The present} invention provides an access control method for a synchronous DRAM that rounds up to the ( ^n- 1) th address (n is an integer) and reads image data from the ( ^2n- 1) th address in the interleave mode.

In order to achieve the above object, the present invention uses a synchronous DRAM as an image memory,
In the access control method of the synchronous DRAM in which the image data is written / read by the shadow DMA, the image data is written in the sequential mode,
When reading the image data, the read start address is set to (2 ⁿ -1) in the block of the synchronous DRAM.
The present invention provides an access control method for a synchronous DRAM that rounds up to the (th) (n is an integer) address and reads image data from the (2 ⁿ -1) th address in the interleave mode.

In order to achieve the above object, the present invention uses a synchronous DRAM as an image memory,
In the access control method of the synchronous DRAM which writes / reads the image data by DMA, the first image data of all the image data to be written is the (2 ⁿ -1) th (n is an integer) in the block of the synchronous DRAM. )
To provide the access control method of the synchronous DRAM, the image data is written in the interleave mode so that the image data is written to the address of the synchronous DRAM, and the image data is read from the first address in the block of the synchronous DRAM in the sequential mode.

In order to achieve the above object, the present invention uses a synchronous DRAM as an image memory,
In the synchronous DRAM access control method for writing / reading image data by shadow DMA, the first image data of all image data to be written is the (2 ⁿ -1) th (n is Synchronous DR for writing image data in the interleave mode and reading the image data from the first address in the block of the synchronous DRAM in the sequential mode so that the data is written to the address
An AM access control method is provided.

In order to achieve the above object, the present invention uses a synchronous DRAM as an image memory,
Synchronous D for writing / reading image data
In the RAM access control device, some or all of the address bits output from the CPU are inverted,
An access control device for a synchronous DRAM provided with an inversion access means for accessing the synchronous DRAM. It should be noted that a part of the address bits is at least an address bit equal to or larger than the block size of the synchronous DRAM.

In order to achieve the above object, the present invention uses a synchronous DRAM as an image memory,
Synchronous D for writing / reading image data
In the RAM access control device, some or all of the address bits output from the CPU are inverted,
Provided is an access control device for a synchronous DRAM, which includes a first access means for accessing the synchronous DRAM and a second access means for accessing the synchronous DRAM without inverting the address bit output from the CPU. It is a thing. It is assumed that a part of the address bits is at least an address bit equal to or larger than the block size of the synchronous DRAM.

In order to achieve the above object, the present invention uses a synchronous DRAM as an image memory,
Synchronous D for writing / reading image data
In the access control device of RAM, synchronous DR
CPU to read image data from AM to printer
Invert all or part of the address bits output from the
A first access means for reading image data from the AM,
The present invention provides an access control device for a synchronous DRAM, which comprises a second access means for reading out image data from the synchronous DRAM in the interleave mode without inverting the address bit output from the CPU. It should be noted that a part of the address bits is at least an address bit equal to or larger than the block size of the synchronous DRAM.

In order to achieve the above object, the present invention uses a synchronous DRAM as an image memory,
Synchronous D for writing / reading image data
In the RAM access control device, when writing image data from the scanner to the synchronous DRAM, the CPU
The first access means for inverting part or all of the address bits output from the CPU to write the image data in the synchronous DRAM, and the address bits output from the CPU without inverting the image data to the synchronous DRAM. The present invention provides an access control device for a synchronous DRAM including a second access means for writing. It is assumed that a part of the address bits is at least an address bit equal to or larger than the block size of the synchronous DRAM.

In order to achieve the above object, the present invention uses a synchronous DRAM as an image memory,
Synchronous D for writing / reading image data
In the RAM access control device, some or all of the address bits output from the CPU are inverted,
The first access means for accessing the synchronous DRAM, the second access means for accessing the synchronous DRAM without inverting the address bit output from the CPU, and the address bit inversion target area The present invention provides an access control device for a synchronous DRAM, which is provided with an area judgment / control means for judging and controlling the switching between the first access means and the second access means. It is assumed that a part of the address bits is at least an address bit equal to or larger than the block size of the synchronous DRAM.

In order to achieve the above object, the present invention uses a synchronous DRAM as an image memory,
Synchronous D for writing / reading image data
In the access control device of RAM, synchronous DR
CPU to read image data from AM to printer
Invert all or part of the address bits output from the
A first access means for reading image data from the AM,
The second access means for reading the image data from the synchronous DRAM in the interleave mode without inverting the address bits output from the CPU, and determining whether or not the area is the address bit inversion target, An access control device for a synchronous DRAM provided with an area determination / control means for controlling switching between the access means and the second access means. It should be noted that a part of the address bits is at least an address bit equal to or larger than the block size of the synchronous DRAM.

In order to achieve the above object, the present invention uses a synchronous DRAM as an image memory,
Synchronous D for writing / reading image data
In the RAM access control device, when writing image data from the scanner to the synchronous DRAM, the CPU
The first access means for inverting part or all of the address bits output from the CPU to write the image data in the synchronous DRAM, and the address bits output from the CPU without inverting the image data to the synchronous DRAM. A synchronization including a second access means for writing and an area determination / control means for determining whether or not the area is an address bit inversion target and for controlling switching between the first access means and the second access means. Eggplant DR
An access control device for AM is provided. In addition,
A part of the address bits is at least an address bit equal to or larger than the block size of the synchronous DRAM.

[0037]

According to the access control method of the synchronous DRAM of the present invention (claims 1 and 2), the sequential image data is written so that the last image data of all the image data to be written is written to the maximum address in the block of the synchronous DRAM. • Descending access is performed by writing the image data in the mode and reading the image data from the maximum address in the block of the synchronous DRAM in the interleave mode.

According to the access control method of the synchronous DRAM of the present invention (claims 3 and 4), the first image data of all the image data to be written is the synchronous DRA.
To be written to the maximum address in the block of M,
The image data is written in the interleave mode, and the image data is read from the maximum address in the block of the synchronous DRAM in the sequential mode, so that the access is performed in the descending order.

Further, in the access control method for the synchronous DRAM of the present invention (claims 5 and 6), the last image data of all the image data to be written is the synchronous DRA.
M (2 ⁿ -1) th block of (n is an integer) to be written to the address of the write image data in sequential mode, in an interleaved mode in the block of synchronous DRAM (2 ⁿ -1 Access is made in descending order by reading the image data from the) th address.

According to the access control method of the synchronous DRAM of the present invention (claims 7 and 8), the first image data of all the image data to be written is the synchronous DRA.
The image data is written in the interleave mode so that the image data is written in the (2 ⁿ -1) th address (n is an integer) in the M block, and the image data is written from the address of the last written image data in the sequential mode. By reading, access is performed in descending order.

Further, according to the access control method of the synchronous DRAM of the present invention (claims 9 and 10), when the image data is written in the sequential mode and the image data is read, the read start address is set to the block of the synchronous DRAM. By rounding up to the (2 ⁿ -1) -th address (n is an integer) in the interleave mode and reading the image data from the (2 ⁿ -1) -th address in the interleave mode, access is performed in the descending order.

According to the access control method of the synchronous DRAM of the present invention (claims 11 and 12), the first image data of all the image data to be written is the synchronous D.
The image data is written in the interleave mode so that it is written at the (2 ⁿ -1) th (n is an integer) address in the RAM block, and the image data is written from the start address in the synchronous DRAM block in the sequential mode. Access is performed in descending order by reading.

Further, the access control device for the synchronous DRAM of the present invention (claims 14 to 16) inverts some or all of the address bits output from the CPU to access the synchronous DRAM,
Access in descending order.

Further, the access control device for the synchronous DRAM of the present invention (claims 17 to 19) determines whether or not the address bit inversion target area, and determines the first access means and the second access means. Access is efficiently performed in descending order by controlling the switching of.

[0045]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [Embodiment 1], [Embodiment 2], and Embodiments of the access control method for synchronous DRAM and the apparatus thereof according to the present invention applied to a control device of a copying machine will be described below.
[Third Embodiment] and [Fourth Embodiment] will be described in detail with reference to the drawings.

[Embodiment 1] FIG. 1 is a block diagram of a control device for a copying machine according to the first embodiment. In the figure, 101
Is a CPU, which performs overall system control and image processing. This CPU 101 has on-chip cache
It has a memory 101a. 102 is a ROM,
A control program executed by the CPU 101, various parameters, and the like are stored. 103 is an ASIC (application-specific IC), and the external access of the CPU 101 is ASIC
It is done via IC. A scanner I / F 104 interfaces with a scanner (not shown).
A host I / F 105 interfaces with a host such as a personal computer.

A printer I / F 107 interfaces with a printer (not shown). Image memory 1
The image data stored in 06 is the printer I / F1.
It is output to the printer via 07.

Reference numeral 106 denotes an image memory composed of a synchronous DRAM (hereinafter, it may be abbreviated as SDRAM in the drawings), and the scanner data received via the scanner I / F 104 and the host I. / F1
C for print data etc. received via 05
The PU 101 stores image data and the like created by performing image processing. Further, the image memory 106 is the CPU 10
1 may be used for working, or instructions may be downloaded here and the program executed there.

The image memory 106 is a synchronous DRAM.
It consists of Therefore, it is possible to access in two address types supported by the synchronous DRAM, that is, the sequential mode and the interleave mode. Figure 2 shows the sequential mode.
As shown in (a), the start address of the transfer block and the value of the binary counter are input to the adder 201, a sequential address is generated while incrementing the burst length, and access is performed according to the sequential address. It is a thing. When the maximum address in the block is reached, the minimum address in the block is returned to.

Further, in the interleave mode, if the burst length is L, as shown in FIG.
-1 is sequentially generated by the binary counter and EXOR
The circuit 202 performs an exclusive OR operation between the count value of the binary counter and the start address of the transfer block, generates the operation result as an interleave address, and accesses according to the interleave address.

Further, FIG. 3 shows a two-bank type cell array mechanism 300 incorporated in the image memory 106 to realize the bank interleave system. As shown in the drawing, two banks 301 are provided in one chip. By having the memory cell arrays of (bank 0) and bank 302 (bank 1), the interleave operation in one chip is possible. By alternately accessing the bank 301 and the bank 302, it is possible to input a command to another bank while one bank is being accessed, and to access from a row address, precharge, CAS latency, etc. It is possible to shorten. As a result, image data can be written and read without interruption.

FIG. 4 shows an internal block diagram of the ASIC 103, and 401 denotes a CPU I / F & DMA control section, which performs DMA adjustment with the CPU 101, address generation and the like. Further, various registers for setting the mode of the ASIC 103 are also included here. Furthermore, this CPU
The I / F & DMA control unit 401 is a shadow DM
It is also possible to correspond to A.

Reference numeral 402 denotes an address decoding unit,
As a result of the address decoding, only the corresponding chip select (CS) signal is activated. In the figure, S
CS is C of the synchronous DRAM (image memory 106)
The S signal and ECS are other CS signals.

Reference numeral 403 denotes an SDRAM control unit for controlling the synchronous DRAM, which is SR
It generates control signals such as AA (address), RAS, CAS, and WE.

In the above-mentioned configuration, the principle of access control of the synchronous DRAM of the first embodiment The first operation example (using DMA, image data from the image memory 106
Operation for rotating and reading 0 degree) Second operation example (Operation for rotating image data by 180 degrees in DMA and writing to image memory 106) Third operation example (Image for image from memory 106 by shadow DMA Operation of Rotating Data by 180 ° and Reading Out) Fourth Operation Example (Operation of Rotating Image Data by 180 ° and Writing to Image Memory 106 by Shadow DMA) The effects of the first embodiment will be described in order.

Principle of Access Control of Synchronous DRAM of Embodiment 1 The synchronous DRAM which is the image memory 106 is generated in the synchronous DRAM during the burst access if an address is first input during burst read. Two types of address generation methods (sequential mode and interleave mode
Access is performed by either type. In the sequential mode, as shown in FIG. 2A, the increment is made from the start address and the burst length is incremented for access. At this time, if the maximum address in the block is reached, the process returns to the minimum address in the block.

On the other hand, in the interleave mode, an address obtained as a result of an exclusive OR operation of a binary counter and a start address, which is incremented from 0, is accessed for the block length. FIG. 5 shows the access sequence when starting from each start address in the interleave mode when the burst length (hereinafter sometimes referred to as BL) is 8. As indicated by reference numeral 501 in the figure, when the start address starts from the maximum address in the block, the blocks are accessed in descending order, but in other cases, the accesses are not necessarily in descending order. Therefore, in the interleave mode, it is not possible to start from any address and access in descending order.

However, as described above, in the interleave mode, the interleave address is determined by the result of the exclusive OR operation with the counter starting from 0. Therefore, if (2 ⁿ -1) is the start address, From there, the minimum address in the block is accessed while decrementing by one. This is clear as shown by the halftone dots in FIG.

The present invention utilizes the characteristics of the address generation in the interleave mode to utilize the synchronous DRA.
The M is accessed in the reverse direction (descending order).

First Operation Example The first operation example shows an operation of rotating the image data from the image memory 106 by 180 degrees and reading it by the DMA.

Specifically, it is an operation of sending the image data stored in the synchronous DRAM to the printer I / F 107 as an image rotated by 180 degrees. However,
In this case, the image data stored in the synchronous DRAM is assumed to have been written in the ascending order in the sequential mode.

FIG. 6 shows the state of the image data stored in the synchronous DRAM, and the image data D (n-
7) to D (n-1) are stored in ascending order at physical addresses m to m + 6 in the synchronous DRAM. In order to read this image data by rotating it by 180 degrees, it is sufficient to read it from the physical address m + 6 in descending order as shown in the reading order.

FIG. 7 shows a timing chart at the time of reading in the reading order of FIG. In addition, Example 1
Then, Latency = 1 is set, and the data is read in the interleave mode from the synchronous DRAM having a two-bank configuration.

Further, in FIG. 7, / CS, / RAS,
/ CAS is a control signal to synchronous DRAM, / WC
EN is a write clock enable signal for the printer I / F 107, and the printer I / F 107 outputs CLK.
When this is sampled as "L" at the rising edge of (clock), it indicates that valid data is present on the data bus. DATA is the data on the data bus, A is the multiplexed address,
BS indicates bank select.

Now, the start address for image reading is the address m + 6, which is the third address in the block. In other words, it is neither the maximum address in the block nor the (2 ⁿ -1) th address in the block. Therefore, as shown in FIG.
In order to access in descending order, it is necessary to change the start address to the (2 ⁿ -1) th address. Therefore, access to the synchronous DRAM is started with m + 7 as the start address.

This flow will be described with reference to the timing chart of FIG. 7. First, at the rising edge of the second clock, m
Input the Row Address corresponding to the +7 address. At the rising edge of the third clock, the ColumnAddress corresponding to the m + 7 address is input. Since Latency = 1 here, the data at the address m + 7 is in the definite state at the rising edge of the fourth clock, but since this data is idle reading data, it is not sent to the printer I / F 107. . That is, at the rising edge of the fourth clock, / WCEN is set to "H" level and sampling is not performed, and the printer I / F 107 determines that this is not valid data and does not accept it.

From the 5th clock rising edge at which valid data is output to the 11th clock rising edge, / WCEN is set to the "L" level to cause the printer I / F 107 to sample the corresponding data.

On the other hand, as shown in FIG. 6, since the block is different from D (n-4), Latency = from the rising edge of the eighth clock where D (n-4) is to be read.
The Column Address corresponding to the m + 3 address is input at the rising edge of the 7th clock, which is one clock before. In addition, at the rising edge of the 6th clock one clock before that, the Row A corresponding to the address of m + 3 is
You have entered the address. As shown in the 2-bank type cell array mechanism 300 of FIG. 3, the address of the first block is made to correspond to the bank 301 and the address of the latter block is made to correspond to the bank 302. It is possible to write and read.

By the above processing, the image data of the image rotated 180 degrees can be sent to the printer I / F 107.

In the first operation example, the synchronous D
Although the last image data of the image data stored in the RAM is neither the maximum address in the block nor the (2 ⁿ -1) th address in the block,
When writing the image data to the synchronous DRAM, the CPU 101 determines that the last image data is synchronous D based on the data amount of all the image data to be written in advance.
Start to be the maximum address in the RAM block or the (2 ⁿ -1) th address in the block
By obtaining the address, writing the image data in the sequential mode based on the start address, and reading the image data from the maximum address in the block of the synchronous DRAM in the interleave mode,
Similarly, image data of an image rotated 180 degrees can be sent to the printer I / F 107.

If the last image data of the image data stored in the synchronous DRAM is not the maximum address within the block or the (2 ⁿ -1) th address within the block, it is reached until either one is reached. , CPU
Dummy data (empty image data) under the control of 101
It is also possible to identify the dummy data on the printer I / F 107 side at the time of writing and reading, and not to take in the dummy data.

Second Operation Example A second operation example shows an operation of rotating the image data by 180 degrees in the DMA and writing the image data in the image memory 106. Specifically, it is an operation of storing the read data of the scanner in the synchronous DRAM as an image rotated by 180 degrees.

FIG. 8 shows the writing order of the image data when the image data is stored in the synchronous DRAM. FIG. 9 shows the timing of writing image data in the writing order of FIG.
A chart is shown.

In FIG. 9, / CS, / RAS, / CA
S, BS, / WE, DQM are control signals to the synchronous DRAM, A is a multiplexed address, DA
TA indicates the data on the data bus. Also, / RCE
N is a control signal to the start address.
When the address is sampled by setting / RCEN to "L" level at the rising edge of the clock, the image data of the pixel is next output onto the data bus.

Now, the start address of image writing is the address of m + 6, which is the third address in the block. In other words, it is neither the maximum address in the block nor the (2 ⁿ -1) th address in the block. Therefore, as shown in FIG.
In order to access in descending order, it is necessary to change the start address to the (2 ⁿ -1) th address. Therefore, access to the synchronous DRAM is started with m + 7 as the start address.

This flow will be described with reference to the timing chart of FIG. 9. First, at the rising edge of the second clock, m
Input the Row Address corresponding to the +7 address. At the rising edge of the third clock, the ColumnAddress corresponding to the m + 7 address is input. Here, at the rising edge of the fourth clock, DQM
Is sampled as "H" level, so the write at this clock is masked and m + 7
Writing is not performed for the address.

On the other hand, from the rising edge of the 5th clock at which valid data is output to the rising edge of the 11th clock, the corresponding data is written in the synchronous DRAM. However, as shown in FIG. 8, D (n-4)
Since it is a write to another block, the corresponding Column Address corresponding to the address of m + 3 is input to the rising edge of the 8th clock, and m + 3 is input to the rising edge of the 7th clock one clock before that.
Inputs the Row Address corresponding to the address.

By the above processing, the image data can be stored in the image memory 106 as an image obtained by rotating the read data of the scanner by 180 degrees.

In the second operation example, the first image data when actually writing to the synchronous DRAM is not the maximum address in the block but (2 ⁿ −
Although the case where it is not the 1) th address is shown, when the image data is written in the synchronous DRAM, the CPU 10
In 1, the start address itself is previously set to the maximum address in the block or (2 ⁿ −
The address may be changed to the 1) th address, and similarly, the image data can be stored in the image memory 106 as an image obtained by rotating the read data of the scanner by 180 degrees.

Third Operation Example In the third operation example, the image memory 1
The operation of rotating the image data 180 degrees and reading the image data from 06 will be described. Specifically, it is an operation of sending the image data stored in the synchronous DRAM to the printer I / F 107 as an image rotated by 180 degrees. However,
In this case, the image data stored in the synchronous DRAM is assumed to have been written in the ascending order in the sequential mode.

FIG. 10 shows a state of the image data stored in the synchronous DRAM, and FIG. 11 shows a timing chart when reading is performed in the reading order of FIG.

In FIG. 11, / RD is a signal indicating an external read request from the CPU 101, Address
s is a signal indicating the target address of the external bus cycle of the CPU 101, / ACK is a signal indicating to the CPU 101 that the external bus cycle may be terminated, / ECS0 is a chip select signal for a space other than the image memory space, / CS, / RAS, / CAS are synchronous DRA
A control signal to M, A is a multiplexed address, BS is a bank select, and DATA is data on the data bus.

The flow of the timing chart of FIG. 11 is as follows.
Basically, it is the same as the timing chart of the first operation example shown in FIG. 7, but since the shadow DMA is used instead of the DMA here, mapping is performed as an address with an offset added to the normal image memory space. The DMA operation is performed by the CPU 101 performing a read operation to the shadow access space that has been created.

This operation will be explained with reference to FIG. 11. By outputting / RD of the shadow space of the image memory 106 from the 0th clock and asserting / RD, the CPU 1
01 starts the read operation for the shadow space. A
Upon recognizing this, the SIC 103 immediately asserts / ACK and releases the CPU 101. CPU 101 is 2
At the rising edge of the clock edge, / ACK is recognized, the data on the data bus is read, and the process then proceeds. However, since the data read here is invalid data, this data is not used inside the CPU 101.
After this, the cache memory 101 inside the CPU 101
When only a is used, the external bus cycle is not used, but in this example, the read request is output to ECS0 in order to read the ECS0 space. However, since the data bus is used for sending the image data to the printer I / F 107, reading from the ECS0 space starts from the 12th clock after this is completed.

By the above processing, the image data of the image rotated 180 degrees can be sent to the printer I / F 107.

In the third operation example, the synchronous D
Although the last image data of the image data stored in the RAM is neither the maximum address in the block nor the (2 ⁿ -1) th address in the block,
When writing the image data to the synchronous DRAM, the CPU 101 determines that the last image data is synchronous D based on the data amount of all the image data to be written in advance.
Start to be the maximum address in the RAM block or the (2 ⁿ -1) th address in the block
By obtaining the address, writing the image data in the sequential mode based on the start address, and reading the image data from the maximum address in the block of the synchronous DRAM in the interleave mode,
Similarly, image data of an image rotated 180 degrees can be sent to the printer I / F 107.

If the last image data of the image data stored in the synchronous DRAM is not the maximum address in the block or the (2 ⁿ -1) th address in the block, until either of them is reached. , CPU
Dummy data (empty image data) under the control of 101
It is also possible to identify the dummy data on the printer I / F 107 side at the time of writing and reading, and not to take in the dummy data.

Fourth Operation Example In the fourth operation example, image data is set to 1 by shadow DMA.
This is an example of an operation of rotating the image by 80 degrees and writing the image memory 106. Specifically, the read data of the scanner is 180
This is an operation of storing the image in the synchronous DRAM in a rotated image.

FIG. 12 shows the order of writing image data when the image data is stored in the synchronous DRAM. FIG. 13 shows a timing chart when the image data is written in the writing order of FIG.

In FIG. 13, / WE is a signal indicating an external write request from the CPU 101, Address
s is a signal indicating the target address of the external bus cycle of the CPU 101, / ACK is a signal indicating to the CPU 101 that the external bus cycle may be terminated, / ECS0 is a chip select signal for a space other than the image memory space, / CS, / RAS, / CAS, / WE, DQM are control signals to the synchronous DRAM, A is a multiplexed address, BS is bank select, DATA
Indicates the data on the data bus.

The flow of the timing chart of FIG. 13 is as follows.
This is basically the same as the timing chart of the second operation example shown in FIG. 9, but since the shadow DMA is used instead of the DMA here, mapping is performed as an address with an offset added to the normal image memory space. The DMA operation is performed by the CPU 101 performing a read operation to the shadow access space that has been created.

This operation will be described with reference to FIG. 13. While outputting the address of the shadow space of the image memory 106,
By asserting WE, the CPU 101 starts the write operation for the shadow space. As soon as the ASIC 103 recognizes this, it asserts / ACK and the CPU1
Release 01. The CPU 101 recognizes / ACK at the rising edge of the third clock, ends this external bus cycle, and shifts to the next processing. After that, when only the cache memory 101a inside the CPU 101 is used, the external bus cycle is not used. However, in this example, the write request to the ECS0 is output because the ECS0 space is written. ing. However, since the data bus is used to write the scanner read data to the image data, 12
Writing to the ECS0 space starts from the clock.

By the above processing, the image data can be stored in the image memory 106 as an image obtained by rotating the read data of the scanner by 180 degrees.

In the fourth operation example, the first image data when actually writing in the synchronous DRAM is not the maximum address in the block but (2 ⁿ −
Although the case where it is not the 1) th address is shown, when the image data is written in the synchronous DRAM, the CPU 10
In 1, the start address itself is previously set to the maximum address in the block or (2 ⁿ −
The address may be changed to the 1) th address, and similarly, the image data can be stored in the image memory 106 as an image obtained by rotating the read data of the scanner by 180 degrees.

Effects of First Embodiment (Effect 1) As described above, in the first embodiment, DMA
The last image data of all the image data to be written is stored at the maximum address in the block of the synchronous DRAM,
By reading the image data from the maximum address in the block of the synchronous DRAM in the interleave mode, when the image data is sent to the printer I / F 107 as an image in which the image data is rotated 180 degrees, a waiting time due to the skip of the data is generated. No, it can read at high speed. Also, because the reading is always performed for each unit length,
Control hardware is not complicated. Furthermore, when the image data is read without rotation, the sequential mode can be used, and in this case as well, there is no waiting time due to the skip of reading the data, so that the reading can be performed at high speed.

(Effect 2) As described above, the first embodiment
Then, in the DMA, in the interleave mode, the first image data of the scanner read data is synchronized DR
By storing at the maximum address in the AM block, the scanner read data can be written as 180 ° rotated image in the synchronous DRAM.
High-speed writing is possible without waiting time for reaching the write address. Moreover, since the writing is always performed for each unit length, the control hardware does not become complicated.

(Effect 3) In DMA, the last image data of all image data to be written is stored in the (2 ⁿ -1) th (n is an integer) address in the block of the synchronous DRAM, and the interleave Synchronous DR in mode
By reading the image data from the (2 ⁿ -1) th block in the AM block, when the image data is sent to the printer I / F 107 as an image obtained by rotating the image data by 180 degrees, there is no waiting time due to data skipping. ， High speed reading is possible. Further, since the reading is always performed for each unit length, the control hardware does not become complicated. Furthermore, when the image data is read without rotation, the sequential mode can be used, and in this case as well, there is no waiting time due to the skip of reading the data, so that the reading can be performed at high speed.

(Effect 4) As described above, the first embodiment
Then, in the DMA, in the interleave mode, the first image data of the scanner read data is synchronized DR
By storing at the (2 ⁿ -1) th address in the AM block, there is a waiting time for reaching the write address even when writing to the synchronous DRAM as an image obtained by rotating the scanner read data by 180 degrees. Writing does not occur and high speed writing is possible. Moreover, since the writing is always performed for each unit length, the control hardware does not become complicated.

[0099] In (effect 5) DMA, when the start address of the image reading is not in the (2 ⁿ -1) th address, and rounded up to (2 ⁿ -1) th address, in an interleaved mode from there An image obtained by rotating the image data 180 degrees by reading the image data,
Printer I / F 107 for both non-rotated images
Can be sent to. Further, since there is no limitation on the start address, the memory is not wasted.

(Effect 6) In DMA, the write start address of the image memory 106 for storing the scanner read data is (2) within the block of the synchronous DRAM.
^If it is not at the ( ^n- 1) th address, round up to the ( ^2n- 1) th address and write the image data in the interleaved mode from there to rotate the scanner read data by 180 degrees or without rotating the image. It can be written to the memory 106. In addition, start
Memory is not wasted because there are no address restrictions.

(Effect 7) In addition to the above effect, when the DMA is performed by the shadow DMA, the CPU can always be the master of the bus, and the over master for the arbitration of the bus master right. -There is an advantage that no head is generated.

[Embodiment 2] FIG. 14 is a block diagram of a control apparatus for a copying machine according to a second embodiment to which the synchronous DRAM access control method and apparatus of the present invention are applied. Note that the same reference numerals as those in the first embodiment indicate the same configurations, and therefore only different portions will be described here.

In the figure, 1401 is a RAM composed of DRAM, 1402 is an ASIC (application specific IC), and external access of the CPU 101 is AS
It is done via IC.

FIG. 15 shows an internal block diagram of the ASIC 1402. Reference numeral 1501 denotes a CPU I / F & DMA control section, which performs DMA adjustment with the CPU 101 and address generation. Also, various registers for setting the mode of the ASIC 1402 are included here.

Reference numeral 1502 denotes an address decoding unit, which activates only the corresponding chip select (CS) signal as a result of the address decoding. In the figure, SCS is a synchronous DRAM (image memory 10
6) CS signal and RCS are DRAM (RAM1401)
The CS signals and ECS are other CS signals.

Reference numeral 1503 is a bit inverting section,
Inverts the lower bits of the input address,
In the second embodiment, the lower 3 bits are inverted. It is also possible to prevent bit inversion under the control of the CPU I / F & DMA control unit 1501.

Reference numeral 1504 denotes an SDRAM control unit for controlling the synchronous DRAM,
(Address), RAS, CAS, WE and other control signals are generated.

FIG. 16 shows the internal structure of the bit inversion unit 1503. EAD [31: 0] is the bit inversion unit 1503.
The 32-bit address signal SEL input to the signal SEL is a signal for controlling bit inversion, and bit inversion is performed when it is "H". IAD [31: 0] is a 32-bit address signal output from the bit inverting unit 1503. A buffer 1601 does not invert the logic. Further, 1602 to 1604 are exclusive OR circuits, which are inverted when the SEL input is "H",
When it is "L", the one that is not inverted is output.

In the above configuration, the principle of access control of the synchronous DRAM of the second embodiment The first operation example (the access control example when the lower 3 bits of the address given to the synchronous DRAM is inverted) The second operation example (Example of Access Control When Outputting Data in Synchronous DRAM to Printer) Third Operation Example (Example of Access Control that Sends Image Data Reversing the Size Relationship of Addresses in Block Units to the Printer Without Image Rotation 4) Fourth operation example (when BL = 8, access control example in which scanner data is stored in the synchronous DRAM by reversing the magnitude relationship of addresses in block units) Order of effects of the second embodiment Described in.

Principle of Access Control of Synchronous DRAM of Embodiment 2 The synchronous DRAM, which is the image memory 106, is generated in the synchronous DRAM during the burst access when an address is first input during burst read. Two types of address generation methods (sequential mode and interleave mode
Access is performed by either type. In the sequential mode, as shown in FIG. 2A, the increment is made from the start address and the burst length is incremented for access. At this time, if the maximum address in the block is reached, the process returns to the minimum address in the block.

On the other hand, in the interleave mode, an address obtained as a result of the exclusive OR operation of the binary counter and the start address, which is incremented from 0, is accessed for the block length. FIG. 17 shows an access sequence when starting from each start address in the interleave mode when the burst length (hereinafter sometimes referred to as BL) is 8. As indicated by reference numeral 1701 in the figure, when the start address starts from the maximum address in the block, the blocks are accessed in descending order, but in other cases, the accesses are not necessarily in descending order. Therefore, in the interleave mode, it is not possible to start from any address and access in descending order.

Here, the exclusive OR operation has a characteristic that the output result is inverted when one of the input data is inverted. Therefore, when the synchronous DRAM is accessed in the interleave mode, even if the start address is inverted, the start address is externally inverted unless the rules of the inversion method are changed. It's no different from nothing. At this time, for example,
From the least significant bit of the address, B. L. If the bit indicating B.L. (3 bits if BL = 8 words) is inverted, the address relation is accessed in a block-by-block manner in the synchronous DRAM inside. Therefore, if the inversion of the address is stopped, it is possible to access each block as data in which the address is inverted. As a result, descending access is possible in the sequential mode.

The present invention utilizes the characteristics of the address generation in the interleave mode described above to make use of the synchronous DRA.
The M is accessed in the reverse direction (descending order).

First Operation Example The first operation example is access control when the lower 3 bits of the address given to the synchronous DRAM are inverted.

FIG. 18 shows what kind of address is accessed from the CPU 101 when the lower 3 bits of the address given to the synchronous DRAM are inverted. In Example 2,
B. of CPU 101. L. = 4 words, but in order to reverse the magnitude relationship of the addresses in the synchronous DRAM in units of 8 words, the address inversion for 3 bits is performed. Since the synchronous DRAM operates in the interleave mode, the address mismatch does not occur even if the CPU 101 performs one word access, interleave mode access, or sequential access starting from the minimum address of the block.

FIG. 19 is a timing chart of the synchronous DRAM by the CPU access shown in FIG.
In the second embodiment, Latency = 2 is set. C
The PU 101 outputs the read address from the rising edge of the first clock, and
When RD is asserted, the synchronous DRAM read is requested.

In response to the assertion of / RD, the ASIC 1402 inputs Row Address to the synchronous DRAM at the rising edge of the 4th clock, and inputs Column Address at the rising edge of the 6th clock.

The synchronous DRAM outputs so as to receive the first data at the rising edge of the eighth clock, and the ASIC 1402 outputs / AC so that the CPU 101 receives the data at the rising edge of the 8th to 11th clocks.
Assert K.

By the above processing, it is possible to invert some or all of the address bits output from the CPU 101 to access the synchronous DRAM, so that there is a relation of magnitude of address in block units determined by the number of inverted bits. Inverted image data can be generated in the synchronous DRAM without the software being aware of it.
Further, since it is possible to generate image data in which the magnitude relationship of the addresses is not reversed, it is possible to read the image data rotated 180 degrees or the image data not rotated in the sequential mode. In either case, since it is possible to read in the sequential mode, even when starting from an arbitrary address, without skipping,
It can be read at high speed.

Second Operation Example The second operation example is an access control example when the data in the synchronous DRAM is output to the printer.

FIG. 20 shows the physical address in the synchronous DRAM and the reading order when the data in the synchronous DRAM is output to the printer.
Here, the synchronous DRAM is B. L. = 8 words, the sequential mode is set, and the first data is stored at the address m-1 of the image data.

FIG. 21 shows a timing chart when the image data shown in FIG. 20 is read out.
ncy = 2 is set. Further, as shown in FIG. 3, the synchronous DRAM is a type in which two banks are built in one chip.

Further, in the second operation example, the address is not inverted, and the synchronous D is performed in the sequential mode.
The RAM is being accessed (it is also possible to use the interleave mode).

At the rising edge of the first clock, the synchronous DRAM outputs a row for bank 1 (302).
Address is input, and Row Address for bank 0 (301) is input at the rising edge of the second clock.
Enter. Then, at the rising edge of the third clock, the Column Address for the bank 1 (302) is
Input s. In the second operation example, since the sequential mode is used, access can be started from any address. In the second operation example, the Column Address corresponding to the address m-1 of the synchronous DRAM is input here.

Bank 0 at the rising edge of the 5th clock
The Column Address for (301) is input. Further, the Column Address corresponding to m-8 of the synchronous DRAM is input.
Since the data corresponding to this address is output from here after Latency = 2 clocks, the previous Column
Only 2 words of data corresponding to n Address are read.

By performing the processing in this way, it is possible to read the image data rotated 180 degrees for each clock from the rising edge of the fifth clock.

Third Operation Example A third operation example is an access control example in which image data in which the magnitude relationship of addresses is reversed in block units is sent to the printer without image rotation.

In FIG. 22, when the image data of which the magnitude relationship is reversed in block units is sent to the printer without image rotation, the address for 3 bits is inverted to access the synchronous DRAM, and this is continuous. It shows the relationship between the address before inversion and the address in the synchronous DRAM when it can be regarded as an address.

FIG. 23 shows a timing chart when the image data of FIG. 22 is read, in which the synchronous DRAM is set to the interleave mode.

At the rising edge of the first clock, the synchronous DRAM outputs the row for bank 1 (302).
Address is input, and Row Address for bank 0 (301) is input at the rising edge of the second clock.
Enter. Then, at the rising edge of the third clock, the Column Address for the bank 1 (302) is
Input s.

Here, the start address is (2 ⁿ −
Since it is 1), it is C corresponding to n + 4 as it is.
You have entered the column address. And
N + 8 at the rising edge of the 7th clock so that the data from D (4) can be read at the clock next to D (3).
The Column Address corresponding to is input.

By performing the processing in this way, it is possible to sequentially read the image data without image rotation from the rising edge of the fifth clock.

Fourth Operation Example The fourth operation example is the B. L. This is an example of access control in which the size of the address is reversed in block units and the scanner data is stored in the synchronous DRAM when = 8.

FIG. L. = 8, the relationship between the address of the synchronous DRAM when storing the scanner data in the synchronous DRAM by reversing the magnitude relationship of the addresses in block units, and the writing order are shown. . In the second embodiment, since the bit inversion unit 1503 that inverts 3 bits of the address is used, by accessing the address m, the synchronous DRAM is accessed as the address of m + 7.

FIG. 25 shows a timing chart when writing the image data of FIG. 24, in which the synchronous DRAM is set in the interleave mode.

At the rising edge of the first clock, the synchronous DRAM outputs a row for bank 1 (302).
Address is input, and Column Addr for bank 1 (302) is input at the rising edge of the third clock.
Entering ess.

In the second embodiment, since the start address passed to the bit inverting unit 1503 is m and m is (2 ⁿ -1), the Column corresponding to m is as it is.
Address is input. Then, after writing the data of D (7), the row address of the bank 1 (302) is input to the rising edge of the ninth clock so that the data from D (8) is continuously written, and 1
At the rising edge of the first clock, C of bank 1 (302)
column Address (Col corresponding to m + 8
umn Address) is input.

By performing the processing in this manner, it is possible to reverse the magnitude relationship of the addresses in block units and store the scanner data in the synchronous DRAM.

Effect of Second Embodiment (Effect 1) As described above, in the second embodiment, a part or all of the address bits output from the CPU are inverted to access the synchronous DRAM (inverted access means (bit inversion). Part 1503), the image memory 106 can be accessed from the CPU 101 with a partially or wholly inverted address. Therefore, the image data in which the size relationship of the addresses is reversed in block units determined by the inverted number of bits can be processed by software. It is possible to generate the image data in the synchronous DRAM and read the image data rotated by 180 degrees in the sequential mode without paying attention to the above. Therefore, even when starting from an arbitrary address, it is possible to read at high speed without skipping.

(Effect 2) Further, there is provided an inversion access means (bit inversion unit 1503) for inverting some or all of the address bits output from the CPU to access the synchronous DRAM, and partially or all of them. A method of accessing the image memory 106 from the CPU 101 with an inverted address and a method of accessing the image memory 106 without inversion of the CPU 10
Both the method of accessing the image memory 106 from 1 can be selected, so that the image data in which the magnitude relationship of the addresses is reversed in block units determined by the inverted number of bits is
Synchronous DRAM without being aware of software
Since it is possible to generate image data in which the image data is not inverted and the image data in which the magnitude relationship of the addresses is not reversed, it is possible to read the image data rotated by 180 degrees and the image data not rotated in the sequential mode. Therefore, even when starting from an arbitrary address, it is possible to read at high speed without skipping.

At this time, since the addresses of the block size of the synchronous DRAM or more are inverted, the CPU 101 uses the cache memory 101a and interleaves the refill at the time of a miss hit of the cache memory 101a. Whether it is accessed in mode, in sequential order, or accessed word by word, it rotates 180 degrees without causing an address mismatch. The CPU 101 can process the generated image data or the image data that is not rotated.

(Effect 3) Further, a method of accessing the image memory 106 from the CPU 101 with an address which is partially or wholly inverted, and the CPU 10 without address inversion.
Both the method of accessing the image memory 106 from 1 can be selected, so that the image data in which the magnitude relationship of the addresses is reversed in block units determined by the inverted number of bits is
Synchronous DRAM without being aware of software
Since it is possible to generate image data in which the address magnitude relationship is not reversed, it is possible to store the scanner read data in the image memory 106 by reversing the address magnitude relationship in block units. ，
In addition, it can be stored without reversing the magnitude relationship of the addresses.

(Effect 4) In addition, a method of accessing the image memory 106 from the CPU 101 with a partially or wholly inverted address, and the CPU 10 without address inversion.
Both the method of accessing the image memory 106 from 1 can be selected, so that the image data in which the magnitude relationship of the addresses is reversed in block units determined by the inverted number of bits is
Synchronous DRAM without being aware of software
Since it is possible to generate the image data in which the address size relationship is not reversed, it is possible to generate the image data in which the address size relationship is reversed in block units and the image data is stored without reversing the size relationship. Image data can be read out and printed out both with and without rotation of the image by 180 degrees.

[Third Embodiment] FIG. 26 is a block diagram showing the control device of a copying machine according to the third embodiment to which the synchronous DRAM access control method and apparatus of the present invention are applied. Note that the same reference numerals as those in the first embodiment indicate the same configurations, and therefore only different portions will be described here.

In the figure, reference numeral 2601 denotes an ASIC (application-specific IC), and external access of the CPU 101 is performed via the ASIC.

FIG. 27 shows an internal block diagram of the ASIC 2601. Reference numeral 2701 denotes a CPU I / F & DMA controller, which performs DMA adjustment with the CPU 101, address generation and the like. Also, various registers for setting the mode of the ASIC 2601 are included here.

Reference numeral 2702 denotes an address decoding unit which activates only the corresponding chip select (CS) signal as a result of the address decoding. In the figure, SCS is a synchronous DRAM (image memory 10
The CS signal and ECS in 6) are other CS signals.

Reference numeral 2703 is an address comparison unit, which determines whether or not it is an address bit inversion target area, and controls switching between inversion and non-inversion in a bit inversion unit 2704 described later.

Reference numeral 2704 is a bit inversion unit,
Inverts the lower bits of the input address,
In the third embodiment, the lower 3 bits are inverted. It is also possible to prevent bit inversion under the control of the address comparison unit 2703.

Reference numeral 2705 denotes an SDRAM control unit for controlling the synchronous DRAM, which is SRAA.
(Address), RAS, CAS, WE and other control signals are generated.

FIG. 28 shows the internal structure of the address comparison unit 2703 and the bit inversion unit 2704.
1: 0] is a 32-bit address signal input to the address comparison unit 2703 and the bit inversion unit 2704, IA.
D [31: 0] is a 32-bit address signal output from the bit inverting unit 2704. SEL is a signal for controlling bit inversion, and bit inversion is performed when it is "H".

The address comparing unit 2703 sets an image area start address setting register 2801, an image area end address setting register 2802, and a mode setting register 2803 for setting a mode for specifying whether or not to perform bit inversion.
, Comparators 2804 and 2805, and AND circuit 28
And 06.

CPU I / F & DMA control unit 27
By controlling 01, the image area start address setting register 2801 and the image area end address setting register 2
An address is set so that 802 includes an image area to be bit-inverted. Note that this address may be preset as a fixed address. Further, when SEL input to the mode setting register 2803 is "H", the bit inversion mode is set. Also,
When "L" is input, bit inversion is not performed for any address space.

The comparators 2804 and 2805 compare the addresses set in the image area start address setting register 2801 and the image area end address setting register 2802 with EAD [31: 0], respectively, and perform EA.
It is determined whether or not D [31: 0] is in the address space (area) that is the target of bit inversion. If it is within the target area, these two comparators 2804 and 2805
Respectively output "H", the AND circuit 280
6, "H" is output to the bit inverting unit 2704 at the next stage only when the area is in the target area and "H" is set in the mode setting register 2803.

The bit inversion unit 2704 has the buffer 280.
7 and three exclusive OR circuits 2808, 2809, 2
810 and 810, the buffer 2807 does not invert the logic. Exclusive OR circuit 2808, 2809, 2
810 indicates that the input from the address comparison unit 2703 is “H”.
, The bit of EAD [2: 0] is inverted and IAD
It outputs as [2: 0], and when it is "L", the one that is not inverted is output.

In the above-described structure, the third embodiment has the same principle as the access control principle of the synchronous DRAM of the second embodiment shown in the second embodiment, and the first operation example and the second operation example of the second embodiment are performed. Operations similar to the operation example, the third operation example, and the fourth operation example can be executed. Therefore,
The same effect as that of the second embodiment can be obtained.

However, in the third embodiment, the address comparison unit 2
In 703, it is possible to determine whether or not it is the target region for bit inversion, so in addition to the effect of the second embodiment,
Even if the bit inversion mode for the image memory 106 is changed midway, the work space of the CPU 101 is not affected.

[0158]

As described above, the access control method of the synchronous DRAM according to the present invention uses the synchronous DRAM as the image memory and controls the access of the synchronous DRAM for writing / reading the image data by the DMA. In the method, the image data is written in the sequential mode so that the last image data of all the image data to be written is written at the maximum address in the block of the synchronous DRAM, and in the block of the synchronous DRAM in the interleave mode. Since the image data is read from the maximum address, if a synchronous DRAM is used as the image memory, the synchronous D
By making the RAM accessible in descending order, the access of the synchronous DRAM can be efficiently matched with the system performance of peripheral devices such as a scanner and a printer.

The access control method of the synchronous DRAM according to the present invention uses the synchronous DRAM as an image memory, and in the access control method of the synchronous DRAM in which the image data is written / read by the shadow DMA, all the writing is performed. The image data is written in the sequential mode so that the last image data of the image data is written in the maximum address in the block of the synchronous DRAM, and the image data is read from the maximum address in the block of the synchronous DRAM in the interleave mode. Therefore, synchronous DR is used as an image memory.
When the AM is used, the synchronous DRAM can be accessed in descending order, and the access of the synchronous DRAM can be efficiently matched with the system performance of peripheral devices such as a scanner and a printer.

Further, the access control method of the synchronous DRAM of the present invention uses the synchronous DR as the image memory.
In the access control method of the synchronous DRAM in which the AM is used to write / read the image data by the DMA, the first image data of all the image data to be written is written to the maximum address in the block of the synchronous DRAM. Further, since the image data is written in the interleave mode and the image data is read from the maximum address in the block of the synchronous DRAM in the sequential mode, the synchronous DRA is used as the image memory.
When M is used, the synchronous DRAMs can be accessed in descending order, and the access of the synchronous DRAMs can be efficiently matched with the system performance of peripheral devices such as a scanner and a printer.

The access control method for the synchronous DRAM according to the present invention uses the synchronous DR as the image memory.
In the access control method of the synchronous DRAM which uses the AM and writes / reads the image data by the shadow DMA, the first image data of all the image data to be written is written to the maximum address in the block of the synchronous DRAM. As described above, the image data is written in the interleaved mode and the image data is read from the maximum address in the block of the synchronous DRAM in the sequential mode. Therefore, when the synchronous DRAM is used as the image memory, the synchronous DRAM is descended. Synchronous DRA with access
The access of M can be efficiently matched with the system performance of peripheral devices such as scanners and printers.

Further, the access control method of the synchronous DRAM of the present invention uses the synchronous DR as the image memory.
In the synchronous DRAM access control method of writing / reading image data by DMA using AM, the last image data of all image data to be written is (2 ⁿ -1) in the block of the synchronous DRAM. The image data is written in the sequential mode so that the image data is written in the address (n is an integer), and the image data is read from the (2 ⁿ -1) th address in the block of the synchronous DRAM in the interleave mode. When the synchronous DRAM is used as the image memory, the synchronous DRAM can be accessed in descending order, and the access of the synchronous DRAM can be efficiently matched with the system performance of peripheral devices such as a scanner and a printer.

Further, the access control method of the synchronous DRAM of the present invention uses the synchronous DR as the image memory.
In the synchronous DRAM access control method of writing and reading image data by shadow DMA using AM, the last image data of all the image data to be written is (2 ⁿ in the block of the synchronous DRAM).
Image data is written in the sequential mode so that it is written in the -1) th (n is an integer) address,
Since the image data is read from the (2 ⁿ -1) th address in the block of the synchronous DRAM in the interleave mode, the synchronous DRAM is used as the image memory.
When the above is used, the synchronous DRAM can be accessed in descending order, and the access of the synchronous DRAM can be efficiently matched with the system performance of peripheral devices such as a scanner and a printer.

Further, the access control method of the synchronous DRAM of the present invention uses the synchronous DR as the image memory.
In the synchronous DRAM access control method of writing / reading image data by DMA using AM, the first image data of all image data to be written is (2 ⁿ -1) in the block of the synchronous DRAM. Synchronous DRAM is used as the image memory in order to write the image data in the interleaved mode so that it can be written to the address (n is an integer) and to read the image data from the address of the last written image data in the sequential mode. If you do, Synchronous D
By making the RAM accessible in descending order, the access of the synchronous DRAM can be efficiently matched with the system performance of peripheral devices such as a scanner and a printer.

Further, the access control method of the synchronous DRAM of the present invention uses the synchronous DR as the image memory.
In the synchronous DRAM access control method of writing and reading image data by shadow DMA using AM, the first image data of all image data to be written is (2 ⁿ
-1) write image data in interleave mode so that it is written at the (n) integer address,
Since the image data is read from the address of the last written image data in the sequential mode, when the synchronous DRAM is used as the image memory, the synchronous DRAM can be accessed in descending order, and the access of the synchronous DRAM is performed by the scanner. , It can be efficiently matched with the system performance of peripheral devices such as printers.

Further, the access control method of the synchronous DRAM of the present invention uses the synchronous DR as the image memory.
In an access control method for a synchronous DRAM that uses AM to write / read image data by DMA, when writing image data in sequential mode and reading the image data, the start address of reading is set to the start address of the synchronous DRAM. (2 ⁿ − in the block
1) Since the image data is read out from the (2 ⁿ -1) th address in the interleave mode by rounding up to the (n is an integer) address, the synchronous DRA is used when the synchronous DRAM is used as the image memory.
Synchronous D by making M accessible in descending order
RAM access can be efficiently matched with the system performance of peripherals such as scanners and printers.

Further, the access control method of the synchronous DRAM of the present invention uses the synchronous DR as the image memory.
In a synchronous DRAM access control method that uses AM to write / read image data by shadow DMA, in the case of writing image data in sequential mode and reading the image data, the start address of reading is the synchronous DRAM. Rounding up to the (2 ⁿ -1) th (n is an integer) address in the block and reading the image data from the (2 ⁿ -1) th address in the interleave mode, a synchronous DRAM is used as the image memory. When used, the synchronous DRAM can be accessed in descending order, and the access of the synchronous DRAM can be efficiently matched with the system performance of peripheral devices such as a scanner and a printer.

Further, the access control method of the synchronous DRAM of the present invention uses the synchronous DR as the image memory.
In the synchronous DRAM access control method of writing / reading image data by DMA using AM, the first image data of all image data to be written is (2 ⁿ -1) in the block of the synchronous DRAM. The image data is written in the interleave mode so that the image data is written to the address (n is an integer), and the image data is read from the first address in the block of the synchronous DRAM in the sequential mode. When used, the synchronous DRAM can be accessed in descending order,
It is possible to efficiently adapt the access of the synchronous DRAM to the system performance of peripheral devices such as a scanner and a printer.

Further, the access control method of the synchronous DRAM of the present invention uses the synchronous DR as the image memory.
In the synchronous DRAM access control method of writing and reading image data by shadow DMA using AM, the first image data of all image data to be written is (2 ⁿ
-1) write image data in interleave mode so that it is written at the (n) integer address,
Since the image data is read from the start address in the block of the synchronous DRAM in the sequential mode,
When a synchronous DRAM is used as the image memory, the synchronous DRAM can be accessed in descending order, and the synchronous DRAM can be accessed by a scanner,
It is possible to efficiently match the system performance of peripheral devices such as printers.

Further, the access control device for the synchronous DRAM of the present invention uses the synchronous DR as the image memory.
In an access control device of a synchronous DRAM that uses AM to write / read image data,
Since an inversion access means for inverting a part or all of the address bits output from the PU to access the synchronous DRAM is provided, when the synchronous DRAM is used as the image memory, the synchronous DRA is used.
Synchronous D by making M accessible in descending order
RAM access can be efficiently matched with the system performance of peripherals such as scanners and printers.

Further, the access control device for the synchronous DRAM of the present invention uses the synchronous DR as the image memory.
In an access control device of a synchronous DRAM that uses AM to write / read image data,
A first access means for inverting a part or all of the address bits output from the PU to access the synchronous DRAM, and a second access means for accessing the synchronous DRAM without inverting the address bits output from the CPU. When the synchronous DRAM is used as the image memory, the synchronous DRAM can be accessed in descending order, and the synchronous DRAM can be accessed in the system performance and efficiency of peripheral devices such as scanners and printers. Can be adapted to suit.

Further, the access control device for the synchronous DRAM of the present invention uses the synchronous DR as the image memory.
In an access control device for a synchronous DRAM that uses AM to write and read image data, when reading image data from the synchronous DRAM to a printer, some or all of the address bits output from the CPU are inverted. A first access means for reading image data from the synchronous DRAM in the interleave mode and a second access means for reading image data from the synchronous DRAM in the interleave mode without inverting the address bit output from the CPU. Since it is equipped with
When the AM is used, the synchronous DRAM can be accessed in descending order, and the access of the synchronous DRAM can be efficiently matched with the system performance of peripheral devices such as a scanner and a printer.

Further, the access control device for the synchronous DRAM of the present invention uses the synchronous DR as the image memory.
In an access control device for a synchronous DRAM that uses AM to write and read image data, when writing image data from the scanner to the synchronous DRAM, some or all of the address bits output from the CPU are inverted. As a result, since the first access means for writing the image data in the synchronous DRAM and the second access means for writing the image data in the synchronous DRAM without inverting the address bit output from the CPU are provided, the image memory is provided. Synchronous DRA
When M is used, the synchronous DRAMs can be accessed in descending order, and the access of the synchronous DRAMs can be efficiently matched with the system performance of peripheral devices such as a scanner and a printer.

Further, the access control device for the synchronous DRAM of the present invention uses the synchronous DR as the image memory.
In an access control device of a synchronous DRAM that uses AM to write / read image data,
A first access means for inverting a part or all of the address bits output from the PU to access the synchronous DRAM, and a second access means for accessing the synchronous DRAM without inverting the address bits output from the CPU. And the area determination / control means for determining whether the area is the address bit inversion target area and controlling the switching between the first access means and the second access means. Synchronous DRA when using synchronous DRAM
Synchronous D by making M accessible in descending order
RAM access can be efficiently matched with the system performance of peripherals such as scanners and printers.

The access control device for the synchronous DRAM according to the present invention uses the synchronous DR as the image memory.
In an access control device for a synchronous DRAM that uses AM to write and read image data, when reading image data from the synchronous DRAM to a printer, some or all of the address bits output from the CPU are inverted. A first access means for reading image data from the synchronous DRAM in the interleave mode and a second access means for reading image data from the synchronous DRAM in the interleave mode without inverting the address bit output from the CPU. And area determination / control means for determining whether or not the address bit is to be inverted and switching control between the first access means and the second access means. Therefore, a synchronous DRAM as an image memory is provided. When you use Be accessible to DRAM is in descending order, it is possible to adapt the access synchronous DRAM scanner, the system performance and efficiency of peripherals such as a printer.

Further, the access control device for the synchronous DRAM of the present invention uses the synchronous DR as the image memory.
In an access control device for a synchronous DRAM that uses AM to write and read image data, when writing image data from the scanner to the synchronous DRAM, some or all of the address bits output from the CPU are inverted. The first access means for writing the image data in the synchronous DRAM, the second access means for writing the image data in the synchronous DRAM without inverting the address bits output from the CPU, and the address bit inversion target area. Area determination / control means for determining whether or not the first access means and the second access means are switched, and therefore, when a synchronous DRAM is used as the image memory, The DRAM can be accessed in descending order, Ronasu access DRAM scanner, it is possible to system performance and efficient adaptation of peripherals such as a printer.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment.

FIG. 2 is an explanatory diagram showing access by two address types of a synchronous DRAM.

FIG. 3 is an explanatory diagram showing a 2-bank type cell array mechanism incorporated in an image memory in order to realize a bank interleave method.

FIG. 4 is an internal block diagram of the ASIC of the first embodiment.

FIG. 5 is an explanatory diagram showing an access order when starting from each start address in the interleave mode when the burst length is 8.

FIG. 6 is an explanatory diagram showing a first operation example of the first embodiment.

FIG. 7 is a timing chart of a first operation example of the first embodiment.

FIG. 8 is an explanatory diagram showing a second operation example of the first embodiment.

FIG. 9 is a timing chart of a second operation example of the first embodiment.

FIG. 10 is an explanatory diagram showing a third operation example of the first embodiment.

FIG. 11 is a timing chart of a third operation example of the first embodiment.

FIG. 12 is an explanatory diagram showing a fourth operation example of the first embodiment.

FIG. 13 is a timing chart of the fourth operation example of the first embodiment.

FIG. 14 is a block diagram of a second embodiment.

FIG. 15 is an internal block diagram of the ASIC of the second embodiment.

FIG. 16 is an internal configuration diagram of a bit inversion unit according to the second embodiment.

FIG. 17: Interleave when the burst length is 8
It is explanatory drawing which showed the access order at the time of starting from each start address in mode.

FIG. 18 is an explanatory diagram illustrating a first operation example of the second embodiment.

FIG. 19 is a timing chart of the first operation example of the second embodiment.

FIG. 20 is an explanatory diagram showing a second operation example of the second embodiment.

FIG. 21 is a timing chart of a second operation example of the second embodiment.

FIG. 22 is an explanatory diagram showing a third operation example of the second embodiment.

FIG. 23 is a timing chart of the third operation example of the second embodiment.

FIG. 24 is an explanatory diagram illustrating a fourth operation example of the second embodiment.

FIG. 25 is a timing chart of a fourth operation example of the second embodiment.

FIG. 26 is a block diagram of a third embodiment.

FIG. 27 is an internal block diagram of the ASIC of the third embodiment.

FIG. 28 is an internal configuration diagram of an address comparison unit and a bit inversion unit according to the third embodiment.

[Explanation of symbols]

 101 CPU 101 Cache Memory 102 ROM 103 ASIC (Application Specific IC) 104 Scanner I / F 105 Host I / F 106 Image Memory 107 Printer I / F 401 CPU I / F & DMA Control Unit 402 Address Decoding Unit 403 SDRAM Control Unit 1401 RAM (DRAM) 1402 ASIC 1501 CPU I / F & DMA control unit 1502 Address decode unit 1503 Bit inversion unit 1504 SDRAM control unit 2601 ASIC 2701 CPU I / F & DMA control unit 2702 Address decode unit 2703 Address comparison unit 2704 Bit inversion unit 2705 SDRAM control unit

Claims (20)

[Claims] 1. A synchronous DRAM as an image memory
In the access control method of the synchronous DRAM which writes / reads the image data by DMA by using, the last image data of all the image data to be written is written to the maximum address in the block of the synchronous DRAM. , Write image data in sequential mode, Synchronous D in interleave mode
An access control method for a synchronous DRAM, wherein image data is read from a maximum address in a block of RAM. 2. A synchronous DRAM as an image memory
Write image data by shadow DMA using
In the access control method of the synchronous DRAM for reading, the image data is written and interleaved in the sequential mode so that the last image data of all the image data to be written is written at the maximum address in the block of the synchronous DRAM. The synchronous DRAM is characterized in that the image data is read from the maximum address in the block of the synchronous DRAM in the mode.
Access control method. 3. A synchronous DRAM as an image memory
In the access control method of the synchronous DRAM for writing / reading the image data by DMA by using, the first image data of all the image data to be written is written to the maximum address in the block of the synchronous DRAM. , Write image data in interleaved mode and synchronous D in sequential mode
An access control method for a synchronous DRAM, wherein image data is read from a maximum address in a block of RAM. 4. A synchronous DRAM as an image memory
Write image data by shadow DMA using
In the synchronous DRAM access control method for reading, the image data is written in the interleave mode so that the first image data of all the image data to be written is written at the maximum address in the block of the synchronous DRAM, and the sequential data is written. The synchronous DRAM is characterized in that the image data is read from the maximum address in the block of the synchronous DRAM in the mode.
Access control method. 5. A synchronous DRAM as an image memory
In the access control method of the synchronous DRAM in which the image data is written / read by the DMA using, the last image data of all the image data to be written is the (2 ⁿ -1) th image in the block of the synchronous DRAM. The image data is written in the sequential mode so that it is written to the address (n is an integer), and the image data is read from the (2 ⁿ -1) th address in the block of the synchronous DRAM in the interleave mode. And a synchronous DRAM access control method. 6. A synchronous DRAM as an image memory
Write image data by shadow DMA using
In the access control method of the synchronous DRAM for reading, the last image data of all the image data to be written is (2 ⁿ −) in the block of the synchronous DRAM.
1) Write the image data in the sequential mode so that it is written in the (th) (n is an integer) address,
An access control method for a synchronous DRAM, wherein image data is read from a (2 ⁿ -1) th address in a block of the synchronous DRAM in the interleave mode. 7. A synchronous DRAM as an image memory
In the access control method of the synchronous DRAM in which the image data is written / read by the DMA using, the first image data of all the image data to be written is the (2 ⁿ -1) th image in the block of the synchronous DRAM. Access control of a synchronous DRAM characterized in that image data is written in an interleave mode so that it is written to an address (n is an integer), and the image data is read from the address of the last written image data in a sequential mode. Method. 8. A synchronous DRAM as an image memory
Write image data by shadow DMA using
In the access control method of the synchronous DRAM for reading, the first image data of all the image data to be written is (2 ⁿ −) in the block of the synchronous DRAM.
1) Write the image data in the interleave mode so that it is written in the (th) (n is an integer) address,
An access control method for a synchronous DRAM, characterized in that the image data is read from the address of the last written image data in the sequential mode. 9. A synchronous DRAM as an image memory
In the access control method of the synchronous DRAM which writes and reads the image data by DMA using the, the image data is written in the sequential mode,
When reading the image data, the read start address is set to (2 ⁿ -1) in the block of the synchronous DRAM.
Synchronous DR characterized by rounding up to the (th) (n is an integer) address and reading the image data from the (2 ⁿ -1) th address in interleave mode
AM access control method. 10. A synchronous DRA as an image memory
In the access control method of the synchronous DRAM which uses M to write / read the image data by the shadow DMA, when writing the image data in the sequential mode and reading the image data, the start address of the read is the synchronous DRAM. Of the synchronous DRAM, which rounds up to the (2 ⁿ -1) -th (n is an integer) address in the block and reads the image data from the (2 ⁿ -1) -th address in the interleave mode. Access control method. 11. Synchronous DRA as an image memory
In the access control method of the synchronous DRAM which uses M to write / read the image data by DMA, the first image data of all the image data to be written is (2 ⁿ -1) in the block of the synchronous DRAM. In the synchronous DRAM, the image data is written in the interleave mode and the image data is read from the first address in the block of the synchronous DRAM in the sequential mode so that the image data is written in the address (n is an integer). Access control method. 12. A synchronous DRA as an image memory
In the access control method of the synchronous DRAM in which M is used to write / read the image data by the shadow DMA, the first image data of all the image data to be written is (2 ⁿ −) in the block of the synchronous DRAM.
1) Write the image data in the interleave mode so that it is written in the (th) (n is an integer) address,
An access control method for a synchronous DRAM, characterized in that image data is read from a start address in a block of the synchronous DRAM in a sequential mode. 13. A synchronous DRA as an image memory
In an access control device of a synchronous DRAM that uses M to write and read image data, a CP
Synchronous D characterized by comprising an inversion access means for inverting a part or all of the address bits output from U to access the synchronous DRAM.
RAM access control device. 14. A synchronous DRA as an image memory
In an access control device of a synchronous DRAM that uses M to write and read image data, a CP
First, a part or all of the address bits output from U are inverted to access the synchronous DRAM.
Access means for accessing the synchronous DRAM without inverting the address bit output from the CPU, and an access control device for the synchronous DRAM. 15. A synchronous DRA as an image memory
In an access control device for a synchronous DRAM that uses M to write / read image data, when reading image data from the synchronous DRAM to a printer, some or all of the address bits output from the CPU are inverted. A first access means for reading image data from the synchronous DRAM in the interleave mode and a second access means for reading image data from the synchronous DRAM in the interleave mode without inverting the address bit output from the CPU. An access control device for a synchronous DRAM, comprising: 16. A synchronous DRA as an image memory
In an access control device for a synchronous DRAM that uses M to write and read image data, when writing image data from the scanner to the synchronous DRAM, some or all of the address bits output from the CPU are inverted. And a second access means for writing the image data to the synchronous DRAM without inverting the address bit output from the CPU, and a second access means for writing the image data to the synchronous DRAM. Access control device for synchronous DRAM. 17. A synchronous DRA as an image memory
In an access control device of a synchronous DRAM that uses M to write and read image data, a CP
First, a part or all of the address bits output from U are inverted to access the synchronous DRAM.
Access means and second access means for accessing the synchronous DRAM without inverting the address bits output from the CPU, and it is determined whether or not the address bit inversion target area, and the first access Means and area determination / control means for performing switching control of the second access means and the synchronous D
RAM access control device. 18. Synchronous DRA as an image memory
In an access control device for a synchronous DRAM that uses M to write / read image data, when reading image data from the synchronous DRAM to a printer, some or all of the address bits output from the CPU are inverted. A first access means for reading image data from the synchronous DRAM in the interleave mode and a second access means for reading image data from the synchronous DRAM in the interleave mode without inverting the address bit output from the CPU. And an area judgment / control means for judging whether or not the area is an address bit inversion target and for controlling switching between the first access means and the second access means. Access control device for DRAM. 19. A synchronous DRA as an image memory
In an access control device for a synchronous DRAM that uses M to write and read image data, when writing image data from the scanner to the synchronous DRAM, some or all of the address bits output from the CPU are inverted. The first access means for writing the image data in the synchronous DRAM, the second access means for writing the image data in the synchronous DRAM without inverting the address bit output from the CPU, and the address bit inversion target area. Access control device for a synchronous DRAM, comprising: area determination / control means for determining whether or not the first access means and the second access means are controlled. 20. The part of the address bits is at least an address bit equal to or larger than the block size of the synchronous DRAM.
An access control device for a synchronous DRAM according to 4, 15, 16, 17, 18 or 19.