JP2007328910A - Main memory system with multiple data paths - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide the architecture of a microprocessor system capable of raising the system performance sharply with the minimum design change in the existing memory system. <P>SOLUTION: This memory is the memory which has a plurality of memory elements which have related addresses, and the memory is constituted by including at least an address specifying circuit which can receive at least a first part of an address from the external source of the memory according to transition of an address strobe signal and also can advance the address in a prescribed address sequence according to the next transition of the address strobe signal, and an output buffer circuit which can drive out data from the memory only after a plurality of transitions of the address strobe signal by burst read access. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to microprocessor system architecture. Specifically, the present invention relates to memory subsystem architecture, memory / microprocessor interface design, computer motherboard (mother board) design, and processor daughter board (daughter board) design.

  With advances in personal computers, there is a need for memory devices or memory devices that are faster, more dense, and less expensive than standard DRAMs. High speed page mode DRAM is the most popular standard DRAM today. In fast page mode operation, the row address strobe (/ RAS) is used to latch the row address portion of the multiplexed DRAM address. Multiple occurrences or occurrences of column address strobe (/ CAS) each latch a column address and randomly access data in the selected row while / RAS is active. The address is latched at the falling edge of / CAS, and the DRAM output is enabled. When / CAS transitions high, the DRAM output is in a high impedance state (tri-state). With the progress of integrated circuit manufacturing technology, the operation of DRAM internal circuits is faster than before. This high speed circuit allows for faster page mode cycle times. If the device operates with a minimum fast page mode cycle time, there is a problem reading the DRAM. / CAS may be as low as 15 nanoseconds, and the data access time (tCAC) from / CAS to valid output data may be up to 15 nanoseconds. Therefore, in the worst case, there is no time to latch output data outside the memory device. For devices that operate faster than the specification requires, the data may only be valid for a few nanoseconds. It is very difficult to latch asynchronous signals that are valid for only a few nanoseconds on a heavily loaded microprocessor memory bus. Even supplying a new address every 35 nanoseconds requires a large address driver that generates a significant amount of electrical noise in the system. In order to improve the data throughput of a memory system, it has become common to interleave multiple memory devices by placing multiple devices on a common bus. For example, two fast page mode DRAMs can be connected to the common address and data bus. One DRAM stores odd address data, and the other stores even addresses. The disadvantage of this approach is that it takes extra time to turn off one memory device and then turn on the other memory device during a memory cycle. In addition, a minimum number of interleave devices are required to realize a specific data bandwidth, and the required memory capacity is satisfied with a smaller number of devices.

There is a need for faster and higher density random access memory integrated circuits that provide strategies for incorporation into current personal computer systems. Many alternatives to standard DRAM architectures have been proposed in an attempt to meet this demand. One way to increase the data validity period at the output of the DRAM without increasing the fast page mode cycle time is called the extended data out (EDO) mode or extended data output mode. In EDO DRAM, during fast page mode operation, the data lines are not tristated between read cycles. Instead, data remains valid after / CAS goes high, until some time after the next / CAS low pulse occurs, or until / RAS or output enable (/ OE) goes high. The The determination of when valid data arrives at the output of fast page mode or EDO DRAM depends on when the column address input is valid, when / CAS falls, / OE status, and / CAS in the previous cycle. It can be a complex function with the time it goes up. The period for which the data is valid for the control line signal (especially / CAS) depends on the particular implementation of the EDO mode coordinated by various DRAM manufacturers. EDO DRAM enables higher frequency operation of the memory by extending the window of valid data output during page mode operation, which is exactly compatible with the aforementioned interleaved memory architecture due to this feature. Is low.

  Methods that further reduce memory access cycles tend to require additional circuitry, additional control pins, and standard device pinouts. For example, in the proposed industry standard synchronous DRAM (SDRAM) there is an additional pin for receiving a system clock signal. Since this system clock is connected to each device in the memory system, it is heavily loaded and always toggles the circuitry in all devices. The SDRAM also has a clock enable pin, a chip select pin, and a data mask pin. Other signals that appear to have names similar to those found on standard DRAMs have significantly different functions in SDRAM. With the addition of several control pins, the device pinout requires a departure from standard DRAM, which further complicates the design work to use these new devices. An SDRAM device requires an enormous number of additional circuits, resulting in increased device manufacturing costs.

  In order for existing computer systems to use improved devices with non-standard pinouts, those systems must be significantly modified. Furthermore, the existing computer system memory architecture has a large capacitive load on the signal line, so the control signal and address signal cannot be switched at the frequency required to operate the new memory device at high speed. It has become. Single in-line memory modules (SIMMs) are an example of an industry standard format for packaging memory in computer systems. In SIMM, all address lines are connected to all DRAMs. Further, in SIMM, a row address strobe (/ RAS) and a write enable (/ WE) are often connected to each DRAM. These lines are inherently capacitively loaded as a result of the number of device inputs driving. Also, since SIMM devices generally ground the output enable (/ OE) pin, / OE is unattractive as a candidate for providing the memory device with an extended function.

  Because of the large number of computers using SIMMs, there is great resistance to any proposal that deviates from the standard SIMM design. The industry's resistance to extreme deviations from standards and the inability of current systems to accommodate new memory devices has slowed the wide acceptance of new devices. Thus, devices with extremely different architectures will initially be manufactured in limited quantities. This limited production volume hinders cost reductions commonly realized by manufacturing improvements and efficiency associated with mass production.

A typical microprocessor system configuration, such as found in personal computers and workstations, includes a microprocessor coupled to a memory controller and a high speed static random access memory (SRAM). A large capacity main memory is coupled to the microprocessor bus via a memory controller, an address buffer, and a data buffer. The main memory is typically a DRAM that combines a relatively large data bandwidth and random access with a high density data storage device. The data buffer may be a transceiver, register, register transceiver, latch, etc. The buffer provides the necessary level of isolation to limit the load on the local microprocessor bus to a level that the microprocessor signal driver can handle. See Patent Document 1 below for a description of a typical system.
US Pat. No. 5,249,277

With the advancement of multimedia devices and software applications, more and more peripheral devices are becoming widely available. In this application, the peripheral device can be, but is not limited to, an internal adder in the circuit board or an external device that communicates with the host system. These devices are also indirectly coupled to the microprocessor and main memory. These peripheral devices include mass data storage devices such as CD ROM drives and magnetic hard drives, floppy disk drives, input / output ports for keyboard and mouse devices, sound cards, fax and modem devices, and display devices. , And other devices can be included. Due to signal drive constraints, not all of these peripheral subsystems can be directly coupled together. Unfortunately, buffering, multiplexing, and decoupling these subsystems from the microprocessor bus introduces delays that reduce system performance. For the description of EDO memory, see Non-Patent Document 1 below.
“HYPER PAGE MODE DRAM” (ELECTRONIC ENGINEERING, vol. 66, no. 813, 1 September 1994, p. 47-48 CP000445400 Barge C.)

  In order to maximize performance, the system resources that a microprocessor needs most often must be resources that the microprocessor can access with minimal delay. A major factor in system performance is the microprocessor-memory interface bandwidth. For this reason, memory subsystems are generally designed for high accessibility, but the interface and peripheral devices are PCI bus (peripheral component interconnect), VL bus (Video Electronics Standards Association (VESA) local) Bus) or via a system bus such as an ISA (Industry Standard Architecture) bus.

  Microprocessors require instructions and data to perform system tasks. Instructions and data are stored in main memory, typically DRAM. The microprocessor's most frequently used instructions and data can be stored in an internal or external SRAM cache to greatly improve system performance. Since the data in the cache is a copy of the data in the main memory, the cache memory provides fast access to the data, but does not increase the memory capacity of the system. Unfortunately, high speed SRAM devices are the most expensive memory devices for a given memory density. Due to the high cost and limited device density, high-speed SRAM cannot be used in most main memory applications. Since there is a high probability that the information required by the processor is in the cache, the performance of the conventional system can be greatly improved with a cache memory having a relatively small capacity. However, the improvement in cache memory “hit rate” tends to slow down long before the cache capacity approaches the capacity of the main memory, so large-capacity SRAM caches are uneconomical. DRAM is a more economical main memory solution, but it still requires a significant number of DRAM chips to achieve the best system performance. This means buffering those chips from the microprocessor bus. This buffering, coupled with the relatively slow initial access time of DRAM compared to SRAM, limits system performance.

There is a need for a new system architecture that increases the bandwidth from the microprocessor to the memory, eliminates the need for an SRAM cache in medium to high performance systems, and uses the SRAM cache to enhance performance in the system. Improvements in main memory access time and bandwidth continue to improve the performance of traditional system architectures. However, signal loading, buffer delay, and asynchronous timing between the memory and the microprocessor limit the ability of current system architectures to utilize such higher bandwidth memory devices. In addition, system elements other than microprocessors also require increased memory bandwidth.

  Integrated circuit memory devices (memory devices) with standard DRAM pinouts have been designed for high speed data access and compatibility with existing memory systems. A high-speed burst operation mode is provided to perform a plurality of sequential accesses after one column addressing, and read data based on the / CAS control signal is output. In the burst operation mode, the address is incremented inside the device, and the external address line does not need to be switched at a high frequency. A read / write command is issued once per burst access, eliminating the need to toggle the read / write control line at high speed. In order to clock the internal address counter and data input / output latch, only one control line (/ CAS) per memory chip must toggle at the operating frequency. Since each / CAS typically controls only a 1 byte wide data bus, the load on each / CAS is generally less than the load on the other control signals (/ RAS, / WE, and / OE). The internal circuit of the memory device is highly compatible with existing extended data output (EDO) DRAMs. This similarity allows the two component types to be manufactured on a single die with only a limited number of additional circuits. Since the standard non-burst mode and the fast burst mode can be switched, the device can be used to replace the standard device, eliminating the need to switch more complex high speed memory devices. Internal address generation provides faster data access times than is possible with fast page mode or EDO DRAMs. This high speed operation of the burst EDO device eliminates the need to interleave memory devices to achieve high data throughput. Unlike standard DRAM devices that can operate at 30 MHz and have a data lifetime of only a few nanoseconds, this burst EDO device can operate predictably at 100 MHz and has a data lifetime of 5 nanoseconds. This device is compatible with existing memory module pinouts. Memory modules include, but are not limited to, a single in-line memory module (SIMM), a multi-chip module (MCM), a dual in-line memory module (DIMM), and the like. This combination of mechanisms can greatly improve system performance with minimal design changes.

  In one embodiment of the present invention, the novel system architecture has a main memory divided into two main memory subsystems. The first part of the main memory consists of a burst access DRAM tightly coupled to the microprocessor data bus for optimum performance, and the second part of the main memory is connected to the micro through the data buffer. Loosely coupled to the processor data bus. The tightly coupled portion provides the processor with wide bandwidth, high density data, and information storage that can be synchronized with the processor clock. The second part provides additional memory capacity and the processor bus load does not increase proportionally. In the preferred embodiment, both subsystems are removable and the capacity / performance of the memory subsystem can be easily upgraded. In another preferred embodiment, only the loosely coupled system is removable and the tightly coupled system is mounted directly on the computer motherboard to achieve controlled signal propagation characteristics for maximum performance.

The second part allows peripheral devices and subsystems to have higher bandwidth memory access. Part of the second part can be used as a display buffer that may require very high bandwidth data access to refresh the display information. In the preferred embodiment, the display buffer can access the loosely coupled system while the microprocessor is accessing the tightly coupled system. In this embodiment, there is little or no performance penalty associated with the location of the display frame buffer in main memory. By using main memory as a display buffer, the additional cost associated with a separate display buffer is eliminated. In particular, the use of video RAM can greatly increase the cost of the computer system. Other advantages of the main memory display buffer include the flexibility of multiple display resolution options, in which case the memory not used for display can be used by the system as additional main memory .

  In order to speed up access by the microprocessor, the most frequently needed information needs to be stored in the first main memory portion. For systems that use SRAM caches, the microprocessor can obtain the most frequently needed information from the cache. In the case of a cache miss (when the requested data is not in the cache), the information is likely to be available in the tightly coupled portion of main memory. Because the percentage of time that the information contained in the second part of the main memory is needed is small, the overall system performance is reduced by the performance penalty associated with the loose coupling of the second part in most applications There is no significant drop.

  In a graphical user interface environment, multiple applications can be open at the same time (the user has started operating the application). In some cases, one application can run in the background while another application can run in the foreground. Each open application requires more main memory. In the preferred embodiment of the present invention, the tightly coupled main memory is assigned the lowest main memory address space, and the loosely coupled memory is assigned to a higher address space. For example, in a system with 144 megabytes of memory, the first 16 megabytes of main memory address space is allocated to tightly coupled main memory, and an additional 128 megabytes is allocated to higher address value loosely coupled main memory. When the operating system allocates memory, the lower address memory is used first. If the user has only a few applications open, all of the application code and data can be stored in tightly coupled memory, optimizing system performance for speed. If the user has many applications open, some application code may enter loosely coupled main memory. When a microprocessor accesses loosely coupled main memory, system performance may be degraded, but the flexibility of opening many applications at the same time is more important than the need to operate at maximum computational speed. This system provides the flexibility of a large memory capacity computer at the speed achievable with the use of limited tightly coupled main memory.

In this system, multiple types of memory can exist simultaneously in the system. For example, the first tightly coupled portion of the memory can be a burst EDO memory and the second loosely coupled portion can be an EDO memory. The memory controller is programmed to access the first portion of the burst EDO format at a first access rate and the second portion of the EDO format at a second access rate. Thereby, the user can obtain a large memory capacity and at least high-speed access to a part of the memory. The second portion of the main memory can be further divided into a plurality of memory banks. The first bank of the second portion can be an EDO memory that provides additional capacity for information that does not fit in the first tightly coupled portion. The second bank of the second portion may be burst EDO memory, providing a display frame with sufficient bandwidth to support a high resolution information display in addition to providing additional system memory capacity. -Also used as a buffer. An SDRAM or other burst access memory device can also be used for the first memory portion.

  At power up or reset, the system can determine the type and amount of memory in each memory bank and adjust memory access signal timing parameters accordingly. Alternatively, the user may need to put a particular type of memory in a particular memory bank. If a particular memory bank can be one of several types of memory, the user can select the memory subsystem with the most economical and / or best performance for that particular computer usage requirement. By choosing to do so, the price / performance characteristics of the system can be more freely governed.

  The features, objects and advantages of the present invention will be best understood with reference to the claims, the detailed description of the embodiments and the accompanying drawings.

  FIG. 1 illustrates a 16 megabit burst access extended data output dynamic random access memory (BEDO DRAM). The device is configured as a 2 mega.times.8 BEDO DRAM having an 8-bit data input / output path 10 for supplying 2,097,152 bytes of information to the memory array 12. In the preferred embodiment, the apparatus (or device) of FIG. 1 has an industry standard pinout for an 8-bit wide EDO DRAM. An active low row address strobe (/ RAS) signal 14 is used to latch the first portion of the multiplexed memory address from the address input 16 to the latch 18. The latched row address 20 is decoded by the row decoder 22. A row of memory array 12 is selected using the decoded row address. The column address strobe (/ CAS) signal 24 is used to latch the second portion of the memory address from the address input 16 to the column address counter 26. The latched column address 28 is decoded by the column address decoder 30. A column of memory array 12 is selected using the decoded column address.

  During a burst read cycle, the data in the memory array at the row address and column address location selected by the row address decoder and column address decoder is read from the memory array and passed through the data path 32 to the output latch 34. Sent to. Data 10 driven from a burst EDO DRAM can be latched outside the device in synchronization with / CAS after a predetermined number of / CAS cycle delays (latency or latency). For a two cycle latency design, the first / CAS falling is used to latch the initial address for burst access. The first burst data from the memory is driven from the memory after the second / CAS fall and remains valid during the third / CAS fall. After the memory device starts outputting data in a burst read cycle, the output driver 34 outputs data during the / CAS high period depending on the state of the output enable 42 and write enable 36 (/ OE and / WE) control lines. It continues to drive the data lines without being tri-stated or tri-stated, thus allowing additional time for the system to latch the output data. Once the row address and column address are selected, an additional transition of the / CAS signal is used to advance the column addresses in the column address counter in a predetermined order. When / OE is kept low and / WE is kept high, the point at which burst data becomes valid at the output of the burst EDO DRAM depends only on the timing of the / CAS signal. The output data signal level can be driven according to, but not limited to, standard CMOS, TTL, LVTTL, GTL, or HSTL output level specifications.

  To maximize compatibility or compatibility with overall system requirements, addresses can be advanced in a linear or interleaved manner. FIG. 2 is a table showing a linear addressing (addressing) sequence and an interleaved addressing (addressing) sequence for burst lengths of 2, 4, and 8 cycles. “V” of the start addresses A1 and A2 in the table represents an address value that does not change throughout the burst sequence. The column address can be advanced using multiple / CAS pulses when reading multiple data words at each / CAS transition, each pulse, or each column address. When using each transition of the / CAS signal to advance the address, data is driven from this portion after each transition following the device delay and referenced at each edge of the / CAS signal. This allows for burst access cycles where the highest switching control line (/ CAS) toggles only once (from high to low or from low to high) in each memory cycle. This is a standard DRAM that needs to be high after / CAS goes low in each cycle, or a synchronous DRAM that requires a full clock cycle (high and low transitions) for each memory cycle. In contrast. In order to maximize compatibility with existing EDO DRAM devices, the present invention will be described with reference to devices designed to latch column addresses on the falling edge of the / CAS signal.

  It is desirable to latch and increment the column address after the first / CAS falling and apply both the latched and incremented addresses to the array at the earliest opportunity during the access cycle. For example, a device can be designed to access two data words per cycle (prefetch architecture). The memory array of a prefetch architecture device can be divided into an odd array half and an even array half. Either the odd or even half is selected using the least significant bit of the column address, while the other column address bits select the column in each array half. In interleaved access mode with column address 1, the data in columns 0 and 1 is read according to the standard interleave addressing described in the SDRAM specification, and the data in column 1 follows the data in column 0. Will be output. In the linear access mode, column address 1 is applied to the odd array half and incremented to address 2 to access the even array half, resulting in a two word access. One way to implement this type of device architecture is to provide a column address increment circuit between the column address counter and the even array half. The increment circuit will increment the column address only if the first column address in the burst access cycle is odd and the address mode is linear. Otherwise, the increment circuit will pass the column address through without modification. In a design that uses two data access prefetches per cycle, the column address will be advanced only once every two active edges of the / CAS signal. A prefetch architecture that accesses more than two data words is also possible.

  Other memory architectures applicable to the present invention include pipelined architectures where memory accesses are sequential but each access requires multiple cycles to complete. In a pipeline architecture, the overall memory throughput approaches one access per cycle, but the memory data output is offset by the number of cycles depending on the length of the pipeline and / or the desired latency from CAS. Sometimes.

In a burst access memory device, each new column address from the column address counter is decoded and used to access additional data in the memory array without having to use additional column addresses at address input 16 To do. This burst data sequence continues at each / CAS fall until a predetermined number of data accesses equal to the burst length is made. A / CAS falling edge received after the last burst address was generated causes other column addresses to be latched from address input 16 and a new burst sequence is initiated. Read data is latched and output at each falling edge of / CAS after the 1 / CAS waiting time.

  In the case of a burst write cycle, data 10 is latched by the input data latch 34. When the first column address is latched, the target data at the first address specified by the row address and column address is latched with the / CAS signal (the write data latency is zero). Other write cycle data latency values are possible, but zero is preferred in current memory systems. Additional input data words to store at the incremented column address location are latched by / CAS on successive / CAS pulses. Input data from the input latch 34 is passed through the data path 32 to the memory array and stored in the storage location selected by the row address decoder and the column address decoder. Like the burst read cycle described above, a predetermined number of burst access writes are performed without the need to provide additional column addresses on address line 16. After a predetermined number of burst writes, a subsequent / CAS pulse latches the new starting column address and another burst read or write access begins.

  The memory device of FIG. 1 can include an option to switch between a burst EDO operating mode and a standard EDO operating mode. In this case, when the row address is latched (/ RAS falling, / CAS high), the write enable signal / WE36 is used to determine whether the memory access of the row is a burst mode cycle or a page mode cycle. You can decide if there is. If / WE is low at the fall of / RAS, the burst access cycle is selected. If / WE is high at the falling edge of / RAS, the standard extended data output (EDO) page mode cycle is selected. Both the burst mode cycle and the EDO page mode cycle are the operating frequency of the memory device without requiring the data line 10 to be in a high impedance state by the data output driver 34 between data read cycles while / RAS is low. Can be high. In addition to executing the standard DRAM control function, the DRAM control circuit 38 controls the I / O circuit 34 and the column address counter / latch 26 according to the mode selected by / WE at the fall of / RAS. In devices designed using burst mode only DRAMs or other methods of switching between burst and non-burst access cycles, use the / WE state at the falling edge of / RAS, You can switch to other possible modes, such as interleaved addressing mode versus linear addressing mode. Alternatively, if the / WE state at the falling edge of RAS is not used to select the operation mode, “don't care” can be used for / WE.

When latching the initial column address of a burst cycle with / CAS, a write enable signal can be used during a burst access cycle to select between read burst access and write burst access. If / WE is low at the time of column address latching, burst write access is selected. Burst read access is selected if / WE is high at column address latch. The level of the / WE signal must be maintained during burst access, high for read burst access and low for write burst access. Transitioning from low to high during a burst write access terminates the burst access and no more writes are performed. If there is a high to low transition on / WE during a burst read access, the burst read access is terminated and the data output 10 is in a high impedance state. To reduce the possibility of a false write cycle being triggered, the / WE signal transition can be locked out during a critical timing period during the access cycle. After a critical timing period, it is determined in the state of / WE whether to continue, start or end burst access. When burst access is completed, the burst length counter is reset and the DRAM is ready to receive another burst access command. If both / RAS and / CAS go high during a burst access, the burst access cycle is terminated, the data driver enters a high impedance output state, and the burst length counter is reset. For compatibility with hidden refresh cycles, if only / RAS goes high while / CAS is active, the read data can be kept valid at the device output, otherwise In some cases, burst access can be terminated using the / RAS only high state. Minimize the delay between burst accesses if you want to end one burst read before starting another burst read, or if you want to end the burst write before doing another burst write. Only write enable pulse width is required. For a burst read, / WE transitions from high to low to finish the first burst read, after which / WE goes high before the next falling edge of / CAS to specify a new burst read cycle. Return. For a burst write, / WE transitions high to end the current burst write access and then returns low before the next falling edge of / CAS to begin another burst write access.

  The basic implementation of the apparatus of FIG. 1 may include a fixed burst length 4, a fixed / CAS latency 2 and a fixed interleaved sequence of burst addresses. This basic implementation requires little additional circuitry for standard EDO page mode DRAM and can be mass produced to provide the functionality of both standard EDO page mode and burst EDO DRAM. In this device, the output enable pin (/ OE) can also be grounded for compatibility with many SIMM module designs. / OE is asynchronous control when disabled (coupled to ground), becomes inactive (high) before / CAS falls, remains inactive after CAS rises The data is prevented from being driven from that part of the read cycle. If these setup and hold conditions are not met, the read data is driven for some portion of the read cycle. Although it is possible to synchronize the / OE signal and / CAS, in this case, the delay time from normal / CAS to data valid becomes longer, and normally there is no unnecessary additional / CAS low pulse / RAS high The read data cannot be disabled before. In the preferred embodiment, if / OE transitions high at some time during the read cycle, the output remains in a high impedance state until the next falling edge of / CAS regardless of the next transition of the / OE signal. is there.

To make the burst length, / CAS latency, and address sequence programmable, one or more address input signals 16 or data signals 10 upon receipt of a write- / CAS-previous- / RAS (WCBR) programming cycle. A mode register 40 can be used to latch the state of In such devices, the output 44 from the mode register controls the necessary circuitry on the DRAM. 2, 4, 8 burst length options, all pages, 1, 2, 3 / CAS latency can be ensured. As device operating speeds increase and computer architectures advance, other burst length options and latency options can be provided. The device of FIG. 1 can make the address sequence programmable by latching the state of the least significant address bit during the WCBR cycle. The burst length and / CAS latency for this particular embodiment are constant. Other possible changes to this DRAM feature set include having only fixed burst mode, choosing between standard fast page mode (non-EDO) and burst mode, and output enable. Includes using pin (/ OE) 42 in combination with / RAS to select an operating mode. Also, the WCBR refresh cycle can be used to select an operating mode rather than a combination of control signal and / RAS. More complex memory devices have additional operations such as switching between fast page mode, EDO page mode, static column mode, burst operation by using various combinations of / WE and / OE at / RAS fall time Mode can be given. A mode can be selected from a similar set of modes by using a WCBR cycle that uses multiple address lines or data lines to encode the desired mode. Alternatively, a device having multiple modes of operation can have wire bond locations, programmable fuses, or non-volatile memory elements that can be used to program the mode of operation of the device.

  A preferred embodiment of a 16-bit wide burst EDO mode DRAM designed in accordance with the teachings of the present invention has two column address strobe input pins / CASH and / CASL. In a read cycle, only one / CAS signal needs to be toggled. The second / CAS can remain high or toggle with the other / CAS. During a burst read cycle, all 16 data bits are driven from a portion of the read cycle even if one / CAS remains inactive. In typical system applications, the microprocessor reads all data bits on the data bus during each read cycle and writes only data bytes, which are write cycles. Having one / CAS control signal remain static during the read cycle helps to reduce overall power consumption and noise in the system. In a burst write access cycle, each / CAS signal (CASH and / CASL) serves as a write enable for 8-bit wide data. Two / CAS are combined in an AND function to give a single internal / CAS, which is low when the first external / CAS falls and the last external / CAS is high It returns to high after a while. All 16 data inputs are latched when the first / CAS signal transitions low. If only one / CAS signal transitions low, the 8-bit data associated with / CAS that remained high is not stored in memory.

  The invention has been described with reference to several preferred embodiments. Fast page mode DRAM and EDO DRAM can be used in many configurations including x1 data width, x4 data width, x8 data width, x16 data width, 1 megabit density, 4 megabit density, 16 megabit density, and 64 megabit density In exactly the same way, the memory device of the present invention can take the form of many different memory configurations. Those skilled in the art of integrated circuit memory design will be able to design various memory devices without departing from the spirit of the present invention with the help of this specification. Therefore, detailed description of various memory device configurations applicable to the present invention is considered unnecessary.

A preferred pinout for a burst EDO memory device is shown in FIG. Note that this pinout may be the same as a standard EDO DRAM pinout. Because of this common pinout, this new device can be used in existing memory designs with minimal design changes. This common pinout also allows those skilled in the art familiar with standard EDO DRAM pinouts to easily make new designs. Variations of the foregoing invention that maintain the standard EDO DRAM pinout include driving the / CAS pin with a system clock signal to synchronize the memory device data access with the system clock. It is. In this embodiment, it is desirable to latch the row address using the first / CAS active edge after / RAS has fallen, and using the slow edge to the first column of the burst access cycle. The address can be latched. After the row and column addresses are latched in the device, the address can be incremented internally to provide a burst access cycle that is synchronized to the system clock. Other pin function alternatives include driving the burst address increment signal on the / OE pin. This is because the data output disable function is not required on this part of this pin. In other alternative uses of the / OE pin, the device can maintain a standard EDO pin array, but with increased functionality such as burst mode access. The / OE pin can be used to signal the presence of a valid column start address or to terminate burst access. Each of these embodiments provides a high speed burst access memory device that can be used in current memory systems with a minimum amount of redesign.

  FIG. 4 is a timing diagram for performing a burst read followed by a burst write of the apparatus of FIG. In FIG. 4, the row address is latched by the / RAS signal. In a design embodiment that uses the state of the / WE pin to specify a burst access cycle during / RAS, / WE goes low when / RAS falls. Next, when / WE goes high, / CAS is driven low to initiate a burst read access and the first column address is latched. The data output signal (DQ's) is not driven in the first / CAS cycle. On the second falling edge of the / CAS signal, the internal address generation circuit advances the column address, starts another access of the array, and after the time from / CAS to data access (tCAC) 1 data output is driven. For devices with a specified burst length of 4, latch the new column address for the new burst read access / the additional burst access cycle continues until the fifth falling edge of CAS. When / WE falls in the fifth / CAS cycle, burst access is terminated and the device is initialized for additional burst access. A new burst address is latched using the sixth falling edge of / CAS when / WE goes low, the input data is latched and the device burst write access is initiated. The additional data value is latched on successive / CAS falling edges until the burst access is completed.

  FIG. 5 is a timing diagram for performing a burst read cycle after a burst write access cycle. As in FIG. 4, the row address is latched using the / RAS signal. However, in this embodiment of the invention, / WE is don't care at the fall of / RAS. Burst write access is initiated with the first falling edge of / CAS combined with the low of / WE, and the first data is latched. Data values are further latched by successive / CAS falling edges, and the memory address is advanced in an interleaved or sequential manner within the device. At the fifth falling edge of / CAS, the new column address and the accompanying write data are latched. In the sixth / CAS cycle, the burst write access cycle continues until the / WE signal goes high. The burst write access is completed by the transition of the / WE signal. The seventh low transition of / CAS causes the new column address to be latched and burst read access begins (/ WE is high). The burst read continues until the end of the burst cycle.

4 and 5, note that during the burst read cycle, the data on the device output remains valid as long as the / OE pin is low, except for a short data transition period. Since the / WE pin is low before / CAS falls or when / CAS falls, the data input / output line is not driven from that part of the write cycle, and the / OE pin is “don't care”. Is. Only the / CAS signal and the data signal toggle at a relatively high frequency, and control signals other than / CAS do not need to be active or inactive during the 1 / CAS cycle time or less. This is often the case for SDRAMs that require row address strobe, column address strobe, data mask, read / write control signals to be valid for less than one clock cycle for various device functions. Symmetric. In a normal DRAM, the column address can be propagated through the array before / CAS falls to initiate data access. This is to allow high speed data access from the falling edge of / CAS if the address is valid for a period of time sufficient for data to be accessed from the array before / CAS falls. Done. In such a design, if the column address is changed before / CAS falls, memory access is resumed using the address transition detection circuit. This method actually requires additional time to make the memory access because it must reserve a period at the beginning of each memory cycle after the last address transition to prepare for the new column address. It is. If the column address is changed just before / CAS falls, the access time increases by about 5 nanoseconds. In embodiments of the present invention, column addresses cannot propagate in the array until / CAS falls. This eliminates the need for an address transition detection circuit and ensures a fixed array access time for / CAS. The column address is prevented from propagating to the array until the falling transition of / CAS, and at the same time, the counter is advanced at the rising edge of / CAS to supply the effective column address in preparation for the next falling edge of / CAS.

  FIG. 6 is a schematic diagram of a single in-line memory module (SIMM) designed in accordance with the present invention. The SIMM has a standard SIMM module pinout for physical compatibility with existing systems and sockets. When each of the 2 mega × 8 memory devices 10, 12, 14, and 16 is operated in EDO page mode, functional compatibility with EDO page mode SIMM is maintained. Each of the / CAS signals 18, 20, 22, and 24 controls a 1-byte wide 32-bit data bus 26, 28, 30, and 32. The / RAS34 signal is used to latch the row address in each memory device and can be used in combination with / WE36 to operate in both page mode burst mode and burst mode access cycles. The device selects between two modes. Address signal 38 provides a multiplexed row and column address to each memory device on the SIMM. In burst mode, only the active / CAS control line needs to be toggled at the operating frequency of the device, or as described above, if each edge of the / CAS signal is used, it must be toggled at half that frequency. The data line must be switchable at half the frequency of the / CAS line or at the same frequency, and other control and address signals are switched at a lower frequency than the / CAS line and the data line. As shown in FIG. 6, each / CAS signal and each data line are connected to one memory device, and can be switched at a higher frequency than other control signals and address signals. Each memory device 10, 12, 14 and 16 is designed in accordance with the present invention and is capable of a burst mode of operation, with a plurality of timings relative to the CAS control line after the first row and column addresses are latched. Internal address generation is implemented to perform sequential or interleaved data access from multiple memory address locations.

  FIG. 7 shows a front view of another SIMM designed in accordance with the present invention. Each device on the SIMM is a 4 megabit DRAM configured as 1 mega × 4. In this configuration, one / CAS controls two memory devices to achieve access to a 1 byte wide data bus. The eight devices shown form a 4-megabyte SIMM that is 32 bits wide. For a 32-bit wide 8-megabyte SIMM, there are eight more devices (not shown) on the back side.

  FIG. 8 shows a preferred pinout for a memory module designed according to the apparatus of FIG. This pinout is compatible with the fast page mode SIMM and EDO SIMM pinouts. Pin 66 is provided with a presence detection pin to indicate EDO operation, and a / OE input is provided on pin 46 in accordance with a standard EDO component type.

An alternative embodiment of the SIMM module of FIGS. 6, 7, and 8 includes the use of two / RAS signals, each / RAS signal controlling a 16-bit wide data bus according to the standard SIMM module pinout. included. It is also possible to realize 4M × 32-bit SIMM by adding four 2M × 8 EDO burst mode DRAMs to the device of FIG. 16-bit wide DRAMs can also be used, and these DRAMs typically have two / CAS signals, each / CAS signal controlling the 8-bit data width. By incorporating parity bits or error detection and correction circuitry, other possible SIMM module configurations are realized. Methods for error detection and correction are well known to those skilled in the art, and a detailed description of such circuits is not described in this application. Those skilled in the art will be able to design other SIMM designs using the novel memory device of the present invention after reading this specification. Although the present invention has been described with reference to SIMM designs, the present invention is not limited to SIMMs. The present invention is equally applicable to other types of memory modules including dual in-line memory modules (DIMMs) and multi-chip modules (MCMs).

  FIG. 9 is a schematic diagram of a data processing system designed in accordance with the present invention. As used herein, a microprocessor can be, but is not limited to, a microprocessor, a microcontroller, a digital signal processor, an arithmetic processor, or a central processing unit (CPU). In FIG. 9, the microprocessor 112 is connected to a microprocessor local bus 114 comprised of address and control signals 116 and data signals 118. The microprocessor can access several resources through timing and control circuitry 120. For example, the timing and control circuit receives address and control signals from the microprocessor and provides control signals to the static random access memory cache 117, the tightly coupled non-cached burst access DRAM 119, and the loosely coupled DRAM 132. Supply.

Microprocessor memory access speed and bandwidth are critical parameters for the performance of a microprocessor system. To maximize these parameters, SRAM caches are typically connected directly to the microprocessor local bus 114 without intermediate data buffers or latches. Main memory, typically DRAM, needs to have a large amount of data storage capacity. Since the microprocessor's bus driving capability is limited, it is necessary to separate the main memory consisting of a few or more memory chips from the microprocessor via an address buffer and a data buffer. In the system of FIG. 9, the microprocessor address bus is coupled to the loosely coupled main memory 132 via the control circuit 120 and optionally via an additional buffer 130. In general, it is necessary to reformat the microprocessor command and address signals within the control circuit 120. In addition, part or all of the reformatted address signal and control signal (126 for loosely coupled memory, 127 for tightly coupled memory) are buffered via the buffer 130 to reduce the load on the associated memory. You may need to drive. The buffered address and control signals for the loosely coupled memory are shown as signal 128. An example of the address reformat required in the control circuit 120 is a 32-bit address from the microprocessor, a 12-bit row address and a 12-bit column address via a 12-bit multiplexed address bus for 16-megabyte loosely coupled memory. To multiplex. The reformatting of the control signal includes the generation of / RAS and / CAS in response to a memory access request from the microprocessor. Microprocessor data bus 118 is coupled to loosely coupled main memory data bus 134 via data transceiver 136. A data transceiver is a bidirectional data buffer that allows memory data to be sent to and received from the microprocessor. The tightly coupled non-cache portion 119 of the main memory is more directly coupled to the microprocessor for high speed data transfer. The microprocessor address and control signals are coupled to the tightly coupled main memory via a control circuit. This control circuit provides a multiplexed address signal and memory specific timing control signal 127 in the preferred embodiment to the tightly coupled main memory. In this case as well, an additional buffer can be added between the control circuit and the tightly coupled memory to reduce the load on the control circuit, but this is not preferable because an additional delay occurs. In the preferred embodiment, the tightly coupled memory consists of eight 2 Mega.times.8 burst EDO DRAMs soldered to a common circuit board with the microprocessor. The number of memory circuits need not be eight, but preferably has a data width equal to the processor data width (in this case, a 64-bit data bus width). Similarly, SDRAM or other burst access memory devices can be used instead of burst EDO DRAM. A limited number of memory circuits directly connected to the system circuit board in this manner provides a high performance memory-to-microprocessor interface. If the system is designed to accept multiple configurations of tightly coupled memory, it may be necessary to reduce the maximum performance of the memory interface to accommodate changes in bus loads and signal noise. After the initial access delay, the burst EDO DRAM can supply data to the microprocessor every clock cycle during burst access. This is different from loosely coupled main memory, which generally requires an idle clock cycle (wait state) between data accesses during page mode operation.

  The control circuit 120 further allows the microprocessor to access other system components on the local system bus 140. The local bus 140 can be a PCI bus (peripheral component interconnect), a VL bus (video electronics standard boundary (VESA) local bus), or an equivalent architecture. The VL bus is primarily used in computers that use Intel 486 generation microprocessors. The PCI bus is primarily used in Intel Pentium (registered trademark) grade microprocessors, but is expected to be widely used in computers using IBM PowerPC microprocessors. Similarly, computers using future generations of microprocessors are likely to have new local bus standards that do not depart from the scope and spirit of the architecture of the present invention. The local bus can access loosely coupled main memory via the control circuit 120 and an additional set of data transceivers 138. The control circuit 120 can also control access from peripheral devices to the tightly coupled memory via the local system bus 140.

  Additional control circuitry 150 can be used to interface with an ISA (Industry Standard Architecture) bus 154. This bus provides compatibility with previous generation computers and peripherals designed for those computers. Additional peripheral devices 152 such as a keyboard, mouse, CD ROM drive, floppy disk drive, hard drive, etc. can also be interfaced to the local bus via the control circuit 150. A microprocessor can access a computer add-in card 158 designed according to the ISA bus interface, or the add-in card 158 can access system resources via the ISA bus. A BIOS (Basic Input / Output System) ROM 156 can also be accessed via the ISA bus. Interface signal 148 controls PCI bus access by devices on the ISA bus and other peripheral devices. As the display buffer bandwidth increases, the video frame buffer card 144 is typically interfaced to a local bus for improved system performance. Other PCI cards 146 can be connected on the PCI bus. In this system architecture, the system components that the microprocessor accesses most often are connected to the microprocessor's local bus to improve overall system performance. Other frequently accessed devices such as video buffers are accessed via the local system bus. Finally, devices with slow access times or devices that are not critical to overall system performance are placed on the ISA bus. The local bus and the ISA bus are generally mounted on the system mother board. The processor, cache memory, and main memory are also typically mounted on the system mother board, but some or all of these system components are mounted on the daughter board, making the daughter board more performant. You can easily upgrade performance by replacing it with a higher processor subsystem. Multiple processor systems are possible, and in the preferred embodiment each processor has its own tightly coupled main memory subsystem and its own loosely coupled memory subsystem or shared loosely coupled memory subsystem.

In operation, if there is a tightly coupled burst EDO main memory portion, the microprocessor reads the data by supplying address and control signals to the memory via the memory control circuit. In response to the initial address, read command, and access cycle strobe, the memory begins to access the first data word at the initial address. During the second access period of the burst access, the second access cycle strobe advances the address in the memory and initiates a read access of data from the second address. If the latency is 2, the first data is driven from the memory after the second access cycle strobe signal is generated. Typically, the first data is latched into the microprocessor in response to a third access cycle strobe that occurs at the beginning of the third access cycle period of the burst access. A second data value is also driven from the memory by the third access cycle strobe. The third access cycle strobe also generates a third address in the memory and starts a third data access. For 4-word burst access, burst data is latched into the microprocessor in response to the third, fourth, fifth and sixth access cycle strobes. In this manner, four data values are received by the microprocessor in response to one address and multiple access cycle strobes. If the memory is designed to perform a 4-word burst sequence and requires additional data values from the memory, the microprocessor uses the fifth access cycle strobe signal to A second address can be provided. In this case, a second 4-word burst sequence is initiated while the microprocessor is receiving data from the first 4-word burst. The relationship between burst access and 66 MHz system clock is, for example: In the first cycle, address information and control information are latched in the control circuit 120. In the second cycle, a row address and a / RAS signal are generated on the signal line 127 for the tightly coupled memory. In the third cycle, a column address is generated on the signal line 127. The fourth cycle generates a first access cycle strobe on 127. In the fifth cycle, a second access cycle strobe is generated on 127. In the sixth cycle, a third access cycle strobe is generated and the first data value is latched into the microprocessor via 118. In subsequent cycles, an access cycle strobe is generated and data is latched into the microprocessor. For 4-word burst access, the timing can be described as 6-1-1-1, and the first data value is latched after 6 system clock cycles and 3 in consecutive system clock cycles. A number of consecutive data values are latched. In contrast, a typical SRAM cache can supply data in a 3-1-1-1 sequence. Due to the size limit of the SRAM cache, cache hits are generally limited to about 80%, but a relatively large capacity tightly coupled memory can achieve a hit rate close to 100%. In systems without tightly coupled memory, cache misses typically result in a 7-2-2-2 access sequence from loosely coupled memory. Loosely coupled main memory alone has a 100% hit rate, resulting in an average access cycle time of (7 + 2 + 2 + 2) /4=3.25 system clock cycles. For a tightly coupled main memory with 100% hit rate, the average access cycle time is 9/4 = 2.25 system clock cycles. Similarly, the average access cycle time for a system with a SRAM cache with loosely coupled main memory is [(0.8 × 6) + (0.2 × 13)] / 4 = 1.85 system clock cycles. Become. Finally, the average access time for a tightly coupled system with SRAM cache is 1.65 system clock cycles with 80% cache hit rate and 20% tightly coupled memory hit rate. These values indicate both read and write access times for the SRAM cache and loosely coupled main memory. However, tightly coupled burst EDO memory write cycles are faster because there is generally no latency for the access cycle signal. This results in a 4-1-1-1 write cycle sequence for tightly coupled memory burst writes. By incorporating tightly coupled main memory, a medium to high performance system can be realized when SRAM cache is not used.
When using an M cache, extremely high performance is achieved.

  The burst EDO memory device of the present invention is particularly suitable for use in tightly coupled main memory applications because it can operate in shorter cycle times than conventional DRAMs. Because the cycle time is long (perhaps two system clock cycles), adding a data buffer does not significantly increase access time, but without the data buffer, the processor data bus is overloaded. There is little advantage in connecting the DRAM memory directly to the processor bus. On the other hand, the burst EDO DRAM has a larger ratio of the buffer delay to the minimum cycle time when the data buffer is incorporated. I can't.

  In the preferred embodiment of the present invention, the loosely coupled memory 132 of FIG. 9 operates using one of two or more types of memory. For example, the memory can consist of burst EDO, fast page mode, or EDO memory devices. The system can be tuned to accept memory modules with, for example, fast page mode, EDO, or burst EDO memory devices, in which case the system can be expanded to allow for the addition or upgrade of loosely coupled memory Each module has the exact same or nearly the same pinout.

  Flash memory and SDRAM memory are also suitable for use in loosely coupled memory, but they are generally not interchangeable with other types of memory devices, thus limiting the variety of system configurations. Flash memory may be particularly beneficial for use in portable computers where flash memory has certain performance advantages over magnetic hard disk drive technology. In this configuration, the loosely coupled non-volatile memory bank can perform the functions of the internal solid state hard drive, and the available memory (not needed as disk space) is increased from the lower performance random access memory. Can serve as an extension to the performance tightly coupled memory subsystem.

  FIG. 10 is a schematic diagram of another embodiment of the present invention. Elements having functions and descriptions in common with the elements of FIG. 9 are numbered accordingly. In FIG. 10, the loosely coupled main memory 132 has a memory data bus 134 coupled to the control circuit 120. The control circuit 120 performs data path control and buffering from the loosely coupled memory to the CPU 112 via the processor bus 114. The control circuit 120 also allows other system components to access the loosely coupled main memory via the system bus 140. Also shown in FIG. 10 is a display device 160 coupled to a video control circuit 144 that may comprise a display frame buffer. The display device can be, but is not limited to, a cathode ray tube (CRT), a liquid crystal display device (LCD), or a field emission display device (FED).

FIG. 11 is a timing diagram of a method for determining what type of memory is present in the system in accordance with the teachings of the present invention. To show a specific example, the data values in the figure correspond to a system with a data width of 4 bits. In practice, typical system data buses may have 8, 16, 32, 64, or other data widths. Similarly, although this timing diagram can be discussed with reference to the system of FIG. 9, the described method is a memory operable in one or more of at least two different access modes. The apparatus can be used equally well in a variety of system configurations in accordance with the teachings of the present invention. In FIG. 11, two data values are written to memory using a page mode write format. This format stores data correctly in fast page mode, EDO, or burst EDO memory devices. If the memory is burst EDO, the second address is generated internally, so the second column address (Cn + 1) in the figure is completely ignored by the memory device or the device being written. After writing two data values (0110 and 1001) selected to be easily distinguishable from each other and easily distinguishable from non-driven buses, the memory is read in burst EDO format. The waveform labeled DATA FPM represents the data bus of the system where the memory is operating in fast page mode. The waveform labeled DATA BEDO represents the data bus of the system where the memory is operating in burst EDO mode. Vertical lines t1, t2, t3, t4, and t5 represent several possible points in time where data can be sampled to distinguish the type of memory that may be present in the system. In particular, at time t5, each memory type shows a different response to the read operation. Since / CAS is high at time t5, the fast page mode memory is not driving the data bus. When the bus is not driven, it floats or terminates at a level that is typically interpreted digitally as a pattern of high, low, or high and low values. In either case, the data is unlikely to match the pattern being written. For systems that use a narrow data bus, or if the bus characteristics are unknown, repeat this method using different data patterns, and the signal is interpreted as a bus that matches the written data. It is desirable to ensure that no level is supplied. For a wide data bus, it is very unlikely that an undriven bus will match a random or appropriately changing data bit pattern, and multiple patterns may be considered unnecessary. For example, a possible pattern for a 32-bit data bus would be 0110 1001 1111 0001 1100 0011 0000 1110. At time t5, since the read address has not changed from cycle to cycle, the EDO memory drives data from the column address Cn onto the data bus. In the example of FIG. 11, this value is 0110. At time t5, the latency E2 burst EDO memory automatically increments the internal address during the burst read access cycle and supplies data from column address Cn + 1. In this way, it can be determined at time t5 whether the memory type is fast page mode, EDO, or burst EDO. A more comprehensive method performs more than two write cycles and three read cycles to allow burst EDO memory devices with latency other than two. For example, if 4 write cycles are followed by 5 read cycles and the data is sampled at / CAS high after the 5th read cycle, in fast page mode memory the data is bus dependent and EDO It is equal to the first data value in the memory and equal to the fourth, third or second data value in a burst EDO memory with a waiting time of 2, 3 or 4 respectively.

  Another method according to the present invention is to write data in burst mode format with the column address maintained at Cn while toggling / CAS to provide multiple data patterns. A read cycle at address Cn + x (where Cn + 1 is within the range of addresses that would have been written to the burst EDO memory device) is then performed as part of the burst or page mode read sequence. If the memory is a burst EDO memory, the data pattern read from address Cn + x will match the pattern written to Cn + x after the wait time. Fast page mode and EDO memory supply whatever data was in Cn + x prior to burst mode write. Alternatively, a single read cycle for address Cn sampling data near the end of the low period of / CAS provides a valid data output for fast page mode or EDO memory, but latency for burst EDO memory. No valid data is output because is not satisfied.

In each of the above methods for determining the type of memory present in the system, if it is known that the memory itself has multiple modes of operation, it is necessary to perform the step of putting the memory into a particular mode. The memory can be inspected after performing appropriate procedures to bring the memory into each possible desired mode of operation to determine what mode of operation the memory supports. Also, if the memory can be switched between linear addressing mode and sequential addressing mode, it must be considered whether it is linear addressing mode or sequential addressing mode. Any SRAM needs to be disabled before performing the above method, or additional steps are needed to ensure that the data read is not just cache data. Also, a known background data pattern can be written to an address range using this method to avoid false matches with uninitialized storage locations.

  The present invention teaches a system having multiple memory banks where each memory bank can have one of several types of memory. In a system designed with this teaching, each bank can be individually examined as described above. The system's memory controller is programmed to access each bank according to the type of memory present.

  Although the invention has been described with reference to preferred embodiments, many modifications and variations of the invention will be apparent to those skilled in the art without departing from the scope of the invention.

2 is a schematic electrical wiring diagram of a burst EDO memory. It is a table | surface which shows contrast with a linear addressing format and an interleave addressing format. FIG. 2 shows a preferred pin arrangement for the apparatus of FIG. FIG. 2 is a timing diagram of a method for accessing the apparatus of FIG. 1. FIG. 6 is another timing diagram for accessing the apparatus of FIG. 1. 2 is a schematic diagram of electrical wiring of a single in-line memory module. FIG. 2 is a front view of another memory module using the apparatus of FIG. FIG. 7 is a diagram illustrating a preferred pin arrangement of the memory module of FIG. 6. 1 is a schematic diagram illustrating a system designed in accordance with the present invention. FIG. 3 is a schematic diagram illustrating another embodiment of a system designed in accordance with the present invention. FIG. 5 is a timing diagram of a method for determining what type of memory is present in a system.

Explanation of symbols

12 memory array 18 latch 22 row decoder 26 counter 30 column decoder 34 input / output logic and latch 38 control circuit 40 mode register 112 CPU
114 Microprocessor local bus 117 SRAM cache 118 Burst EDO DRAM
120 Bus and memory control circuit 130 Buffer 132 DRAM
140 Local system bus 150 Control circuit 152 Peripheral device

Claims (1)

A memory device having a plurality of memory elements, each having an associated address,
At least a first portion of an address may be received from a source external to the memory device in response to a transition of an address strobe signal that is a column address strobe signal, and in response to a next transition of the address strobe signal. An addressing circuit capable of advancing addresses in a predetermined address sequence;
An output buffer circuit capable of transferring data from the memory device only after a plurality of transitions of the address strobe signal in a burst read access;
Including a memory device.

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