JPH0695893A - Interruption processor - Google Patents

Abstract

PURPOSE:To reduce circuits and to accelerate the processing of mask-impossible interruption. CONSTITUTION:By providing a mask-impossible interruption processing flag 11 set by the response cycle of the mask-impossible interruption and for inhibiting the output of the level of the mask-impossible interruption while it is set and a priority register 13 for holding and comparing priority between requests set to the mask-impossible interruption, for canceling the mask- impossible interruption processing flag and for outputting an interruption request when the mask-impossible interruption with higher priority is present, the mask impossible interruption with lower priority is prevented from being generated in multiplex during the time when a CPU is processing the mask-impossible interruption. Thus, the need of an interruption mask register is eliminated, the setting of a mask register inside an interruption processor performed by the CPU can be omitted and the reduction of the circuits and the acceleration of the processing can be realized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interrupt processing for controlling a processing request of a peripheral processing device in an information processing system comprising a central processing device and a plurality of peripheral devices requesting processing to the central processing device. It relates to the device.

[0002]

2. Description of the Related Art A conventional interrupt processing device will be described below.

FIG. 2 is a block diagram of a conventional interrupt processing device. In FIG. 2, 1 is an interrupt processing device, and 2 is an interrupt request input from a peripheral device, and a plurality of requests are simultaneously input. Reference numeral 3 is an interrupt level register, and 4 is an interrupt mask register. An interrupt request output unit 5 outputs an interrupt request output 6 to the CPU or a higher-order interrupt processing device.

The operation of the conventional interrupt processing device configured as described above will be described below.

First, in the initialization of the system, the interrupt level register 3 is set, and the interrupt level for each interrupt request input 2 is set. When the interrupt request 2 is generated, the interrupt request output unit 5 outputs the interrupt level corresponding to the interrupt request input being generated as the interrupt request output 6. When the generated interrupt request input 2 is set to the non-maskable interrupt by the interrupt level register 3, the level of the non-maskable interrupt is output to the interrupt request output 6.

[0006]

However, in the above-described conventional configuration, when the CPU accepts the non-maskable interrupt, the interrupt mask register 4 is set and the interrupt processing is performed prior to the interrupt response cycle for searching the interrupt vector. It is necessary to prohibit the non-maskable interrupt from being output to the CPU until the end of the above step, and unmask the interrupt mask register again after the end of the interrupt processing. Further, while the mask register is set, there is a drawback that interrupt processing is not executed even if an interrupt having a higher priority among interrupts set as non-maskable interrupts occurs.

The present invention solves the above-mentioned conventional problems. It is not necessary for the CPU to set the mask register in the interrupt processing unit prior to the interrupt response cycle for the non-maskable interrupt, and a plurality of non-maskable interrupts are required. It is an object of the present invention to provide an interrupt processing device capable of setting a priority during a non-maskable interrupt in the presence of the above.

[0008]

To achieve this object, an interrupt processing device of the present invention masks an interrupt level register holding an interrupt level corresponding to each interrupt request input and a request output of a non-maskable interrupt. A mask that holds the non-maskable interrupt processing flag and the priority level of the request input set to the non-maskable interrupt, and unmasks the request level output when a non-maskable interrupt request set to a higher priority level occurs. It has a configuration with a disabled interrupt priority register.

[0009]

With this configuration, the level of the non-maskable interrupt is not output to the CPU while the CPU is executing the processing of the non-maskable interrupt. Interrupt processing can be started without setting the mask register. Even if the CPU is processing a non-maskable interrupt, if an interrupt with a higher priority than the interrupt being processed occurs, an interrupt request is output to the CPU, so the interrupt with a higher priority waits. Processing is performed immediately without being forced to do so.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an interrupt processing device according to an embodiment of the present invention. In FIG. 1, 10 is an interrupt processing device, 11 is a non-maskable interrupt processing flag, which is set in the interrupt response cycle of a non-maskable interrupt and indicates that non-maskable interrupt processing is in progress. An interrupt level output unit 12 masks the output of the non-maskable interrupt level while the non-maskable interrupt processing flag is set. 1
Reference numeral 3 is a non-maskable interrupt priority register that holds the priority of the request set to the non-maskable interrupt. 2 is an interrupt request input from a peripheral device, 3 is an interrupt level register, 6
Indicates an interrupt request output, which has the same configuration as that of a conventional interrupt processing device.

The operation of the interrupt processing device configured as described above will be described below.

Until the CPU activates the interrupt response cycle of the non-maskable interrupt, the interrupt level corresponding to the interrupt request input is output to the interrupt request output 6 as in the conventional example. Similarly, when a non-maskable interrupt is generated, the interrupt request output 6 outputs the level of the non-maskable interrupt. When the CPU detects a non-maskable interrupt and becomes ready to accept an interrupt, an interrupt response cycle for searching an interrupt vector is started for the interrupt processing device. When the non-maskable interrupt processing flag unit 11 in the interrupt processing device recognizes that it is a response cycle of the non-maskable interrupt, it sets a flag, stores that the CPU is processing, and sets the non-maskable interrupt priority register. The priority of the non-maskable interrupt being processed is stored in. When the non-maskable interrupt processing flag 11 is set, the interrupt request output unit 12 masks the level output of the non-maskable interrupt. When the processing of the non-maskable interrupt by the CPU is completed, the CPU resets the non-maskable interrupt processing flag, and the interrupt output unit 12 outputs the level of the interrupt normally generated to the interrupt request output 6. If another non-maskable interrupt occurs during the processing of the non-maskable interrupt, that is, before the non-maskable interrupt processing flag is cleared by the CPU, it is compared with the priority held in the non-maskable interrupt priority register 13. If the request has a higher priority, the non-maskable interrupt processing flag is cleared and the level of the non-maskable interrupt is output to the interrupt request output 6. If the generated non-maskable interrupt is set to a lower priority than the interrupt being processed, the non-maskable interrupt processing flag is not released, and therefore the interrupt request output unit 6 does not output the level of the non-maskable interrupt.

As described above, according to the present embodiment, by providing the non-maskable interrupt processing flag and the non-maskable interrupt priority register, the interrupt mask register in the interrupt processing device becomes unnecessary, and the CPU executes the interrupt processing device. Since the mask register setting of can be omitted, non-maskable interrupts can be processed at high speed, and if a non-maskable interrupt with a higher priority occurs during the processing of a non-maskable interrupt, the CPU is immediately notified. Thus, it is possible to realize an excellent interrupt processing device that maintains system consistency.

[0015]

As described above, according to the present invention, the priority of a non-maskable interrupt can be set when there are a plurality of non-maskable interrupts, and the priority can be set and set by the interrupt response cycle of the non-maskable interrupt. By setting a non-maskable interrupt processing flag that masks the request level output of non-maskable interrupts other than the non-maskable interrupt set to a higher priority during the period, the interrupt mask register in the interrupt processing device becomes unnecessary, Since the mask register setting in the interrupt processing unit, which is performed by the CPU, can be omitted, the number of circuits can be reduced, the processing of non-maskable interrupts can be speeded up, and even in the non-maskable interrupts, the request of higher priority can be preceded. It is possible to realize an excellent interrupt processing device capable of processing.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an interrupt processing device according to an embodiment of the present invention.

FIG. 2 is a block diagram of a conventional interrupt processing device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 interrupt processing device 2 interrupt request input 3 interrupt level register 4 interrupt mask register 5 interrupt request output unit 6 interrupt request output 10 interrupt processing device 11 non-maskable interrupt processing flag 12 interrupt request output unit 13 non-maskable interrupt priority register

Claims (1)

[Claims] 1. An interrupt level register for inputting a plurality of interrupt requests and holding an interrupt level corresponding to each interrupt request input, and a non-maskable interrupt during setting and setting by an interrupt response cycle of the non-maskable interrupt. An interrupt processing flag that masks the request level output, an interrupt request output section that outputs the interrupt request level by using the output of the interrupt level register and the output of the non-maskable interrupt processing flag, and a non-maskable interrupt by the interrupt level register Holds the priority of the set interrupt and holds the priority of the non-maskable interrupt permitted to be processed in the interrupt response cycle of the non-maskable interrupt. If another non-maskable interrupt occurs during processing, the mask is processed. If the interrupt with the higher priority occurs by comparing the priority with the disabled interrupt, The interrupt processing apparatus including a non-maskable interrupt priority register to allow to release the disable interrupt processing flag interrupt request output.