JPH0691512B2 - Method and apparatus for detecting error in data transferred on transmission line - Google Patents

Description

TECHNICAL FIELD The present invention relates to detection of an error that occurs during serial transfer of an information signal in a transmission line of an information processing device.

An information processing device is a device that integrates a computer, a storage device, and other data processing devices, and is an interface that connects a first device such as a channel device with an input / output device (IO device) and a channel device and an IO device, for example. It is composed of a second device including a transmission line such as a line. For simplification of description below, a channel device, an IO device, and an interface line are defined as a first device, a second device, and a transmission line, respectively. Error detection is performed by an interface circuit connected to the interface line, and the interface circuit is provided in each of the channel device and the IO device.

As the processing speed or capacity of the data processing device increases, the amount of signal transferred on the interface line also increases. The signal transferred on the interface line, hereinafter referred to as "information signal", consists of "data signal" and "control signal". The data signal means, for example, a signal stored in or read from a storage device such as a main storage device of a data processing device or a buffer memory of an IO device.
A control signal refers to a signal that controls a data signal that is sent to, or stored in or read from, a device in a data processing device, for example.

BACKGROUND ART Before then, coaxial cables were used for interface lines. However, when the coaxial cable is used, the stray capacitance is distributed along the coaxial cable, so that the information signal cannot be transmitted at high speed. Therefore, many coaxial cables, more than 100, had to be used as interface lines. Furthermore, since each coaxial cable is not small, it requires a large space. Therefore, in order to save space, there is a parallel signal conversion technique (PS conversion technique) that converts parallel information signals into serial signals. However, the PS conversion technique has not been used in practice because the transfer of information signals takes a lot of time due to the stray capacitance. The PS conversion technique became widely used only after the optical fiber technology was established.

As is well known, optical fibers are extremely small and have a high signal transfer rate. The above PS conversion is
Only by using this optical fiber for the interface line can the effect be exhibited, and therefore the information signal can be converted and transferred in the form of a continuous frame. A data buffer is used to convert the information signal into a series of frames.The information signal is stored in the data buffer for several bytes each time it is transferred, and PS conversion is performed by reading it one by one. It However, as long as the data buffer is used, the speed of signal transfer is limited to low speed, and a trouble called "command overrun" often occurs. These problems were solved by putting dummy code in the frame instead of using the data buffer. The dummy code is always transferred on the interface line between the channel device and the IO device even when there is no transfer of the information signal, and when the information signal to be transferred is given, it is replaced with the information signal of several bytes. To be However, the dummy code method and its circuit still have a problem, and the present invention solves the problem.

Prior to disclosing the present invention, a conventional frame structure, a dummy code and an information signal in the frame will be described with reference to FIGS. 2 and 3.

FIG. 2 shows an example of the structure of the frame 30. The frame 30 includes a frame header 1, a plurality of signal transfer units 32, for example, 32 signal transfer units for setting a control signal 3, a data signal 4 and a dummy code. 2 and check code 5. Here, frame header 1 is frame 30
Placed at the beginning of a cyclic redundancy check code (CRC)
5 is placed in the last part of the frame 30, and the control signal 3, the data signal 4 and the dummy code 2 are arranged in the signal transfer unit 32. The numbers in parentheses in FIG. 2 indicate the positions of the control signal 3, the data signal 4 and the dummy code 2, respectively. The frame header 1 is located at the beginning of the frame 30 and indicates that the frame 30 starts, whereby the frames are synchronized. The CRC code 5 is for detecting an error in the signal in the signal transfer unit 32 as shown by a line 34 connecting the check code 5 from each signal unit 32 in FIG.

In the prior art, this dummy code 2 has a problem when an error is detected.

FIGS. 3A to 3D show the configuration of the signal transfer unit 32. FIG. 3 (a) shows the transfer of the dummy code 2, FIG. 3 (b) shows the control signal 3, FIG. 3 (c) shows the 1-byte data signal 4, and FIG. 3 (d) shows the 2-byte data signal 4. Fig. 3 (a) ~
As shown in (d), each signal transfer unit 32 has an 18-bit location from bit 0 to bit 17, and has 0 to 8 and 9 to
It is divided into two subunits, each consisting of 17 bit locations. The first and second bit positions (bits 0 and 1) and (bit 9 and 9) of subunits 21 and 22, respectively.
10) are attribute flags, respectively. That is, “00” in FIG. 3A is for the dummy code 2, “01” in (b) is for the control signal 3, and “1” in (c) or (d) is for the data signal 4. It is an attribute flag.

When there is no information signal to be sent, the attribute flag becomes "00" and only the dummy code 2 is contained in the subunits 21 and 22, as shown in FIG. 3 (a).

When the control signal 3 to be sent comes, the same control signal 3 is set in the subunits 21 and 22 as shown in FIG. 3 (b). This is because they are compared with each other in order to detect an error occurring in the control signal 3 during signal transfer. Since the control signal 3 is very important for the control of the data signal 4, a double check is thus made on the control signal 3.

When the 1-byte data signal is transmitted, the attribute flag of the subunit 21 is set to 1 and the attribute flag of the subunit 22 is set to 0 as shown in FIG. 3 (c).
Next, the 1-byte data signal is set to bits 1 to 8 of the subunit 21 instead of the dummy signal 2 and to the subunit 21 so that the bit form of the normal data signal 4 is inverted. The 1-byte data signal in the form of the inverted 1-byte data signal is set in bits 10 to 17 of the subunit 22. This is to prevent the data signal 4 from being confused with the control signal 3. That is, if the first bit of the 1-byte data signal is 1 and the 1-byte data signal set in bits 10 to 17 is not inverted, bit 0 of the attribute flag will be confused with 0, When it becomes "01", the first 2 bits of both subunits 21 and 22 are as if they were attribute flags for control signal 3,
Will be taken.

When the 2-byte data signal is transferred, the attribute flags become 1 in bits 1 and 9 as shown in FIG. 3 (d). And the 2-byte data signal is the subunit 21
And 22 are set to bits 1 to 8 and bits 10 to 17, respectively. If the data signal is 2 bytes or more, for example, 3 bytes, the third byte of the 3-byte signal is set to the next subunit, and then the attribute flags of the conventional subunit and the next subunit are set to "1", respectively. "I will.

Figure 1 consists of optical fiber, channel unit 1a
FIG. 3 is a block diagram illustrating a basic configuration of an interface line connecting between the input / output unit 1b and the input / output unit 1b. The interface line 1c consists of two lines. That is, the line for signal transfer from the channel unit 1a to the IO unit 1b
1c-1 and a line 1c-2 for signal transfer from the IO unit 1b to the channel unit 1a, as shown in FIG. 1, the channel unit 1a and the IO unit
Both 1b are devices for transmitting and receiving information signals. When the receiving device receives the frame 30, the receiving device first checks the attribute flag. If the attribute flag is "00", the receiving device acknowledges that only the dummy code 2 is received, and as a result, the receiving device does not work. If the attribute flag is “01”, the receiving device acknowledges that the control signal 3 has been sent, and the receiving device includes “read”, “write”, “accept”, “end”, etc. given by the control device. Work according to instructions like "Connect". If the attribute flag is "1x", the receiving device acknowledges that the data signal 4 has been sent. Then, the receiving device functions, for example, to store the data signal 4 in the buffer memory according to the instruction of the control signal 3.

When an error is detected in the information signal by the CRC code 5 in the receiving device, at least one frame containing the error has to be retransmitted, and sometimes a considerable amount of information signal is retransmitted together with a plurality of frames. Occur. On the other hand, since the optical fiber has come to be used for the interface line, the signal transfer speed is remarkably increased, and therefore the transfer frequency of the dummy code 2 is also increased. Therefore, in the information processing device, the attribute flag “00”
The re-transmission of the signal due to the error causes an overall decrease in the signal transfer rate.

Especially, the data signal 4 stored in the buffer memory of the IO unit 1b is read out and transmitted through the optical fiber 1c-2,
When sent to the channel unit 1a, most of the dummy code 2 is transferred and sometimes the control signal 3 is also sent to the optical fiber 1c-2.
Sent through. In such cases optical fiber 1c-1
If an error confusing with the control signal 3 occurs in the dummy code 2 passing through, not only the dummy code 2 but also the data signal 4 transferred through the optical fiber 1c-2 must be retransmitted. I won't. because,
It is considered that an error has occurred in the control signal 3 sent through the optical fiber 1c-1, and the control signal 3 is very important for controlling the data signal 4.
The error of the dummy code 2 can be ignored, but in the prior art, there was no way to confirm which is the true error, so it could not be ignored. The above is just one example, and there were many similar problems in data processing systems. These problems have caused a decrease in the overall signal transfer rate in the data processing system. And this kind of problem could not be solved as long as the dummy code 2 is the target of error detection.

DISCLOSURE OF THE INVENTION It is an object of the present invention to reduce the frequency of re-transmission of an information signal due to a dummy code error when the information signal is continuously transmitted through an interface line formed of an optical fiber in a data processing system.

Another purpose is to increase the transfer rate of information signals, and yet another purpose is to increase the amount of information transmitted over the interface lines.

These objects are achieved by excluding the dummy code from the detection target of the information signal in the frame. This exclusion is performed by an interface circuit which is connected at both ends of the interface line and includes a transmission circuit and a reception circuit, respectively. But when this exclusion was made,
It should be considered that the attribute flag "00" for the dummy code 2 may be converted to "01" as an error confusing with the attribute flag for the control signal. Therefore, exclusion must be performed in consideration of the error caused by the attribute flag “00”. In consideration of the above, exclusion is performed in the next step. (For ease of understanding, the description of the steps is defined as follows: In the description of the steps, two frames are used, which are called the first frame and the second frame, respectively, and the first frame is the first frame. It is assumed to be immediately before two frames.) Step 1) In the transmission circuit, a new flag called a first flag for notifying whether or not the first frame has a control signal in the frame header 1 of the second frame Set a flag.

Step 2) In the transmission circuit, the attribute flag “01” is added to the first frame in the frame header 1 of the second frame.
There is provided another new flag called the second flag in order to notify the least significant bit indicating whether the number of is an odd number or an even number.

Step 3) In the transmitting circuit and the receiving circuit, it is detected whether or not the attribute flag "00" for the dummy code 2 is present in the first frame, and every time the attribute flag "00" is detected in the first frame. Make a bit “1” in.

Step 4) In order to exclude the attribute flag “00” and the dummy code 2 from the CRC target for the information signal in the first frame, use the bit “1” obtained in Step 3) above. The transmission circuit and the reception circuit CRC unit are controlled so as to stop the CRC count of the attribute flag “00” and the dummy code 2 in the first frame.

Step 5) In the receiving circuit, the CRC code 5 of the first frame is compared with that in the receiving circuit, and if they do not match, an output bit "1" is created.

Step 6) The control unit of the data processing system gives the receiving circuit whether or not there is at least one data signal 4 in the first frame, and if there is the data signal 4, a bit "1" is created.

Step 7) In the receiving circuit, it is detected whether or not the attribute flag "01" for the control signal 3 is included in the first frame, this is compared with the first flag, and if they match, the output bit " Make 1 ".

Step 8) In the receiving circuit, the flag "01" in the first frame is counted, the least significant bit of that number is created and compared with the similar least significant bit of the second flag. If both least significant bits match, bit "0" is created.

Step 9) Bit “1” in step 7), step 8)
If "0" is output at, bit "0" is created.

Step 10) AND of outputs from steps 5) and 6)
Take

Step 11) OR the outputs of steps 9) and 10).

In steps 3), 4) and 5), by excluding the attribute flag “00” and the dummy code 2 in the first frame,
The error detection of the information signal in the first frame is performed, and step 6) should retransmit the information signal of the first frame when there is a CRC error in the first frame and the data signal 4 is present. Is a step for taking into account that it has to be decided that is, and the other steps are for taking into account the error due to the attribute flag “00”. In particular, as described in step 2), since the second flag is provided in the second frame, the re-transmission of the information signal of the first frame is performed even if the control signal 3 is in the first frame together with the dummy code 2. It becomes unnecessary, and the attribute flag "00" changes to "01".

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an interface line connecting a channel unit and an IO unit in a data processing system.

FIG. 2 is a diagram showing the structure of a frame which is the object of CRC detection in the conventional example.

FIG. 3A is a diagram showing a signal transfer unit in a frame in which a dummy code is set.

FIG. 3B is a diagram showing a signal transfer unit in which a control signal is set.

FIG. 3 (c) is a diagram showing a signal transfer unit in which a 1-byte data signal is set.

FIG. 3 (d) is a diagram showing a signal transfer unit in which a 2-byte data signal is set.

FIG. 4 is a diagram in which an information signal is written, showing the configuration of a frame which is the object of CRC detection in the present invention.

FIG. 5 is a diagram showing the structure of the frame header in the first embodiment of the present invention.

FIG. 6 is a diagram showing the structure of a frame header in the second embodiment of the present invention.

FIG. 7 is a block diagram of a conventional transmission circuit.

FIG. 8 is a block diagram of a conventional receiving circuit.

FIG. 9 is a block diagram of a CRC unit in a conventional transmission circuit.

FIG. 10 is a block diagram of a CRC unit in a conventional receiving circuit.

FIG. 11 is a block diagram of a transmission circuit according to the first embodiment of the present invention.

FIG. 12 is a block diagram of a receiving circuit according to the second embodiment of the present invention.

FIG. 13 is a block diagram of the CRC unit in the transmission circuits of the first and second embodiments of the present invention.

FIG. 14 is a block diagram of a CRC unit in the receiving circuit according to the first and second embodiments of the present invention.

FIG. 15 is a block diagram of a transmission circuit according to the second embodiment of the present invention.

Finally, FIG. 16 is a block diagram of a receiving circuit according to the second embodiment of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION Prior to disclosing an embodiment of the present invention, a transmission circuit 100 and a reception circuit 200 of a conventional example will be described with reference to FIGS.
The transmission CRC unit 150 of the conventional transmission circuit 100 and the reception CRC unit 250 of the conventional reception circuit 20 will be described with reference to FIGS.

FIG. 7 shows a conventional transmission circuit 100 in an interface circuit in, for example, the channel unit 1a (see FIG. 1).
It is a block diagram of. FIG. 7 shows how an information signal composed of a plurality of 9-bit signals is sent to the register (REG) 101. The bit position of the 9-bit signal is shown in FIG.
Bits 0 through 8 or bits 9 through 17, as shown in (d). The 9-bit signal is also sent to the multiplexer (MPX) 102 and the Tx-CRC unit 150 through the REG 101. Tx-
CRC unit 150 creates CRC code 5, which is MPX10
It consists of a CRC circuit that acts to send to 2. In MPX102, 9-bit signal and CRC code 5 are sequentially selected, and code converter 103
Sent to. The code converter 103 converts each of the 9-bit signal and the CRC code 5 into a 12-bit signal in order to make the existence ratio of bit 0 to bit 1 of the 12-bit signal approximately 50%. This is usually the well known method of signal processing. The signal converted to 12 bits is MPX1 that gives the frame header pattern to frame header 1.
Sent to 04. The frame header pattern is, for example, a frame header pattern generator (not shown in FIG. 10) in the interface circuit of the channel unit 1a.
Sent from. Frame header pattern signal, 12
Bit signal and CRC code 5 are sent to shift RGE105,
As shown in FIG. 2, it is converted into an information signal arranged in frames. That is, the shift REG 105 functions as a parallel / serial converter for forming an information signal. The information signal from the shift REG 105 is sent to the optical transmitter 107 to be converted into an optical information signal through the REG 106, and is then sent to the receiving circuit through, for example, the optical fiber 1c-1. The circuit with reference number 110 is a transmission frame control circuit (Tx-FR
AME CONT), where a large amount of timing signals are provided using the original clock signal generated by the clock generator 113. Timing signals are transmitted through the lines from Tx-FRAME CONT110 (couplings are marked with a number *) to register, MPX and CRC in order to properly operate the parts and units described above to form the frame shown in FIG. It is sent to each unit 150.

FIG. 9 shows a conventional Tx-CRC unit 150 in the transmission circuit 100.
It is a block diagram of. Tx-CRC unit 150 consists of CRC code generator (CRC GEN) 151, CRC multiplexer (CRC MPX)
152, a CRC register (CRC REG) 153 and a feedback line 154. Information signal from REG101 is CRC
It is sent to CRC GEN 151 which generates the code. The output of CRC GEN151 is sent to CRC MPX152. Thereby, the timing of signal detection in the frame is selected, and the frame header 1 is excluded from the detection target. The output of CRC MPX152 is sent to CRC REG153. There, the timing to output the CRC code is determined by the timing signal (* 1) from Tx-FRAME CONT110. CRC REG1
The output of 53 is sent to the MPX102, and at the same time, the output is fed to the CRC GEN by the feedback line 154.
Feedback to 151 and CRC MPX152. This feedback is provided on lines 111 and 112 as shown in FIGS.
This is for excluding the frame header 1 in cooperation with the timing signal sent from the Tx-FRAME CONT 110 through.

FIG. 8 is a block diagram of a conventional receiving circuit 200 in an interface circuit provided in, for example, the IO unit 1b (see FIG. 1). In the figure, for example, optical fiber 1c
The optical information signal sent from the transmission circuit 100 in the channel unit 1a via -1 or the like is received by the optical receiver 201, where the optical information signal is converted into an electronic information signal.
The information signal from the optical receiver 201 is sent to the shift REG 202. Therefore, the information signal is of serial transfer type together with the frame,
It is converted into a parallel type consisting of 12-bit signals and sent to REG203. The 12-bit signal from REG 203 is sent to code converter 204, where the 12-bit signal is converted to a 9-bit signal. The 9-bit signal coming from the code converter 204 is sent to the REG 205, the 9-bit signal from the REG 205 is sent to the receiving circuit 200 as an output, and at the same time the 9-bit signal is CR.
It is also sent to the Rx-CRC unit 250 which generates the C code 5.

FIG. 10 is a block diagram of a conventional Rx-CRC unit 250. As shown, the Rx-CRC unit 250 is a CRC GEN25
1, CRC MPX252, CRC REG253 and feedback line 2
It is composed of 54, and these circuits are Tx-C described in FIG.
Functions the same as in RC unit 150. Rx-CRC
CRC code 5 from unit 250 is a CRC code comparator (CRC
COMP).

The 9-bit signal coming from the REG 205 is also sent to the CRC COMP 206, where the CRC code 5 from the transmission circuit 100 is selected by the timing signal from the receive frame control circuit (Rx-FRAME CONT) 210. In the CRC COMP206, the CRC code 5 and Rx-CRC unit sent from the transmission circuit 100
The CRC codes 5 made by 250 are compared with each other, and if there is an error in the signal in the frame, the error signal is output through a flip-flop (FF) circuit.

The 12-bit signal from the REG 203 is sent to a frame header comparator (FRAME COMP) 208, which compares the frame header of the received signal with the frame header of the frame header pattern generator. Although not shown in FIG. 8, the frame header pattern generator is provided in the interface circuit or the like in the IO unit 1b and produces the same pattern as that produced by the transmission circuit 100. The output from FRAME COMP 208 is sent to Rx-FRAME CONT 210, where a large amount of timing signals are generated in synchronization with the output from FRAME COMP 208. The timing signal is sent to the REG, MPX, comparator and CRC unit 250 as shown in FIG.

Conventionally, error detection of signals has been performed in this manner not only for the control and data signals 3 and 4, but also for the dummy code 2. As mentioned earlier, it slowed down the signal transfer through the interface line.

The present invention is to exclude the dummy code 2 from the object of error detection of the entire information signal. That is, as indicated by the line 41 in FIG. 4, the control signal 3 and the data signal 4 are the targets of error detection. FIG. 4 shows the same structure as the frame 30 shown in FIG. As can be seen, in the present invention, the number of error detection targets is reduced compared to FIG. 2, which results in an increased signal transfer rate.

The invention will be described in detail using two embodiments, a first and a second. In the two embodiments, the attribute flag "00" for the dummy code 2 and the dummy code itself are naturally excluded from the error detection target of the first frame. As described above, the first and second frames are the first frame and the second frame.
It shall be immediately before the frame.

Further, in the first embodiment, the conventional transmitting circuit 100 and the receiving circuit 200 are improved so that they occur when the attribute flag "00" is changed to "01" in the first frame and the data signal 4 is not present in the frame. The conventional re-transmission of the information signal was
It has been improved so that it is no longer done. This improvement cooperates with the newly provided first flag 13 in the frame header 1 of the second frame as shown in FIG. 5 in order to inform the receiving circuit whether the receiving circuit has at least one control signal. Done. In FIG. 5, the number (13) is the first flag 13
Shows the set position of.

The block diagram of FIG. 11 shows the transmitting circuit 30 of the first embodiment of the present invention.
It is 0. The same numbers as in FIG. 7 indicate the same parts.

In FIG. 11, the attribute flag "00" is detected by the NOR 121, and the bit 1 is created only when "00" of the first frame is input. Bit 1 is sent to Tx-CRC unit 1500 through flip-flop circuit (FF) 122 for reset. The Tx-CRC unit 1500 has the same configuration as the Tx-CRC unit 150 shown in FIG. In FIG. 13, the same numbers as those in FIG. 9 indicate the same parts, and the configuration is the first part.
The frame attribute flag “00” and the dummy code 2 are changed to be excluded from the CRC detection target. This modification is done by applying bit 1 provided from FF 122 through line 123. That is, when bit 1 from FF122 is sent to CRC MPX152, attribute flag "00"
CRC is the timing to create CRC code for dummy code 2
It is removed by MPX152, and as a result, the flag "0" of the first frame
CRC codes that detect 0 "and dummy code 2 are excluded.

In FIG. 11, the attribute flag “01” for the control signal 3
Is included in the first frame, NOT131 and AND132 detect the "01" and form bit 1. Bit 1 is F
It is sent to the MPX 104 through F133, where bit 1 is added to the frame header 1 as the first flag 13 as shown in FIG.

FIG. 12 is a block diagram of the receiving circuit 400 according to the first embodiment of the present invention. In the figure, the same numbers as in FIG. 8 indicate the same parts.

In FIG. 12, NOR221, FF222 and Rx-CRC unit 250
0, like the NOR 121, FF 122 and Tx-CRC unit 1500, functions to exclude the attribute flag “00” and the dummy code 2 from the CRC detection target of the first frame. FIG. 14 is a block diagram of an Rx-CRC unit 2500 that operates similarly to the Tx-CRC unit 1500 of FIG.

In FIG. 12, when bit 1 of the first flag 13 is included in the second frame, bit 1 is detected by the first flag detector 231 and bit 1 is created. First flag detector 231
1 is sent to AND209 through OR242 which outputs the final error detection output signal of the receiving circuit 400. Another input is sent from the FF207 to the AND209 so that bit 1 is sent when there is a CRC error as described in FIG. The FF 241 informs the receiving circuit 400 whether or not the data signal 4 is transferred together with the first frame. When the data signal 4 is transferred through the interface line together with the first frame, FF241
(Not shown in FIG. 12) receives information from the control unit of the data processing system and outputs bit 1 to OR242.

In conclusion, the error detection output of the receiving circuit 400 is obtained as follows.

1) When the FF207 produces an output of bit 1, that is, when there is no CRC error in the first frame, the output from AND209 is 0, which means that there is no error in the first frame.

2) When FF207 outputs bit 1, that is, there is a CRC error, but FF241 and the first flag detector 231 output bit 0, in other words, both data signal 4 and control signal 3 are in the first frame. When not inside,
The output from AND209 becomes 0. This is an error due to the attribute flag "00" even if there is an error in the first frame, and this error is ignored.

3) When FF207 outputs bit 1 and either FF241 or the first flag detector 231 outputs 1, the output of AND209 becomes 1. This is because even if a CRC error is actually created by a simple error of the attribute flag “00”, where “00” is “1X” or “01”, the data signal 4 or control signal of the first frame 3 must be considered to be in error, so bit 1 means that it must be in the first frame. Then, although not shown in FIG. 12, the last error output of 1 is used for the retransmission of the first frame.

Thus, according to the first embodiment, when the dummy code 2 is only present in the first frame and one (or more) attribute flag "00" is changed to "01", the error from the CRC detection is ignored. . That is, in the first embodiment, only the attribute flag "00" is the object of CRC detection. This is because the control signal 3
This is because, as shown in FIG. 6B, the data is always sent in duplicate. As a result, errors from the control signal 3 itself can be detected by comparing the double control signals. In the case of the data signal 4, since double transfer is not performed, error detection using the attribute flag “0x” cannot be performed. This is because the FF241 is provided in the receiving circuit.

However, the first embodiment has the following problems. That is, when the control signal 3 is included in the first frame,
Even if it is a CRC error due to the error of the attribute flag "00",
It cannot be ignored. The second embodiment solves this problem.

In the second embodiment, the second flag 14 is, as shown in FIG.
It is also provided in the frame header 1 of the second frame. The second flag 14 informs the least significant bit of the number of the control signals 3 of the first frame. Figures 15 and 16 show
2 illustrates a transmitter circuit 500 and a receiver circuit 600 according to a second embodiment of the present invention. In FIG. 15 (and 16), the same numbers as in FIG. 11 (and 12) represent the same parts.

In the transmission circuit 500 of FIG. 15, the attribute flag “01” is NOT131.
Each time it is sent to AND132, bit 1 is output from AND132 and its output is sent to MPX 104 to provide the first flag 13 in the second frame. This is the same as in FIG. In the second embodiment, bit 1 is sent to the counter 134, and in order to create the second flag 14 in the frame header 1 of the second frame, this counter 134 sets the attribute flag "01" of the first frame. The least significant bit of the number is created and sent on line 136 to the MPX 104. Therefore, as shown in FIG. 6, the first and second flags 13 and 14 are arranged in the frame header 1 of the second frame.

In the receiving circuit 600 of FIG. 16, the attribute flag “01” in the information signal received in the first frame is checked by NOT232 and AND233, and at the same time, the double check of the control signal 3 is performed by the control signal comparator (CONT- SIG COMP) 261.
As described with reference to FIG. 3 (b), the control signal 3 is doubly set in the subunits 21 and 22. Therefore, the duplicate control signal 3 in the subunits 21 and 22 is fed from the REG205 input and output respectively to the CONT-SIG COMP2.
It is sent to 61 and compared with each other. Bit 1 is made from CONT-SIG COMP261 when double control signals match, and AN
It is sent to D233. Therefore, AND233 produces bit 1 as an output as long as the true attribute flag for control signal 3 is "01". That is, AND233 never creates bit 1 even if the attribute flag "00" changes to "01" during signal transfer. The output "1" from AND233 is sent to the counter 235, where the attribute flag "0" of the first frame is sent.
The least significant bit of the count number of 1 "is made and output. The least significant bit from the counter 234 is compared with the second flag 14 in the second flag comparator 235, and when they do not match, the The two flag comparator outputs bit 1, where the second flag 14 bit is the line 238.
Via REG203. The output from the comparator 235 and the bit of the first flag 13 are sent to the AND236, and the output is sent to the OR243 through the FF237. AND242
The output from is also sent to OR243, resulting in AND24
Either 2 or the output from AND236 becomes "1", and the OR243 outputs bit 1 for indicating that there is an error in the first frame. That is, the error detection output of the receiving circuit 600 is obtained as follows.

1) When the output bits of FF207 and AND236 are "0", that is, when there is no CRC error in the first frame, O
The output of R243 is "0", which means that there is no error in the first frame.

2) When the output bit of FF207 is "1", that is, there is a CRC error, but when FF241 outputs bit 1, the output from OR243 is "1". This means that as long as the data signal 4 is in the first frame, it is determined that there is one error in the first frame.

3) When the output bit from FF207 is "1", the output from FF241 is "0" and the output of OR243 is "0" unless the output of AND236 is "1". When the data signal 4 is not in the first frame, it means that the CRC error is ignored even if the control signal 3 is present, because the number of control signals 3 is the same and the attribute flag "00" itself is an error. This is because it is determined that they have.

In this way, the problem in the first embodiment is solved in the second embodiment.

In the first and second embodiments, the transmit and receive circuits are described as circuits within a device, such as a channel unit or IO unit, in a data processing system. However, the present invention is applicable to any system that transfers a signal from a transmitting means to a receiving means through a signal transferring means.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Ho Mikuni 2-13-13 Edakita, Midori-ku, Yokohama-shi, Kanagawa 6th Ichigao Dormitory

Claims (8)

[Claims] 1. A method for detecting an error in an information signal transferred from a signal transmission means to a signal reception means through a signal transfer means in a plurality of frames arranged based on a serial transfer format, which method is at least as follows: When there is no information signal in the frame, a dummy code is provided in the frame instead of the information signal in the signal transmitting means; in the signal transmitting means, the information signal and the dummy code are included in the frame. An attribute flag indicating existence is provided in the frame; in the signal transmitting means, in order to detect the attribute flag and the information signal error in the frame, excluding the attribute flag of the dummy code and the dummy code, A first check code is provided in the frame; the attribute flag of the dummy code and the A second check code is provided by using the received information signal and dummy code and those attribute flags to detect an error of the attribute flag and the information signal in the frame, except for the dummy code. Detecting the first check code; and comparing the first check code and the second check code in the signal receiving means. 2. The method according to claim 1, wherein the first and second check codes are cyclic redundancy check codes. 3. An error of an information signal including a first signal and a second signal transferred from the signal transmission means to the signal reception means through the signal transfer means in a plurality of frames arranged based on the serial transfer format is checked. A method, wherein the first signal refers to a signal that is doubly arranged in a frame, the second signal refers to a signal provided in the frame, and the third signal is The second signal is a signal which informs the signal receiving means that the second signal is in the frame, and the method comprises at least the following steps: In the signal transmitting means, when there is no information signal in the frame, Instead, a dummy code is provided in the frame; In the signal transmitting means, an attribute flag is provided to inform that the information signal and the dummy code are present in the frame; In the stage, the attribute flag of the dummy code and the dummy code are removed, and a first check code for checking an error of the attribute flag and information signal in the frame is provided; in the signal transmitting means, in the first frame A first flag is provided at the beginning of the second frame to notify whether or not there is a first signal in the first frame and the second frame.
A frame refers to two consecutive frames arranged so that the first frame is immediately before the second frame; the first frame except the attribute flag of the dummy code and the dummy code in the signal receiving means. A second check code for checking an error of the attribute flag and the information signal therein; a first check code is detected in the signal receiving means; a first check code and the second in the signal receiving means
The check codes are compared with each other, and if there is an error in the comparison, a first output for notifying the error is generated, and if there is no error in the comparison, a second output for notifying the error is generated; If the first flag is detected, and if the first flag is detected, a third output indicating that the first signal was present in the first frame is made, and if the first flag is not detected, , Producing a fourth output notifying that the first signal was not present in the first frame; the signal receiving means receives the information whether the second signal is present in the first frame by the third signal Then, if the information informs that the second signal is present in the first frame, a fifth output that informs the information is produced, and if it is informed that it is not present, the second signal is given in the first frame.
Producing a sixth output indicating that no signal is present; when the second output is present at the signal receiving means,
Outputting a first final output signal informing that there is no error in the first frame; the signal receiving means, if the first output, the fourth output and the sixth output are present, the first final output Outputting an output signal; in the signal receiving means, when there is only the first output and the third output, outputting a second final output signal indicating that an error exists in the first frame; and a signal The receiving means outputs the second final output signal when the first output and the fifth output are present. 4. The method of claim 3, wherein the method further comprises at least the following steps: Counting the number of attribute flags of the first signal in the first frame in the signal transmitting means, the least significant of the number. A bit is created; in the signal transmitting means, a second flag is provided at the head part of the first frame in order to inform the least significant bit; in the signal receiving means, a double check of the first signal is performed, and depending on the result of the check The seventh output for notifying that the first signal has been correctly received is made, and the eighth output for notifying that the first signal has not been correctly received is made; in the signal receiving means, the attribute of the first signal in the first frame A flag is detected and the number of the first signals in the first frame is counted to create the least significant bit of the number; and in the signal receiving means, the least significant bit counted by the signal receiving means and the Comparing the two flags with each other, and producing a ninth output indicating that the least significant bit and the second flag match with each other according to the comparison result, and that the least significant bit and the second flag do not match with each other. Producing a tenth output for notifying that the third output, the seventh output and the ninth output
If the outputs are obtained, create an eleventh output indicating that those outputs are present; and, if there is not only the first output and the third output but also the eleventh output in the signal receiving means, the first output Output the final output signal. 5. The method according to claim 3 or 4, wherein the first check code generated by the signal transmitting means and the second check code generated by the signal receiving means are cyclic redundancy check codes. 6. An information signal transferred from a signal transmission means to a signal reception means through a signal transfer means in a plurality of frames arranged according to a continuous transfer format.
A device for detecting an error including a signal and a second signal,
Here, the first signal refers to a signal that is doubly arranged in a frame, the second signal refers to a signal provided in a frame, and the third signal refers to the second signal. This is a signal for notifying the signal receiving means of the information that it is in a frame, and the apparatus has at least the following configuration: In the signal transmitting means, when the information signal is not included in the frame, instead of the information signal. A means for preparing a dummy code in the frame; a means for providing each attribute flag in the frame in the signal transmitting means in order to inform that the information signal and the dummy code belong to the frame; , A first check in the frame to check the attribute flag of the dummy code and the error of the attribute signal and information signal in the frame excluding the dummy code A means for providing a code; a means for providing a first flag in the head portion of the second frame in the signal transmitting means for notifying whether or not the first signal is present in the first frame, wherein the first flag is provided. The frame and the second frame refer to two consecutive frames in which the first frame is arranged immediately before the second frame; in the signal receiving means, the attribute flag of the dummy code and the dummy code are excluded. Means for providing a second check code for checking the error of the attribute flag and the information signal in one frame; A means for detecting the first check code in the signal receiving means; A first check code in the signal receiving means And the second
Means for comparing the check codes and means for producing a first output notifying that an error has been detected by the comparing means,
And means for producing a second output notifying that no error has been detected by the comparing means; in the signal receiving means, if the first flag is detected in the second frame and the first flag is detected, in the first frame Means for producing a third output notifying that the first signal was present and a fourth output notifying that the first signal was not present in the first frame if the first flag was not detected; In the signal receiving means, means for receiving the information as to whether or not the second signal is present in the first frame by the third signal, and the presence of the second signal when the second output signal is present in the first frame. Means for producing a fifth output for notifying and means for producing a sixth output for notifying that the second signal is not present when the second signal is not present in the first frame; the second output is output by the signal receiving means The first output signal for notifying that the error does not exist in the first frame when the first output signal is present, the signal receiving means has the first output, the fourth output and the sixth output A means for causing the first final output signal to be output to the signal receiving means; a second final output signal notifying that there is an error in the first frame when only the first output and the third output are present in the signal receiving means. Means for outputting; and, in the signal receiving means: means for outputting the second final output signal when the first output and the fifth output are present. 7. The apparatus according to claim 6, further comprising at least the following structure: In the signal transmitting means, the number of attribute flags of the first signal in the first frame is counted, and the maximum number of the attribute flags is counted. Means for producing a lower bit; means for providing a second flag at the head of the first frame in order to inform the least significant bit in the signal transmitting means; means for performing a double check of the first signal in the signal receiving means, Means for producing a seventh output for notifying that the first signal is correctly received and an eighth output for notifying that the first signal is not correctly received according to the check result; Means for detecting the attribute flag of one signal and counting the number of the first signals in the first frame to generate the least significant bit of the number; Means for comparing the least significant bit counted with the second flag and the comparison result, and producing a ninth output for notifying that the least significant bit and the second flag match, Means for producing a tenth output for notifying that the lower bit and the second flag do not match; signal receiving means for notifying that the third output, the seventh output and the ninth output are present Means for producing 11th output; and means for outputting the first final output signal when not only the first output but also the 11th output is present in the signal receiving means. 8. A device according to claim 6 or 7, wherein
The means for producing the first check code by the signal transmitting means and the means for producing the second check code by the signal receiving means are cyclic redundancy check circuits, respectively.