JPH0669270A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPH0669270A
JPH0669270A JP4217581A JP21758192A JPH0669270A JP H0669270 A JPH0669270 A JP H0669270A JP 4217581 A JP4217581 A JP 4217581A JP 21758192 A JP21758192 A JP 21758192A JP H0669270 A JPH0669270 A JP H0669270A
Authority
JP
Japan
Prior art keywords
bonding
film
wire
bonding pad
aluminum film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4217581A
Other languages
Japanese (ja)
Inventor
Tadashi Fukui
正 福井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP4217581A priority Critical patent/JPH0669270A/en
Publication of JPH0669270A publication Critical patent/JPH0669270A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05073—Single internal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05557—Shape in side view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4807—Shape of bonding interfaces, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4845—Details of ball bonds
    • H01L2224/48451—Shape
    • H01L2224/48453—Shape of the interface with the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To prevent corrosion of bonding pad due to moisture, etc., and to simultaneously improve a connection strength of a bonding wire. CONSTITUTION:A second aluminum film (bonding pad) 4, and a boundary part between the film 4 and a cover film 3 are completely covered with a bonding wire 5 thereby to improve moisture resistance. Further, when the wire 5 is bonded, it is so bonded as to bite the film 4, and hence the connection strength of the wire 5 to the film 4 is increased.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、半導体集積回路装置に
関し、特にボールボンディングされるボンディングパッ
ド部の形状に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to the shape of a bonding pad portion to be ball-bonded.

【０００２】[0002]

【従来の技術】従来、半導体集積回路装置、特にボール
ボンィングされるボンディングパッドは、アルミニウム
等の金属により表面が平坦な正方形あるいは長方形に形
成され、この上にボール状の先端を持った金線等のボン
ディングワイヤがボンディングされるようになってい
る。2. Description of the Related Art Conventionally, a semiconductor integrated circuit device, particularly a bonding pad to be ball-bonded, is formed of a metal such as aluminum into a square or rectangular flat surface, on which a gold wire having a ball-shaped tip is formed. Bonding wires such as the above are to be bonded.

【０００３】従来のこの種のボンディングパッドの例を
図３（ａ），（ｂ）に示す。図３（ａ）は図３（ｂ）の
Ｂ−Ｂ線断面図、図３（ａ）は平面図である。これらの
図において、６は半導体基板であり、この上に第１アル
ミニウム膜１の一部を配設する。そして、この上に層間
膜２を形成しかつその一部を開口して第１アルミニウム
膜１を露出させ、更に第２アルミニウム膜４を正方形ま
たは長方形に形成する。その上で、この第２アルミニウ
ム膜４上の外周付近をカバー膜３で被覆することでボン
ディングパッドが形成される。このボンディングパッド
に対しては、先端をボール状にした金線等からなるボン
ディングワイヤ５を熱圧着等により接続している。An example of this type of conventional bonding pad is shown in FIGS. 3 (a) and 3 (b). 3A is a sectional view taken along line BB of FIG. 3B, and FIG. 3A is a plan view. In these figures, 6 is a semiconductor substrate, on which a part of the first aluminum film 1 is provided. Then, an interlayer film 2 is formed on this and a part of it is opened to expose the first aluminum film 1, and further the second aluminum film 4 is formed in a square or a rectangle. Then, a bonding pad is formed by covering the periphery of the second aluminum film 4 with the cover film 3. A bonding wire 5 made of a gold wire or the like having a ball-shaped tip is connected to the bonding pad by thermocompression bonding or the like.

【０００４】[0004]

【発明が解決しようとする課題】この従来のボンディン
グパッドの構造では、実際にボンディングされる第２ア
ルミニウム膜４の表面積よりもボンディングワイヤ５の
接着領域の方が小さく、必ず第２アルミニウム膜４の露
出部分が存在するため、半導体装置のパッケージ内に浸
入した水分等によって第２アルミニウム膜４、さらに第
１アルミニウム膜１が露出部分から腐食され、半導体装
置の耐湿性が劣化するという問題がある。In this conventional bonding pad structure, the bonding area of the bonding wire 5 is smaller than the surface area of the second aluminum film 4 to be actually bonded, and the bonding area of the second aluminum film 4 is always required. Since the exposed portion is present, there is a problem that the second aluminum film 4 and the first aluminum film 1 are corroded from the exposed portion by the moisture or the like that has entered the package of the semiconductor device, and the moisture resistance of the semiconductor device is deteriorated.

【０００５】さらに、従来のボンディングパッドは、ボ
ンディングワイヤ５がボンディングされる第２アルミニ
ウム膜４の表面が平面であるため、ボンディングワイヤ
５との接着強度が弱いという問題もある。Further, in the conventional bonding pad, since the surface of the second aluminum film 4 to which the bonding wire 5 is bonded is flat, there is a problem that the bonding strength with the bonding wire 5 is weak.

【０００６】[0006]

【課題を解決するための手段】本発明は、半導体基板上
にボンディングワイヤと接続されるボンディングパッド
を有する半導体集積回路装置において、ボンディングパ
ッドは上位層と下位層の２層からなり、上位層は、ボン
ディングワイヤとの接着領域よりも小さい範囲に円環状
の凸パターンを有し、その凸パターンの外周部までカバ
ー膜で覆われていることを特徴とする。According to the present invention, in a semiconductor integrated circuit device having a bonding pad connected to a bonding wire on a semiconductor substrate, the bonding pad is composed of two layers of an upper layer and a lower layer, and the upper layer is It is characterized in that it has an annular convex pattern in a range smaller than the bonding area with the bonding wire, and the outer peripheral portion of the convex pattern is covered with the cover film.

【０００７】[0007]

【実施例】次に本発明について図面を参照して説明す
る。図１は本発明の２層アルミニウムの半導体集積回路
装置についての第１の実施例を示す図で、図１（ａ）は
図１（ｂ）のＡ−Ａ線断面図、図１（ｂ）はその平面図
である。これらの図において、６は半導体基板であり、
この上に図外の素子に接続される第１アルミニウム膜１
の一部を配設する。そして、この上に層間膜２を形成
し、かつその一部を開口することにより第１アルミニウ
ム膜１を露呈する。更に、従来のものより厚く第２アル
ミニウム膜４を形成させ、その後エッチングを行なうこ
とによりボンディングワイヤの接着領域よりも狭い範囲
に円環状の凸パターンを形成する。その上で、この第２
アルミニウム膜上の凸パターンの外周部までカバー膜３
で被覆することでボンディングパッドが形成される。The present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a first embodiment of a two-layer aluminum semiconductor integrated circuit device of the present invention. FIG. 1 (a) is a sectional view taken along the line AA of FIG. 1 (b), and FIG. Is a plan view thereof. In these figures, 6 is a semiconductor substrate,
A first aluminum film 1 connected to an element (not shown)
A part of. Then, the first aluminum film 1 is exposed by forming an interlayer film 2 on this and opening a part thereof. Further, the second aluminum film 4 having a thickness larger than that of the conventional one is formed, and then etching is performed to form an annular convex pattern in a region narrower than the bonding region of the bonding wire. On top of that, this second
Cover film 3 up to the outer periphery of the convex pattern on the aluminum film
The bonding pad is formed by coating with.

【０００８】このように構成されるボンディングパッド
にボンディングワイヤ５を熱圧着等により接続すると、
ボンディングワイヤ５は、第２アルミニウム膜４を完全
に覆うことになる。このため外部から半導体装置のパッ
ケージ内に浸入した水分等によって第２アルミニウム膜
４等の腐食が防止され、半導体装置の耐湿性が著しく向
上する。また、ボンディングワイヤ５がボンディングさ
れる際に、第２アルミニウム膜４に食い込むようにボン
ディングされるため、ボンディングパッドに対するボン
ディングワイヤ５の接着強度が非常に大きくなる。When the bonding wire 5 is connected to the bonding pad thus constructed by thermocompression bonding or the like,
The bonding wire 5 completely covers the second aluminum film 4. Therefore, the second aluminum film 4 and the like are prevented from being corroded by moisture or the like that has entered the package of the semiconductor device from the outside, and the moisture resistance of the semiconductor device is significantly improved. Further, when the bonding wire 5 is bonded, the bonding is performed so as to bite into the second aluminum film 4, so that the bonding strength of the bonding wire 5 to the bonding pad becomes very large.

【０００９】図２は本発明の第２の実施例の平面図であ
る。この第２の実施例では、第２アルミニウム膜４の凸
パターンを円環状ではなく正方形または長方形で形成し
ている。この実施例においても第２アルミニウム膜４を
ボンディングワイヤ８の接着領域よりも狭い範囲に限定
していることで、半導体装置の耐湿性の向上とボンディ
ングワイヤ５の接着強度の向上とともに、凸パターンが
正方形あるいは長方形であるので設計段階においてデー
タ数を少なくすることができる。FIG. 2 is a plan view of the second embodiment of the present invention. In the second embodiment, the convex pattern of the second aluminum film 4 is formed in a square shape or a rectangular shape instead of a ring shape. Also in this embodiment, since the second aluminum film 4 is limited to a region narrower than the bonding area of the bonding wire 8, the moisture resistance of the semiconductor device is improved and the bonding strength of the bonding wire 5 is improved. Since it is a square or a rectangle, the number of data can be reduced at the design stage.

【００１０】[0010]

【発明の効果】以上説明したように本発明は、ボンディ
ングワイヤとボンディングパッドが実際に接着するボン
ディングパッドの最上位層において、最上位層とボンデ
ィングワイヤとの接着領域よりも小さい範囲に円状の凸
パターンを形成し、その凸パターンの外周部までカバー
膜で覆うことにより、ボンディング後にボンディングパ
ッドの露出部分、ボンディングパッドとカバー膜の境界
部分がなくなるため、耐湿性が著しく向上するという効
果がある。また、ボンディングパッドがボンディングワ
イヤに食い込むように接続されるため、その接着強度が
向上するという効果がある。As described above, according to the present invention, in the uppermost layer of the bonding pad where the bonding wire and the bonding pad are actually bonded, a circular shape is formed in a range smaller than the bonding area between the uppermost layer and the bonding wire. By forming a convex pattern and covering the outer periphery of the convex pattern with a cover film, the exposed portion of the bonding pad and the boundary portion between the bonding pad and the cover film are eliminated after bonding, so that moisture resistance is significantly improved. . Further, since the bonding pad is connected so as to bite into the bonding wire, there is an effect that the adhesive strength thereof is improved.

【図面の簡単な説明】[Brief description of drawings]

【図１】（ａ），（ｂ）は本発明の第１の実施例の縦断
面図と平面図である。1A and 1B are a vertical sectional view and a plan view of a first embodiment of the present invention.

【図２】本発明の第２の実施例の平面図である。FIG. 2 is a plan view of a second embodiment of the present invention.

【図３】（ａ），（ｂ）は従来例の縦断面図と平面図で
ある。3A and 3B are a vertical sectional view and a plan view of a conventional example.

【符号の説明】 １ 第１アルニニウム膜 ２ 層間膜 ３ カバー膜 ４ 第２アルミニウム膜 ５ ボンディングワイヤ ６ 半導体基板[Explanation of reference numerals] 1 first aluminum film 2 interlayer film 3 cover film 4 second aluminum film 5 bonding wire 6 semiconductor substrate

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】 半導体基板上にボンディングワイヤと接
続されるボンディングパッドを有する半導体集積回路装
置において、ボンディングパッドは下位層と上位層の２
層から成り、上位層がボンディングワイヤとの接着領域
よりも小さい範囲に円環状の凸パターンを有し、その凸
パターンの外周部までカバー膜で覆われていることを特
徴とする半導体集積回路装置。1. In a semiconductor integrated circuit device having a bonding pad connected to a bonding wire on a semiconductor substrate, the bonding pad includes a lower layer and an upper layer.
The semiconductor integrated circuit device is characterized in that the upper layer has an annular convex pattern in an area smaller than the bonding area with the bonding wire, and the outer peripheral portion of the convex pattern is covered with a cover film. .
JP4217581A 1992-08-17 1992-08-17 Semiconductor integrated circuit device Pending JPH0669270A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4217581A JPH0669270A (en) 1992-08-17 1992-08-17 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4217581A JPH0669270A (en) 1992-08-17 1992-08-17 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPH0669270A true JPH0669270A (en) 1994-03-11

Family

ID=16706528

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4217581A Pending JPH0669270A (en) 1992-08-17 1992-08-17 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPH0669270A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7176576B2 (en) * 2000-03-03 2007-02-13 Micron Technology, Inc. Conductive connection forming methods, oxidation reducing methods, and integrated circuits formed thereby
US7982254B2 (en) 2005-07-04 2011-07-19 Fujitsu Semiconductor Limited Semiconductor device and method of fabricating the same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7176576B2 (en) * 2000-03-03 2007-02-13 Micron Technology, Inc. Conductive connection forming methods, oxidation reducing methods, and integrated circuits formed thereby
US7220663B2 (en) 2000-03-03 2007-05-22 Micron Technology, Inc. Conductive connection forming methods, oxidation reducing methods, and integrated circuits formed thereby
US7329607B2 (en) 2000-03-03 2008-02-12 Micron Technology, Inc. Conductive connection forming methods, oxidation reducing methods, and integrated circuits formed thereby
US7982254B2 (en) 2005-07-04 2011-07-19 Fujitsu Semiconductor Limited Semiconductor device and method of fabricating the same

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