JPH0659090B2 - Frequency-voltage conversion circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency-voltage conversion circuit, and more specifically, a horizontal and vertical deflection circuit of a video display device which automatically follows the frequency of an input signal. The present invention relates to a frequency-voltage conversion circuit used for the above.

[Conventional technology]

In a video display device such as a television receiver, both vertical and horizontal synchronizing signals are detected by frequency separation, and an image is displayed with this as a reference. Therefore, in a device of a type that performs a display operation by following the frequency of the input synchronization signal, a frequency-voltage conversion circuit that converts the frequency of the input synchronization signal into a voltage using a so-called self-propelled oscillator is used. .

FIG. 4 is a circuit diagram showing a configuration of such a conventional frequency-voltage conversion circuit (hereinafter referred to as an FV conversion circuit).

In the figure, reference numeral 1 is a one-shot multivibrator, a synchronizing signal is input to its signal input terminal IN, and a signal output terminal
A pulse signal is output from OUT.

The cycle of the output pulse signal of the one-shot multivibrator 1 is determined by the oscillation time constant circuit composed of the resistor 2 and the capacitor 3.

The output pulse signal of the one-shot multivibrator 1 is divided by the voltage dividing resistors 4 and 5 and given to the base of the output transistor 6.

A predetermined voltage is applied to the collector of the output transistor 6 via the load resistor 7. Further, this collector is connected to the frequency separation output terminal VO via the integration time constant resistor 8 and is also grounded via the integration time constant capacitor 9.

The emitter of the output transistor 6 is directly grounded.

The operation of the conventional FV conversion circuit having such a configuration is as follows.

When a synchronizing signal is input from the synchronizing signal input terminal FI to the signal input terminal IN of the one-shot multivibrator 1, a rectangular pulse signal having a pulse width determined by the resistor 2 and the capacitor 3 is output as a signal of the one-shot multivibrator 1. Output from the terminal OUT. This rectangular pulse signal is divided by the voltage dividing resistors 4 and 5 and then applied to the base of the output transistor 6.

Since a predetermined voltage is applied to the collector of the output transistor 6 via the load resistor 7, when the output transistor 6 is in the conductive state, that is, the high level of the rectangular pulse output from the one-shot multivibrator 1. In the section, the voltage applied to the collector of the output transistor 6 is discharged to the ground terminal via the output transistor 6. In other words, the predetermined voltage applied to the collector of the output transistor 6 is integrated by the integration time constant resistor 8 and the integration time constant capacitor 9 in the low level section of the rectangular pulse output from the one-shot multivibrator 1.

Now, the pulse width (width of the high level section) of the rectangular pulse output from the one-shot multivibrator 1 is constant due to the action of the resistor 2 and the capacitor 3, and the number of pulses corresponds to the frequency of the input synchronizing signal. Therefore, the duty in each one cycle of the pulse signal changes. As a result, the ratio between the charging time and the discharging time of the integration time constant capacitor 9 changes, and as a result, the signal input terminal IN of the one-shot multivibrator 1 is changed.
The frequency of the synchronizing signal input to is detected at the frequency separation output terminal VO as a change in the voltage across the integration time constant capacitor 9.

[Problems to be solved by the invention]

In the conventional FV conversion circuit as described above, when the horizontal sync signal is not input during the period of the vertical sync signal (its duration is longer than that of the horizontal sync signal), the output is dominated by the vertical sync signal. As a result, an abnormality occurs in the FV conversion output of the horizontal sync signal. Further, in order to eliminate the influence of noise, it is necessary to set a large integration time constant, but in this case, there is a problem that the responsiveness deteriorates.

The present invention has been made in view of such circumstances,
An object of the present invention is to provide a frequency-voltage conversion circuit capable of quick response to a frequency change of an input signal and capable of sufficiently eliminating noise by devising software for performing pulse counting by a microcomputer. And

[Means for solving problems]

The frequency-voltage conversion circuit of the present invention counts the frequencies of the input vertical and horizontal synchronizing signals by a microcomputer, D / A converts the result and outputs a voltage signal, and counts the frequencies of both synchronizing signals. The results are classified, and when the frequency of each classification result is high, the effect of noise generation is eliminated by setting it as a new counting result of the frequency.

[Action]

In the frequency-voltage conversion circuit of the present invention, the count value of the frequency of the input vertical and horizontal synchronizing signals is D / A converted and the voltage signal is output, and when noise occurs, the count result is excluded. To be done.

Example of Invention

Hereinafter, the present invention will be described in detail with reference to the drawings showing its embodiments.

FIG. 1 is a circuit diagram showing a configuration of a frequency-voltage conversion circuit (hereinafter referred to as an FV conversion circuit) of the present invention, which includes a CPU, a ROM, and a RA.
It is composed of a microcomputer 11 including M, latch circuits 12 and 13, D / A converters 14 and 15, and the like.

The microcomputer 11 is provided with two input terminals I ₁ and I ₂ , and a horizontal synchronizing signal is supplied to the first input terminal I ₁ .
The second input terminal I ₂ and the vertical synchronizing signal is inputted, while operating as a frequency counting means for counting the frequency of these two synchronization signals, eliminating noise mixed in the frequency counting, as described below It also has the function to do.

From the output terminals Q _{1 to} Q _{n of} this microcomputer 11, F-
Data for V conversion is output, and trigger pulses for the latch circuits 12 and 13 are output from T ₁ and T ₂ , respectively.

The output terminals Q _{1 to} Q _n of the microcomputer 11 are connected to the input terminals D _{1 to} D _n of the latch circuits 12 and 13, and the output terminals T ₁ and T _{2 of the} microcomputer 11 are also connected to the trigger terminal T. Are connected respectively. Both latch circuits 1
From the 2 and 13 output terminals Q _{1 to} Q _n , the respective input terminals D _{1 to} D _n
The FV conversion data input to and latched at is output.

Output terminals Q _{1 to} Q _n of both latch circuits 12 and 13 are connected to the input terminals D _{1 to} D _n of both D / A converters 14 and 15, respectively, and a voltage signal is output from each output terminal O. It

FIG. 2 is a schematic diagram showing a method of counting vertical synchronizing signals and horizontal synchronizing signals by the microcomputer 11.

Specifically, the vertical synchronizing signal shown in FIG. 3A is input to the input terminal I ₂ of the microcomputer 11, and the horizontal synchronizing signal shown in FIG. 3C is input to the input terminal I ₁ of the microcomputer 11. .

Inside the microcomputer 11, the frequencies of the vertical synchronizing signal and the horizontal synchronizing signal are respectively counted by using the internal pulse of FIG. 2 (b) depending on the system clock which is the operation reference. That is, the frequency of the vertical synchronizing signal is counted by counting the number of internal pulses of the microcomputer 11 in one cycle of the vertical synchronizing signal input to the input terminal I ₂ of the microcomputer 11, and A certain period P in the cycle is specified by an internal pulse of the microcomputer 11, and the input terminal is input during that period.
The frequency of the horizontal synchronizing signal is counted by counting the number of pulses of the horizontal synchronizing signal input to I ₁ .

FIG. 3 is a flowchart showing a processing procedure for D / A converting the frequencies of the vertical synchronizing signal and the horizontal synchronizing signal counted as described above while eliminating noise.

The procedure for processing the counting result will be described below with reference to the flowchart of FIG. Although the flowchart of FIG. 3 shows the processing procedure regarding the horizontal synchronizing signal,
The processing procedure of the vertical synchronizing signal is similar.

The counting of the horizontal synchronizing signal and the processing of the result are performed in synchronization with the vertical synchronizing signal. When the counting of the frequency of the horizontal synchronizing signal is completed, the counting result is stored as the count value COUNT2. The count value COUNT1 is the previous count value.

Next, the count value COUNT2 is compared with the previous count value COUNT1,
As a result, if they are the same, the loop pass counter CT0 is incremented by 1. After this, loop pass counter CT
0 is compared with the constant A (A> S). As a result, when it is determined that CT0 ≧ A, the counters CT1, CT2, ... CTn, CTX are cleared, and when it is determined that CT0 <A, the counting result of the horizontal synchronization signal is directly calculated. Return to the process of storing in the numerical value COUNT2. As a result, each time the vertical synchronization signal is input to the microcomputer 11 A + 1 times, each counter CT1, CT2,
… CTn and CTX are cleared.

In the above processing, the current count value COUNT2 is the previous count value COUNT1
That is, the frequency of the input horizontal synchronizing signal is constant and does not change. In this case, data output and latch output from the microcomputer 11 to the latch circuit 12 are not performed. That is, at the time of counting the previous count value COUNT1 or before that, the data provided to the latch circuit 12 from the microcomputer 11 and latched is still valid, and the voltage signal output from the D / A converter 14 is constant. Maintained.

On the other hand, when both count value COUNT1 and count value COUNT2 are different,
The current count value COUNT2 is sequentially changed to COUNT1-1, COUNT1 + 1, COUNT1
By comparing with +2, ... COUNT1 + n, the counters CT1, CT2, ... CTn corresponding to the values judged to be equal are incremented by 1, and if neither, the counter CTX is incremented by 1 The count value COUNT2 is classified.

Next, one of the counters CT1, CT2, ..., CTn, CTX incremented by 1 in the above-described processing is compared with a predetermined threshold value S, and if the result is that the counter value is larger than the threshold value S, all After clearing the counters CT1, CT2, ... CTn, CTX, the current count value COUNT2 is stored as the previous count value COUNT1.

Then, the above-mentioned count value COUNT1 is decoded to create data for D / A conversion, and this is given to the latch circuit 12 to be latched. The data latched in the latch circuit 12 is converted into an analog signal, that is, a voltage signal by the D / A converter 14, and is output from the output terminal O.

That is, as described above, the current count value COUNT2 is the previous count value COUN
If it is different from T1, the counter CT1 corresponding to that value
(Or CT2, ... CTn, CTX are incremented by 1 and when the value reaches the threshold value S, all counters CT1, CT
2, ... Count value COUNT at that point after CTn and CTX are cleared
Data corresponding to 2 is applied from the microcomputer 11 to the latch circuit 12 and latched, and the analog-converted voltage signal is output from the D / A converter 14.

The value of the counter CT1 (or CT2, ... CTn, CTX) is the threshold value S.
In the following cases, the process goes to the process in which the loop passage counter CT0 is incremented by 1, and the same process as in the case where the count value COUNT2 and the count value COUNT1 are equal is performed.

By the way, when noise occurs, the current count value COUNT2 and the previous count value COUNT1 naturally differ. In this case, since the count value COUNT2 generally changes randomly each time, the incremented counters CT1, CT2, ... CTn, CTX are different each time. In other words, since the increment of each counter due to the noise occurrence is distributed, the value of any one of the specific counters CT1, CT2, ... CTn, CTX may be significantly increased during the processing of A + 1 times. The probability is very low. However, when the frequency of the input signal actually changes, not due to noise, the value of one of the counters corresponding to the frequency after the change will be processed at maximum A + 1 times. Increase significantly during. As a result, since the value of the counter exceeds the threshold value S, it can be determined that it is not noise.

That is, noise can be eliminated by preparing a sufficient number of counters CT1, CT2, ... CTn, CTX.

Further, since the data for analog output of the D / A converter 14 is latched in the latch circuit 12, even if there is no horizontal synchronizing signal in the output period of the vertical synchronizing signal, the horizontal synchronizing from the D / A converter 14 is performed. The output of the voltage signal corresponding to the signal is maintained.

The procedure of counting the frequency of the vertical synchronizing signal is replaced with the counting of the horizontal synchronizing signal at the time of counting the frequency of the horizontal synchronizing signal shown in FIG. If the internal pulse is to be counted, the processing procedure is exactly the same.

〔The invention's effect〕

As described above in detail, according to the FV conversion circuit of the present invention, a time constant circuit composed of a resistor, a capacitor, etc. is not required, so that it is stable against temperature changes and noise is eliminated. Since the processing to obtain is adopted, a stable FV conversion circuit can be obtained against noise.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of an embodiment of an FV conversion circuit according to the present invention, and FIG. 2 is a timing chart showing a relationship between a vertical synchronizing signal and a horizontal synchronizing signal to be processed and a pulse used for counting them. FIG. 3 is a flowchart showing a processing procedure by the device of the present invention, and FIG. 4 is a circuit diagram showing a configuration of a conventional FV conversion circuit. 11 …… Microcomputer, 12,13 …… Latch circuit, 1
4,15 ...... D / A converter In the figures, the same symbols indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A frequency-voltage conversion circuit of a video display device for converting and outputting a voltage signal corresponding to each of the frequencies of an input vertical and horizontal synchronizing signal, wherein a reference pulse generating circuit and one cycle of the vertical synchronizing signal are provided. First frequency counting means for counting the number of reference pulses in between, means for obtaining frequency-voltage conversion data for the vertical synchronizing signal corresponding to the counting result, and a predetermined period within one cycle of the vertical synchronizing signal. Second for counting the number of pulses of the horizontal synchronizing signal based on the reference pulse
Frequency counting means, means for obtaining horizontal synchronizing signal frequency-voltage conversion data corresponding to this counting result, and means for classifying and counting the counting results of the first and second frequency counting means. A microcomputer for correcting the frequency-voltage conversion data based on the count value of the frequency counting means corresponding to the count means when the count value of the counting means exceeds a predetermined value; Frequency-voltage conversion, comprising: a latch circuit that latches a frequency-voltage conversion output of a computer; and a D / A converter that converts the data latched in the latch circuit into a voltage signal and outputs the voltage signal. circuit.